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d="scan'208";a="107099650" Received: from ettammin-mobl2.ger.corp.intel.com (HELO localhost) ([10.245.246.80]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Oct 2024 07:45:34 -0700 From: Jani Nikula To: Suraj Kandpal , intel-xe@lists.freedesktop.org Cc: uma.shankar@intel.com, jouni.hogander@intel.com, Suraj Kandpal Subject: Re: [PATCH] drm/i915/psr: Implement WA to help reach PC10 In-Reply-To: <20241006164934.1689930-2-suraj.kandpal@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20241003145337.1673715-2-suraj.kandpal@intel.com> <20241006164934.1689930-2-suraj.kandpal@intel.com> Date: Wed, 09 Oct 2024 17:45:31 +0300 Message-ID: <87o73t8hdg.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Sun, 06 Oct 2024, Suraj Kandpal wrote: > To reach PC10 when PKG_C_LATENCY is configure we must do the following > things > 1) Enter PSR1 only when delayed_vblank < 6 lines and DC5 can be entered > 2) Allow PSR2 deep sleep when DC5 can be entered > 3) DC5 can be entered when all transocoder have either PSR1, PSR2 or > eDP 1.5 PR ALPM enabled and VBI is disabled and flips and pushes are > not happening. > > --v2 > -Add debug prints > > WA: 22019444797 > Signed-off-by: Suraj Kandpal > --- > drivers/gpu/drm/i915/display/intel_ddi.c | 3 + > .../drm/i915/display/intel_display_types.h | 3 + > drivers/gpu/drm/i915/display/intel_psr.c | 117 +++++++++++++++++- > drivers/gpu/drm/i915/display/intel_psr.h | 2 + > 4 files changed, 124 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c > index fe1ded6707f9..cbd71c136c8d 100644 > --- a/drivers/gpu/drm/i915/display/intel_ddi.c > +++ b/drivers/gpu/drm/i915/display/intel_ddi.c > @@ -4368,6 +4368,9 @@ static int intel_ddi_compute_config_late(struct intel_encoder *encoder, > port_sync_transcoders & ~BIT(crtc_state->cpu_transcoder); > } > > + if (intel_encoder_is_dp(encoder)) > + intel_psr_compute_config_late(encoder, crtc_state); > + > return 0; > } > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h > index 17fc21f6ae36..7fb3eeb0e0f2 100644 > --- a/drivers/gpu/drm/i915/display/intel_display_types.h > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h > @@ -1576,6 +1576,9 @@ struct intel_psr { > #define I915_PSR_DEBUG_PANEL_REPLAY_DISABLE 0x40 > > u32 debug; > + bool is_dpkgc_configured; > + bool is_dc5_entry_possible; > + bool is_wa_delayed_vblank_limit; > bool sink_support; > bool source_support; > bool enabled; > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c > index 8e9f068b9b2b..9b77045df228 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.c > +++ b/drivers/gpu/drm/i915/display/intel_psr.c > @@ -26,6 +26,7 @@ > #include > #include > #include > +#include > > #include "i915_drv.h" > #include "i915_reg.h" > @@ -896,6 +897,82 @@ static u8 psr_compute_idle_frames(struct intel_dp *intel_dp) > return idle_frames; > } > > +static bool > +intel_psr_check_wa_delayed_vblank(const struct drm_display_mode *adjusted_mode) > +{ > + return (adjusted_mode->crtc_vblank_start - adjusted_mode->crtc_vdisplay) >= 6; > +} > + > +/* > + * PKG_C_LATENCY is configured only when DISPLAY_VER >= 20 and > + * VRR is not enabled > + */ > +static bool intel_psr_is_dpkgc_configured(struct intel_display *display, > + struct intel_crtc_state *crtc_state) > +{ > + if (DISPLAY_VER(display) < 20 || crtc_state->vrr.enable) > + return false; > + > + return true; > +} > + > +static bool wa_22019444797_psr1_check(const struct intel_crtc_state *crtc_state, > + struct intel_psr *psr) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + > + if (DISPLAY_VER(display) == 20 && psr->is_dpkgc_configured && > + (psr->is_wa_delayed_vblank_limit || !psr->is_dc5_entry_possible) && > + !crtc_state->has_sel_update && !crtc_state->has_panel_replay) { > + drm_dbg_kms(display->drm, > + "Wa 22019444797 requirement met PSR1 disabled\n"); > + return true; > + } else { > + return false; > + } > +} > + > +/* > + * DC5 entry is only possible if vblank interrupt is disabled > + * and either psr1, psr2, edp 1.5 pr alpm is enabled on all > + * enabled encoders. > + */ > +static bool > +intel_psr_is_dc5_entry_possible(struct intel_display *display, > + struct intel_crtc_state *crtc_state) > +{ > + struct intel_crtc *intel_crtc; > + > + if ((display->power.domains.target_dc_state & > + DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0) > + return false; > + > + if (!crtc_state->has_psr && !crtc_state->has_sel_update && > + !crtc_state->has_panel_replay) > + return false; > + > + for_each_intel_crtc(display->drm, intel_crtc) { > + struct drm_crtc *crtc = &intel_crtc->base; > + struct drm_vblank_crtc *vblank; > + struct intel_encoder *encoder; > + > + if (!intel_crtc->active) > + continue; > + > + vblank = drm_crtc_vblank_crtc(crtc); > + > + if (vblank->enabled) > + return false; > + > + for_each_encoder_on_crtc(display->drm, crtc, encoder) > + if (encoder->type != INTEL_OUTPUT_EDP || > + !CAN_PSR(enc_to_intel_dp(encoder))) > + return false; > + } > + > + return true; > +} > + > static void hsw_activate_psr1(struct intel_dp *intel_dp) > { > struct intel_display *display = to_intel_display(intel_dp); > @@ -1008,7 +1085,18 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp) > u32 val = EDP_PSR2_ENABLE; > u32 psr_val = 0; > > - val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > + /* > + * Wa_22019444797 > + * TODO: Disable idle frames when vblank gets enabled while > + * PSR2 is enabled > + */ > + if (DISPLAY_VER(dev_priv) != 20 || > + !intel_dp->psr.is_dpkgc_configured || > + intel_dp->psr.is_dc5_entry_possible) > + val |= EDP_PSR2_IDLE_FRAMES(psr_compute_idle_frames(intel_dp)); > + else > + drm_dbg_kms(display->drm, > + "Wa 22019444797 requirement met PSR2 deep sleep disabled\n"); > > if (DISPLAY_VER(display) < 14 && !IS_ALDERLAKE_P(dev_priv)) > val |= EDP_SU_TRACK_ENABLE; > @@ -1686,6 +1774,24 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, > crtc_state->has_sel_update = intel_sel_update_config_valid(intel_dp, crtc_state); > } > > +void intel_psr_compute_config_late(struct intel_encoder *intel_encoder, > + struct intel_crtc_state *crtc_state) > +{ > + struct intel_display *display = to_intel_display(intel_encoder); > + struct intel_dp *dp = enc_to_intel_dp(intel_encoder); > + > + if (DISPLAY_VER(display) == 20) { > + mutex_lock(&dp->psr.lock); > + dp->psr.is_dpkgc_configured = > + intel_psr_is_dpkgc_configured(display, crtc_state); > + dp->psr.is_dc5_entry_possible = > + intel_psr_is_dc5_entry_possible(display, crtc_state); > + dp->psr.is_wa_delayed_vblank_limit = > + intel_psr_check_wa_delayed_vblank(&crtc_state->hw.adjusted_mode); Compute config should only change the crtc state. BR, Jani. > + mutex_unlock(&dp->psr.lock); > + } > +} > + > void intel_psr_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > @@ -2742,6 +2848,7 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, > * - Changing between PSR versions > * - Region Early Transport changing > * - Display WA #1136: skl, bxt > + * - Display WA_22019444797 > */ > needs_to_disable |= intel_crtc_needs_modeset(new_crtc_state); > needs_to_disable |= !new_crtc_state->has_psr; > @@ -2751,6 +2858,8 @@ void intel_psr_pre_plane_update(struct intel_atomic_state *state, > psr->su_region_et_enabled; > needs_to_disable |= DISPLAY_VER(i915) < 11 && > new_crtc_state->wm_level_disabled; > + /* TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled */ > + needs_to_disable |= wa_22019444797_psr1_check(new_crtc_state, psr); > > if (psr->enabled && needs_to_disable) > intel_psr_disable_locked(intel_dp); > @@ -2791,6 +2900,12 @@ void intel_psr_post_plane_update(struct intel_atomic_state *state, > keep_disabled |= DISPLAY_VER(display) < 11 && > crtc_state->wm_level_disabled; > > + /* > + * Wa_22019444797 > + * TODO: Disable PSR1 when vblank gets enabled while PSR1 is enabled > + */ > + keep_disabled |= wa_22019444797_psr1_check(crtc_state, psr); > + > if (!psr->enabled && !keep_disabled) > intel_psr_enable_locked(intel_dp, crtc_state); > else if (psr->enabled && !crtc_state->wm_level_disabled) > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h > index 5f26f61f82aa..e0fa04952393 100644 > --- a/drivers/gpu/drm/i915/display/intel_psr.h > +++ b/drivers/gpu/drm/i915/display/intel_psr.h > @@ -47,6 +47,8 @@ void intel_psr_init(struct intel_dp *intel_dp); > void intel_psr_compute_config(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state, > struct drm_connector_state *conn_state); > +void intel_psr_compute_config_late(struct intel_encoder *intel_encoder, > + struct intel_crtc_state *crtc_state); > void intel_psr_get_config(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config); > void intel_psr_irq_handler(struct intel_dp *intel_dp, u32 psr_iir); -- Jani Nikula, Intel