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* [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY
@ 2024-06-26  5:00 Ankit Nautiyal
  2024-06-26  5:00 ` [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Ankit Nautiyal
                   ` (12 more replies)
  0 siblings, 13 replies; 26+ messages in thread
From: Ankit Nautiyal @ 2024-06-26  5:00 UTC (permalink / raw)
  To: intel-gfx, intel-xe
  Cc: jani.nikula, ville.syrjala, mika.kahola, matthew.d.roper

The HDMI PLL programming involves pre-calculated values for specific
frequencies and an algorithm to compute values for other frequencies.
While the algorithm itself wasn't part of the driver, tables were
added based on it for known modes.

Some HDMI modes were pruned due to lack of support (for example issues
[1],[2], and [3]).
This series adds the algorithm for computing HDMI PLLs for SNPS/C10PHY
to work with all modes supported by the hardware.

The original algorithm uses floating-point math, which has been
converted to integers while preserving precision. As a result,
the values in the existing computable tables are very close but not
exact. Testing with DG2 and MTL on various panels revealed no issues.

[1] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/9722
[2] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10654
[3] https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/10956

Ankit Nautiyal (5):
  drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2
  drm/i915/snps_phy: Use HDMI PLL algorithm for DG2
  drm/i915/cx0_phy_regs: Add C10 registers bits
  drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm
  drm/xe: Add intel_pll_algorithm in Makefile

 drivers/gpu/drm/i915/Makefile                 |   1 +
 drivers/gpu/drm/i915/display/intel_cx0_phy.c  |  15 +
 .../gpu/drm/i915/display/intel_cx0_phy_regs.h |  24 ++
 .../drm/i915/display/intel_pll_algorithm.c    | 317 ++++++++++++++++++
 .../drm/i915/display/intel_pll_algorithm.h    |  41 +++
 drivers/gpu/drm/i915/display/intel_snps_phy.c |  20 +-
 drivers/gpu/drm/xe/Makefile                   |   1 +
 7 files changed, 407 insertions(+), 12 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_pll_algorithm.c
 create mode 100644 drivers/gpu/drm/i915/display/intel_pll_algorithm.h

-- 
2.40.1


^ permalink raw reply	[flat|nested] 26+ messages in thread

end of thread, other threads:[~2024-06-28  5:06 UTC | newest]

Thread overview: 26+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2024-06-26  5:00 [PATCH 0/5] Add HDMI PLL Algorithm for SNPS/C10PHY Ankit Nautiyal
2024-06-26  5:00 ` [PATCH 1/5] drm/i915/display: Add support for SNPS PHY HDMI PLL algorithm for DG2 Ankit Nautiyal
2024-06-26 10:04   ` Jani Nikula
2024-06-27 16:41     ` Nautiyal, Ankit K
2024-06-26 18:12   ` kernel test robot
2024-06-26 18:46   ` kernel test robot
2024-06-26  5:00 ` [PATCH 2/5] drm/i915/snps_phy: Use " Ankit Nautiyal
2024-06-26 10:07   ` Jani Nikula
2024-06-27 17:02     ` Nautiyal, Ankit K
2024-06-27 18:30       ` Jani Nikula
2024-06-28  5:06         ` Nautiyal, Ankit K
2024-06-26  5:00 ` [PATCH 3/5] drm/i915/cx0_phy_regs: Add C10 registers bits Ankit Nautiyal
2024-06-26  5:00 ` [PATCH 4/5] drm/i915/pll_algorithm: Compute C10 HDMI PLLs with algorithm Ankit Nautiyal
2024-06-26 10:10   ` Jani Nikula
2024-06-27 17:08     ` Nautiyal, Ankit K
2024-06-26  5:00 ` [PATCH 5/5] drm/xe: Add intel_pll_algorithm in Makefile Ankit Nautiyal
2024-06-26 10:12   ` Jani Nikula
2024-06-27 17:12     ` Nautiyal, Ankit K
2024-06-26  5:05 ` ✓ CI.Patch_applied: success for Add HDMI PLL Algorithm for SNPS/C10PHY Patchwork
2024-06-26  5:05 ` ✗ CI.checkpatch: warning " Patchwork
2024-06-26  5:06 ` ✓ CI.KUnit: success " Patchwork
2024-06-26  5:18 ` ✓ CI.Build: " Patchwork
2024-06-26  5:20 ` ✗ CI.Hooks: failure " Patchwork
2024-06-26  5:22 ` ✗ CI.checksparse: warning " Patchwork
2024-06-26  5:44 ` ✓ CI.BAT: success " Patchwork
2024-06-26  7:06 ` ✓ CI.FULL: " Patchwork

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