RE: [PATCH v3 05/15] drm/xe/xe3p_lpg: Add MCR steering

Bhadane, Dnyaneshwar
2026-02-09T05:34:12Z

> -----Original Message-----
> From: Sousa, Gustavo <gustavo.sousa@intel.com>
> Sent: Saturday, February 7, 2026 12:06 AM
> To: intel-xe@lists.freedesktop.org; intel-gfx@lists.freedesktop.org
> Cc: Sousa, Gustavo <gustavo.sousa@intel.com>; Roper, Matthew D
> <matthew.d.roper@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>
> Subject: [PATCH v3 05/15] drm/xe/xe3p_lpg: Add MCR steering
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> Xe3p_LPG has nearly identical steering to Xe2 and Xe3. The only DSS/XeCore
> change from those IPs is an additional range from 0xDE00-0xDE7F that was
> previously reserved, so we can simply grow one of the existing ranges in the
> Xe2 table to include it. Similarly, the "instance0" table is also almost identical,
> but gains one additional PSMI range and requires a separate table.
>
> v2:
> - Drop reserved range from MEMPIPE range. (Dnyaneshwar)
>
> Bspec: 75242
> Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Gustavo Sousa <gustavo.sousa@intel.com>

Thanks for the update.

LGTM,
Reviewed-by: Dnyaneshwar Bhadane <dnyaneshwar.bhadane@intel.com>

> ---
> drivers/gpu/drm/xe/xe_gt_mcr.c | 18 +++++++++++++++++-
> 1 file changed, 17 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c
> b/drivers/gpu/drm/xe/xe_gt_mcr.c index 7c1fe9ac120d..da8f6187f893
> 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -201,7 +201,7 @@ static const struct xe_mmio_range
> xe2lpg_dss_steering_table[] = {
> { 0x009680, 0x0096FF }, /* DSS */
> { 0x00D800, 0x00D87F }, /* SLICE */
> { 0x00DC00, 0x00DCFF }, /* SLICE */
> - { 0x00DE80, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
> + { 0x00DE00, 0x00E8FF }, /* DSS (0xE000-0xE0FF reserved) */
> { 0x00E980, 0x00E9FF }, /* SLICE */
> { 0x013000, 0x0133FF }, /* DSS (0x13000-0x131FF), SLICE
> (0x13200-0x133FF) */
> {},
> @@ -280,6 +280,19 @@ static const struct xe_mmio_range
> xe3p_xpc_instance0_steering_table[] = {
> {},
> };
>
> +static const struct xe_mmio_range xe3p_lpg_instance0_steering_table[] = {
> + { 0x004000, 0x004AFF }, /* GAM, rsvd, GAMWKR */
> + { 0x008700, 0x00887F }, /* NODE */
> + { 0x00B000, 0x00B3FF }, /* NODE, L3BANK */
> + { 0x00B500, 0x00B6FF }, /* PSMI */
> + { 0x00C800, 0x00CFFF }, /* GAM */
> + { 0x00D880, 0x00D8FF }, /* NODE */
> + { 0x00DD00, 0x00DD7F }, /* MEMPIPE */
> + { 0x00F000, 0x00FFFF }, /* GAM, GAMWKR */
> + { 0x013400, 0x0135FF }, /* MEMPIPE */
> + {},
> +};
> +
> static void init_steering_l3bank(struct xe_gt *gt) {
> struct xe_device *xe = gt_to_xe(gt);
> @@ -533,6 +546,9 @@ void xe_gt_mcr_init_early(struct xe_gt *gt)
> gt->steering[INSTANCE0].ranges =
> xe3p_xpc_instance0_steering_table;
> gt->steering[L3BANK].ranges =
> xelpg_l3bank_steering_table;
> gt->steering[NODE].ranges =
> xe3p_xpc_node_steering_table;
> + } else if (GRAPHICS_VERx100(xe) >= 3510) {
> + gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
> + gt->steering[INSTANCE0].ranges =
> xe3p_lpg_instance0_steering_table;
> } else if (GRAPHICS_VER(xe) >= 20) {
> gt->steering[DSS].ranges = xe2lpg_dss_steering_table;
> gt->steering[SQIDI_PSMI].ranges =
> xe2lpg_sqidi_psmi_steering_table;
>
> --
> 2.52.0