From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5C26CEB64D9 for ; Mon, 10 Jul 2023 05:57:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E266010E0EC; Mon, 10 Jul 2023 05:57:43 +0000 (UTC) Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9405E10E0EC for ; Mon, 10 Jul 2023 05:57:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1688968662; x=1720504662; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=ZW+F0uCbvRgctn9+o+Bq45s3ja8raaPuqyBHgF2H7Lo=; b=WNGUMkb+smoqKi5tmredoMbReSZ4JkC9bSHDLDGXKYPjw9T7ccGuEhTn O7PylLKVtD5KbG2RnyY2i0DHhbf82y8BZSLjBoNn8zXZf5BVIZimvGRTF 0qNsnYRMGXKRVY+ISAKJOIWJrLtCZdwCU0Xd/ExyBlW04wxe5hh/O8KNP jkaUWDXh1M2e43mDYpxjd/+/wVhE221MkUDIHwar+QVszgAuRS8lQmI54 Vt5JyR/+qje/yItoNXh9/+YagZDTEN9ZtYd87o7P3GP9mrlMZ/bHWCi0q p+9weonLt4TRSBc8FdHDX4tv8rn75NvmNylB9FqwAW4DvZQTXfEmuu9hn g==; X-IronPort-AV: E=McAfee;i="6600,9927,10766"; a="450621906" X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="450621906" Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2023 22:57:41 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=McAfee;i="6600,9927,10766"; a="894663544" X-IronPort-AV: E=Sophos;i="6.01,194,1684825200"; d="scan'208";a="894663544" Received: from adixit-mobl.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.212.175.176]) by orsmga005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Jul 2023 22:57:40 -0700 Date: Sun, 09 Jul 2023 22:57:40 -0700 Message-ID: <87wmz8gvfv.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: "Iddamsetty, Aravind" In-Reply-To: References: <20230627122113.1472532-1-aravind.iddamsetty@intel.com> <20230627122113.1472532-3-aravind.iddamsetty@intel.com> <87mt09daqu.wl-ashutosh.dixit@intel.com> <87a5w8cvmr.wl-ashutosh.dixit@intel.com> <04ae6811-9bc1-c66d-6cb8-640bfd8a9c7b@intel.com> <87y1jphqlm.wl-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Subject: Re: [Intel-xe] [PATCH v2 2/2] drm/xe/pmu: Enable PMU interface X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah , intel-xe@lists.freedesktop.org, Tvrtko Ursulin Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Sun, 09 Jul 2023 21:13:59 -0700, Iddamsetty, Aravind wrote: > > On 09-07-2023 06:02, Dixit, Ashutosh wrote: > > On Thu, 06 Jul 2023 20:53:47 -0700, Iddamsetty, Aravind wrote: > >> On 07-07-2023 07:48, Dixit, Ashutosh wrote: > >>> On Thu, 06 Jul 2023 06:42:29 -0700, Iddamsetty, Aravind wrote: > >>> Also, could you please explain where the requirement to expose these OAG > >>> group busy/free registers via the PMU is coming from? Since these are OA > >>> registers presumably they can be collected using the OA subsystem. > >> > >> L0 sysman needs this > >> https://spec.oneapi.io/level-zero/latest/sysman/api.html#zes-engine-properties-t > >> and xpumanager uses this > >> https://github.com/intel/xpumanager/blob/master/core/src/device/gpu/gpu_device.cpp > > > > Also there is the above mentioned open regarding this: "Since these are OA > > registers presumably they can be collected using the OA subsystem". L0 now > > seems to be supporting OA and we are going to provide an OA subsystem for > > xe. This probably also needs arch input. > > While I try to check on this, by any chance do you know why we have to > go with custom OA subsystem implementation and cannot use PMU for > reporting OA. Because we already had a big OA subsystem in i915 (i915_perf.c) which we are bringing over to xe. And OA has many more metrics than just the few we are exposing (or had exposed via the PMU). You can see these metrics in build/lib directory of the IGT build (after you compile IGT). Grep for busyness. Some of metrics which come from GuC will not be available from OA (since OA data is HW generated) so we will have to expose these separately. Separately, I think it would be good to understand how other drm drivers expose such performance data (such as what we were doing in i915 with OA and PMU) for userland to digest. Let's see. I am not against PMU per se, just asking questions so we can get some opinion about these things before we commit to supporting the PMU interface. Thanks. -- Ashutosh