From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 9CA6FC5473F for ; Tue, 27 Aug 2024 22:25:50 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 65D8910E421; Tue, 27 Aug 2024 22:25:50 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="UnsoZUMv"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4E1D710E421 for ; Tue, 27 Aug 2024 22:25:48 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1724797549; x=1756333549; h=date:message-id:from:to:cc:subject:in-reply-to: references:mime-version; bh=+HugFWC6FXU6d7P+6apHmWbWDGt5tl1Nv2DY2c6jJaA=; b=UnsoZUMvdhqvs842aou+4nz8IySou58szmN81dGjUWzKj3DuB6Nu7Vah r3BxvnnTLVm7GU3bEL3X+ueP6nddhgNL27Uq+cTXsDj4+1EcnRrqKf9hQ wlZLELo4/sDdf39eWSPJnwufceogwmyM8H9tp0Ye1W5giodmOfactk3+s pKMAs2EYbgqxiEWuw1AcqXd0tJ4Azsuosrnr5NwWCppkTroUNa58hwXFS pOCWSl+xTjPs7+VtnCASKPJk29i2SE/GJyI6niObCUW3mLcFXWnlKfBbw S+eVEF3Gcj8y0Aw2ji1mmqovIuWvJxZcw9QwiCVzLONAGUiDmokm65i+7 w==; X-CSE-ConnectionGUID: T4RCz8DkTByfAbtPMf96vQ== X-CSE-MsgGUID: j/fCxfm4RFy9DcydG3WwWg== X-IronPort-AV: E=McAfee;i="6700,10204,11177"; a="45821324" X-IronPort-AV: E=Sophos;i="6.10,181,1719903600"; d="scan'208";a="45821324" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 15:25:49 -0700 X-CSE-ConnectionGUID: 6pSEA/vXQYeBDSIlVnhVlw== X-CSE-MsgGUID: gns1ikxIT+esI953DGZdvQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.10,181,1719903600"; d="scan'208";a="93808863" Received: from shahrach-mobl2.amr.corp.intel.com (HELO adixit-arch.intel.com) ([10.124.96.72]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Aug 2024 15:25:48 -0700 Date: Tue, 27 Aug 2024 15:25:43 -0700 Message-ID: <87zfoxr4bc.wl-ashutosh.dixit@intel.com> From: "Dixit, Ashutosh" To: Matthew Brost Cc: intel-xe@lists.freedesktop.org, Maarten Lankhorst , Michal Wajdeczko Subject: Re: [CI] drm/xe: Replace xe_device_wmb by wmb In-Reply-To: References: <20240826234100.1850471-1-ashutosh.dixit@intel.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?ISO-8859-4?Q?Goj=F2?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 26 Aug 2024 20:03:50 -0700, Matthew Brost wrote: > Hi Matt, > On Mon, Aug 26, 2024 at 04:41:00PM -0700, Ashutosh Dixit wrote: > > CI ONLY for now > > > > In xe_device_wmb(), it is not clear what the purpose of register write > > The comment you delete in this patch does explain this. Hmm doesn't explain, says we need an additional register write, without explaining. Anyway. > IIRC this the equivalent of intel_guc_write_barrier in the i915. intel_guc_write_barrier doesn't seem to have a wmb() for lmem, only for smem, so not sure about that either. > Also IIRC I added that in i915 when working on GuC submission chasing > extreme corner case bugs in stress tests. That being said, I can't say > with 100% certainity that is required on all platforms or our usage in Xe > in is correct. > > > following wmb() is. Replace xe_device_wmb() with just wmb() to see if we > > see any failures in CI. > > > > I would not be comfortable removing this based on CI results. CI is ok, > but typically doesn't catch corner cases bugs which this is supposed to > prevent. To be comfortable removing this I would say CI is green, run a > battery of stress tests on RIL platforms in a loop, and finally confirm > with the hardware team that this in fact is not required. OK, not planning to merge this patch unless you are ok so will just drop it. Thanks. -- Ashutosh > > Matt > > > Signed-off-by: Ashutosh Dixit > > --- > > drivers/gpu/drm/xe/xe_device.c | 18 ------------------ > > drivers/gpu/drm/xe/xe_device.h | 2 -- > > drivers/gpu/drm/xe/xe_guc_ct.c | 2 +- > > drivers/gpu/drm/xe/xe_guc_submit.c | 2 +- > > drivers/gpu/drm/xe/xe_migrate.c | 2 +- > > drivers/gpu/drm/xe/xe_vm.c | 2 +- > > 6 files changed, 4 insertions(+), 24 deletions(-) > > > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > > index b6db7e082d887..f0154281f3eea 100644 > > --- a/drivers/gpu/drm/xe/xe_device.c > > +++ b/drivers/gpu/drm/xe/xe_device.c > > @@ -800,24 +800,6 @@ void xe_device_shutdown(struct xe_device *xe) > > { > > } > > > > -/** > > - * xe_device_wmb() - Device specific write memory barrier > > - * @xe: the &xe_device > > - * > > - * While wmb() is sufficient for a barrier if we use system memory, on discrete > > - * platforms with device memory we additionally need to issue a register write. > > - * Since it doesn't matter which register we write to, use the read-only VF_CAP > > - * register that is also marked as accessible by the VFs. > > - */ > > -void xe_device_wmb(struct xe_device *xe) > > -{ > > - struct xe_gt *gt = xe_root_mmio_gt(xe); > > - > > - wmb(); > > - if (IS_DGFX(xe)) > > - xe_mmio_write32(gt, VF_CAP_REG, 0); > > -} > > - > > /** > > * xe_device_td_flush() - Flush transient L3 cache entries > > * @xe: The device > > diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h > > index f052c06a2d2f5..3be5fa94fa113 100644 > > --- a/drivers/gpu/drm/xe/xe_device.h > > +++ b/drivers/gpu/drm/xe/xe_device.h > > @@ -42,8 +42,6 @@ int xe_device_probe(struct xe_device *xe); > > void xe_device_remove(struct xe_device *xe); > > void xe_device_shutdown(struct xe_device *xe); > > > > -void xe_device_wmb(struct xe_device *xe); > > - > > static inline struct xe_file *to_xe_file(const struct drm_file *file) > > { > > return file->driver_priv; > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c > > index f24dd52239268..5ac610f227d88 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c > > @@ -596,7 +596,7 @@ static int h2g_write(struct xe_guc_ct *ct, const u32 *action, u32 len, > > /* Write H2G ensuring visable before descriptor update */ > > xe_map_memcpy_to(xe, &map, 0, cmd, H2G_CT_HEADERS * sizeof(u32)); > > xe_map_memcpy_to(xe, &map, H2G_CT_HEADERS * sizeof(u32), action, len * sizeof(u32)); > > - xe_device_wmb(xe); > > + wmb(); > > > > /* Update local copies */ > > h2g->info.tail = (tail + full_len) % h2g->info.size; > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > > index fbbe6a487bbb3..bbf7ec0111642 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > > @@ -699,7 +699,7 @@ static void wq_item_append(struct xe_exec_queue *q) > > q->guc->wqi_tail += wqi_size; > > xe_assert(xe, q->guc->wqi_tail <= WQ_SIZE); > > > > - xe_device_wmb(xe); > > + wmb(); > > > > map = xe_lrc_parallel_map(q->lrc[0]); > > parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c > > index cbf54be224c96..06cc1f1e65a1f 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > @@ -1298,7 +1298,7 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m, > > } > > > > trace_xe_vm_cpu_bind(vm); > > - xe_device_wmb(vm->xe); > > + wmb(); > > > > return dma_fence_get_stub(); > > } > > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > > index bfa4880a1673a..975f174df41c9 100644 > > --- a/drivers/gpu/drm/xe/xe_vm.c > > +++ b/drivers/gpu/drm/xe/xe_vm.c > > @@ -3186,7 +3186,7 @@ int xe_vm_invalidate_vma(struct xe_vma *vma) > > > > for_each_tile(tile, xe, id) { > > if (xe_pt_zap_ptes(tile, vma)) { > > - xe_device_wmb(xe); > > + wmb(); > > xe_gt_tlb_invalidation_fence_init(tile->primary_gt, > > &fence[fence_id], > > true); > > -- > > 2.41.0 > >