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From: Julia Filipchuk <julia.filipchuk@intel.com>
To: Alan Previn <alan.previn.teres.alexis@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
	Rodrigo Vivi <rodrigo.vivi@intel.com>
Subject: Re: [PATCH 2/2] drm/xe/nvl-s: Enable PXP for NVL-S
Date: Tue, 29 Sep 2026 12:18:54 -0700	[thread overview]
Message-ID: <8847b63e-bf98-4b63-8cb6-daa4b1f7490d@intel.com> (raw)
In-Reply-To: <20260923183600.1186943-6-alan.previn.teres.alexis@intel.com>

Reviewed-by: Julia Filipchuk <julia.filipchuk@intel.com>

On 9/23/2026 11:36 AM, Alan Previn wrote:
> Now that the GSC FW is defined, we can enable PXP for NVL-S. The feature
> will only be turned on if the binary is found on disk.
> 
> Signed-off-by: Alan Previn <alan.previn.teres.alexis@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pci.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index d64e873d9e71..94fa9c960235 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -460,6 +460,7 @@ static const struct xe_device_desc nvls_desc = {
>  	.has_flat_ccs = 1,
>  	.has_pre_prod_wa = 1,
>  	.has_sriov = true,
> +	.has_pxp = true,
>  	.max_gt_per_tile = 2,
>  	MULTI_LRC_MASK,
>  	.va_bits = 48,


  reply	other threads:[~2026-09-29 19:19 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-23 18:36 [PATCH 0/2] Enable GSC loading and PXP for NVL-S Alan Previn
2026-09-23 18:36 ` [PATCH 1/2] drm/xe/gsc: Define GSC " Alan Previn
2026-09-29 19:18   ` Julia Filipchuk
2026-09-23 18:36 ` [PATCH 2/2] drm/xe/nvl-s: Enable PXP " Alan Previn
2026-09-29 19:18   ` Julia Filipchuk [this message]
2026-09-29 19:36     ` Rodrigo Vivi
2026-09-23 19:41 ` ✓ CI.KUnit: success for Enable GSC loading and " Patchwork
2026-09-23 21:39 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-24 11:20 ` ✗ Xe.CI.FULL: failure " Patchwork
2026-09-29 18:24   ` Teres Alexis, Alan Previn

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