Re: [PATCH 2/3] drm/fourcc: define Intel Xe2 related tile4 ccs modifiers

[Maarten Lankhorst <maarten.lankhorst@linux.intel.com>]

Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Den 2024-08-17 kl. 02:06, skrev Lucas De Marchi:
> On Fri, Aug 16, 2024 at 02:52:28PM GMT, Juha-Pekka Heikkila wrote:
>> Add Tile4 type ccs modifiers to indicate presence of compression on Xe2.
>> Here is defined I915_FORMAT_MOD_4_TILED_LNL_CCS which is meant for
>> integrated graphics with igpu related limitations
>> Here is also defined I915_FORMAT_MOD_4_TILED_BMG_CCS which is meant
>> for discrete graphics with dgpu related limitations
>>
>> Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
> 
> not very fond of adding the platform names, but looks like this was
> always the approach, so this keeps the consistency.
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
> 
> We will need an ack from drm-misc maintainer to merge this through
> drm-intel. Let's add some Cc.
> 
> Lucas De Marchi
> 
>> ---
>> include/uapi/drm/drm_fourcc.h | 25 +++++++++++++++++++++++++
>> 1 file changed, 25 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index 2d84a8052b15..78abd819fd62 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -702,6 +702,31 @@ extern "C" {
>>  */
>> #define I915_FORMAT_MOD_4_TILED_MTL_RC_CCS_CC fourcc_mod_code(INTEL, 15)
>>
>> +/*
>> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
>> + * on integrated graphics
>> + *
>> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
>> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
>> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
>> + * GEM object in a reserved memory area dedicated for the storage of the
>> + * CCS data for all compressible GEM objects.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_LNL_CCS fourcc_mod_code(INTEL, 16)
>> +
>> +/*
>> + * Intel Color Control Surfaces (CCS) for graphics ver. 20 unified compression
>> + * on discrete graphics
>> + *
>> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
>> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
>> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
>> + * GEM object in a reserved memory area dedicated for the storage of the
>> + * CCS data for all compressible GEM objects. The GEM object must be stored in
>> + * contiguous memory with a size aligned to 64KB
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_BMG_CCS fourcc_mod_code(INTEL, 17)
>> +
>> /*
>>  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>>  *
>> -- 
>> 2.45.2
>>