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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by IA3PR11MB9399.namprd11.prod.outlook.com (2603:10b6:208:577::9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9412.13; Tue, 16 Dec 2025 12:31:07 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9434.001; Tue, 16 Dec 2025 12:31:07 +0000 Message-ID: <8d31226f-a94d-49f7-8ee5-aa34ea37f19c@intel.com> Date: Tue, 16 Dec 2025 18:00:59 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v10 17/17] drm/i915/vrr: Enable DC Balance To: Mitul Golani , CC: , , , References: <20251202073659.926838-1-mitulkumar.ajitkumar.golani@intel.com> <20251202073659.926838-18-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251202073659.926838-18-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 11 ++++++++++- > 1 file changed, 10 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index ba8b3c664e70..db74744ddb31 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -399,6 +399,7 @@ intel_vrr_dc_balance_compute_config(struct intel_crtc_state *crtc_state) > crtc_state->vrr.dc_balance.vblank_target = > DIV_ROUND_UP((crtc_state->vrr.vmax - crtc_state->vrr.vmin) * > DCB_BLANK_TARGET, 100); > + crtc_state->vrr.dc_balance.enable = true; > } > > void > @@ -789,6 +790,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) > enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > enum pipe pipe = crtc->pipe; > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); As Uma pointed out, it would be better to use trans_vrr_ctl() here. > > if (!crtc_state->vrr.dc_balance.enable) > return; > @@ -827,6 +829,9 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) > intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), > ADAPTIVE_SYNC_COUNTER_EN); > intel_pipedmc_dcb_enable(NULL, crtc); > + > + vrr_ctl |= VRR_CTL_DCB_ADJ_ENABLE; > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); > } > > static void > @@ -836,6 +841,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) > enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder; > struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); > enum pipe pipe = crtc->pipe; > + u32 vrr_ctl = intel_de_read(display, TRANS_VRR_CTL(display, cpu_transcoder)); > > if (!old_crtc_state->vrr.dc_balance.enable) > return; > @@ -858,6 +864,9 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) > intel_de_write(display, TRANS_VRR_DCB_ADJ_FLIPLINE_CFG(cpu_transcoder), 0); > intel_de_write(display, TRANS_VRR_DCB_VMAX(cpu_transcoder), 0); > intel_de_write(display, TRANS_VRR_DCB_FLIPLINE(cpu_transcoder), 0); > + > + vrr_ctl &= ~VRR_CTL_DCB_ADJ_ENABLE; > + intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), vrr_ctl); > } > > static void intel_vrr_tg_enable(const struct intel_crtc_state *crtc_state, > @@ -963,7 +972,7 @@ void intel_vrr_get_dc_balance_config(struct intel_crtc_state *crtc_state) > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > enum pipe pipe = crtc->pipe; > > - if (!HAS_VRR_DC_BALANCE(display)) > + if (!intel_vrr_dc_balance_possible(crtc_state)) > return; This change looks out of place. Hmm .. In Patch#5, intel_vrr_get_dc_balance_config() is added, but at that point intel_vrr_dc_balance_possible() is not yet defined. I think the above update should either: Move to Patch#7 (where the helper is introduced), or Introduce the helper in a separate patch placed right after Patch#7 but before the enablement patch. PS: My earlier suggestion in [1] was to introduce the helper sooner to avoid having it as the last patch. This was to make sure we have pipe restriction in place before the enablement logic lands, to avoid any risk enabling DC balancing on unsupported pipes. Given the current series structure, moving this change to Patch#7 or introducing a separate patch right after Patch#7 (before enablement) seems a better idea. [1] https://patchwork.freedesktop.org/patch/690789/?series=158156&rev=1 Regards, Ankit > > reg_val = intel_de_read(display, PIPEDMC_DCB_VMIN(pipe));