Intel-XE Archive on lore.kernel.org
 help / color / mirror / Atom feed
From: "Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>
To: Matthew Brost <matthew.brost@intel.com>,
	<intel-xe@lists.freedesktop.org>
Cc: Maarten Lankhorst <dev@lankhorst.se>
Subject: Re: [PATCH v8 10/24] drm/xe: Update GuC submission backend to run PT jobs
Date: Sat, 26 Sep 2026 04:50:14 +0530	[thread overview]
Message-ID: <8edf915c-8322-45c6-a03d-ced5198c2fa9@intel.com> (raw)
In-Reply-To: <20260925201526.1355279-11-matthew.brost@intel.com>



On 26-09-2026 01:45, Matthew Brost wrote:
> PT jobs bypass GPU execution for the final step of a bind job, using the
> CPU to program the required page tables. Teach the GuC submission backend
> how to execute these jobs.
> 
> PT job submission is implemented in the GuC backend for simplicity. A
> follow-up patch could introduce a dedicated backend for PT jobs.
> 
> Signed-off-by: Matthew Brost <matthew.brost@intel.com>
> Reviewed-by: Maarten Lankhorst <dev@lankhorst.se>
> ---
>   drivers/gpu/drm/xe/xe_guc_submit.c | 31 +++++++++++++++++++++++++++---
>   drivers/gpu/drm/xe/xe_migrate.c    | 20 +++++++++++++++----
>   drivers/gpu/drm/xe/xe_migrate.h    |  7 +++++++
>   3 files changed, 51 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c
> index 4bd1ead57efa..9faddb7c6407 100644
> --- a/drivers/gpu/drm/xe/xe_guc_submit.c
> +++ b/drivers/gpu/drm/xe/xe_guc_submit.c
> @@ -39,9 +39,11 @@
>   #include "xe_lrc.h"
>   #include "xe_macros.h"
>   #include "xe_map.h"
> +#include "xe_migrate.h"
>   #include "xe_mocs.h"
>   #include "xe_module.h"
>   #include "xe_pm.h"
> +#include "xe_pt.h"
>   #include "xe_ring_ops_types.h"
>   #include "xe_sched_job.h"
>   #include "xe_sleep.h"
> @@ -1238,21 +1240,44 @@ static void submit_exec_queue(struct xe_exec_queue *q, struct xe_sched_job *job)
>   	}
>   }
>   
> +static bool is_pt_job(struct xe_sched_job *job)
> +{
> +	return job->is_pt_job;
> +}
> +
> +static void run_pt_job(struct xe_sched_job *job, bool force_clear)
> +{
> +	xe_migrate_update_pgtables_cpu_execute(job->pt_update[0].vm,
> +					       job->pt_update[0].tile,
> +					       job->pt_update[0].ops,
> +					       job->pt_update[0].pt_job_ops->ops,
> +					       job->pt_update[0].pt_job_ops->current_op,
> +					       force_clear);
> +}
> +
>   static struct dma_fence *
>   guc_exec_queue_run_job(struct drm_sched_job *drm_job)
>   {
>   	struct xe_sched_job *job = to_xe_sched_job(drm_job);
>   	struct xe_exec_queue *q = job->q;
>   	struct xe_guc *guc = exec_queue_to_guc(q);
> -	bool killed_or_banned_or_wedged =
> -		exec_queue_killed_or_banned_or_wedged(q);
> +	bool killed_or_banned_or_wedged_or_error  =
> +		exec_queue_killed_or_banned_or_wedged(q) ||
> +		xe_sched_job_is_error(job);

Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com>

>   
>   	xe_gt_assert(guc_to_gt(guc), !(exec_queue_destroyed(q) || exec_queue_pending_disable(q)) ||
>   		     exec_queue_banned(q) || exec_queue_suspended(q));
>   
>   	trace_xe_sched_job_run(job);
>   
> -	if (!killed_or_banned_or_wedged && !xe_sched_job_is_error(job)) {
> +	if (is_pt_job(job)) {
> +		xe_gt_assert(guc_to_gt(guc), !exec_queue_registered(q));
> +		run_pt_job(job, killed_or_banned_or_wedged_or_error);
> +		xe_pt_job_ops_put(job->pt_update[0].pt_job_ops);
> +		dma_fence_put(job->fence);	/* Drop ref from xe_sched_job_arm */
> +
> +		return NULL;
> +	} else if (!killed_or_banned_or_wedged_or_error) {
>   		if (xe_exec_queue_is_multi_queue_secondary(q)) {
>   			struct xe_exec_queue *primary = xe_exec_queue_multi_queue_primary(q);
>   
> diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
> index d7f35aa91c1c..3007fe0b8535 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.c
> +++ b/drivers/gpu/drm/xe/xe_migrate.c
> @@ -1819,11 +1819,23 @@ struct migrate_test_params {
>   	container_of(_priv, struct migrate_test_params, base)
>   #endif
>   
> -static void
> +/**
> + * xe_migrate_update_pgtables_cpu_execute() - Update a VM's PTEs via the CPU
> + * @vm: The VM being updated
> + * @tile: The tile being updated
> + * @ops: The migrate PT update ops
> + * @pt_ops: The VM PT update ops
> + * @num_ops: The number of The VM PT update ops
> + * @force_clear: Force clear
> + *
> + * Execute the VM PT update ops array which results in a VM's PTEs being updated
> + * via the CPU.
> + */
> +void
>   xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
>   				       const struct xe_migrate_pt_update_ops *ops,
>   				       struct xe_vm_pgtable_update_op *pt_op,
> -				       u32 num_ops)
> +				       u32 num_ops, bool force_clear)
>   {
>   	u32 j, i;
>   
> @@ -1834,7 +1846,7 @@ xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
>   
>   			xe_tile_assert(tile, !iosys_map_is_null(&update->pt_bo->vmap));
>   
> -			if (pt_op->bind)
> +			if (pt_op->bind && !force_clear)
>   				ops->populate(tile, &update->pt_bo->vmap,
>   					      NULL, update->ofs, update->qwords,
>   					      update);
> @@ -1874,7 +1886,7 @@ xe_migrate_update_pgtables_cpu(struct xe_migrate *m,
>   
>   	xe_migrate_update_pgtables_cpu_execute(vm, m->tile, ops,
>   					       pt_update_ops->pt_job_ops->ops,
> -					       pt_update_ops->num_ops);
> +					       pt_update_ops->num_ops, false);
>   
>   	return dma_fence_get_stub();
>   }
> diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h
> index 2ec9de896dfe..c41f6e3ca2c6 100644
> --- a/drivers/gpu/drm/xe/xe_migrate.h
> +++ b/drivers/gpu/drm/xe/xe_migrate.h
> @@ -24,6 +24,7 @@ struct xe_pt;
>   struct xe_tile;
>   struct xe_vm;
>   struct xe_vm_pgtable_update;
> +struct xe_vm_pgtable_update_op;
>   struct xe_vma;
>   
>   enum xe_sriov_vf_ccs_rw_ctxs;
> @@ -163,6 +164,12 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m,
>   
>   struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m);
>   
> +void
> +xe_migrate_update_pgtables_cpu_execute(struct xe_vm *vm, struct xe_tile *tile,
> +				       const struct xe_migrate_pt_update_ops *ops,
> +				       struct xe_vm_pgtable_update_op *pt_op,
> +				       u32 num_ops, bool force_clear);
> +
>   struct dma_fence *
>   xe_migrate_update_pgtables(struct xe_migrate *m,
>   			   struct xe_migrate_pt_update *pt_update);


  parent reply	other threads:[~2026-09-25 23:20 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-25 20:15 [PATCH v8 00/24] CPU binds and ULLS on migration queue Matthew Brost
2026-09-25 20:15 ` [PATCH v8 01/24] drm/xe: reference VM from PT BOs Matthew Brost
2026-09-25 20:15 ` [PATCH v8 02/24] drm/xe: Drop struct xe_migrate_pt_update argument from populate/clear vfuns Matthew Brost
2026-09-25 20:15 ` [PATCH v8 03/24] drm/xe: Add xe_migrate_update_pgtables_cpu_execute helper Matthew Brost
2026-09-25 20:15 ` [PATCH v8 04/24] drm/xe: Decouple exec queue idle check from LRC Matthew Brost
2026-09-25 20:15 ` [PATCH v8 05/24] drm/xe: Add job count to GuC exec queue snapshot Matthew Brost
2026-09-25 20:15 ` [PATCH v8 06/24] drm/xe: Update xe_bo_put_deferred arguments to include writeback flag Matthew Brost
2026-09-25 20:15 ` [PATCH v8 07/24] drm/xe: Update scheduler job layer to support PT jobs Matthew Brost
2026-09-25 20:15 ` [PATCH v8 08/24] drm/xe: Add helpers to access PT ops Matthew Brost
2026-09-25 20:15 ` [PATCH v8 09/24] drm/xe: Add struct xe_pt_job_ops Matthew Brost
2026-09-25 20:15 ` [PATCH v8 10/24] drm/xe: Update GuC submission backend to run PT jobs Matthew Brost
2026-09-25 20:38   ` sashiko-bot
2026-09-25 23:20   ` Ghimiray, Himal Prasad [this message]
2026-09-25 20:15 ` [PATCH v8 11/24] drm/xe: Store level in struct xe_vm_pgtable_update Matthew Brost
2026-09-25 20:15 ` [PATCH v8 12/24] drm/xe: Don't use migrate exec queue for page fault binds Matthew Brost
2026-09-25 20:15 ` [PATCH v8 13/24] drm/xe: Enable CPU binds for jobs Matthew Brost
2026-09-25 20:39   ` sashiko-bot
2026-09-25 20:15 ` [PATCH v8 14/24] drm/xe: Remove unused arguments from xe_migrate_pt_update_ops Matthew Brost
2026-09-25 20:15 ` [PATCH v8 15/24] drm/xe: Make bind queues operate cross-tile Matthew Brost
2026-09-25 20:15 ` [PATCH v8 16/24] drm/xe: Add CPU bind layer Matthew Brost
2026-09-25 20:15 ` [PATCH v8 17/24] drm/xe: Add device flag to enable PT mirroring across tiles Matthew Brost
2026-09-25 20:46   ` sashiko-bot
2026-09-25 20:15 ` [PATCH v8 18/24] drm/xe: Add ULLS support to LRC Matthew Brost
2026-09-25 20:15 ` [PATCH v8 19/24] drm/xe: Add ULLS migration job support to migration layer Matthew Brost
2026-09-25 20:41   ` sashiko-bot
2026-09-25 20:15 ` [PATCH v8 20/24] drm/xe: Add ULLS migration job support to ring ops Matthew Brost
2026-09-25 20:48   ` sashiko-bot
2026-09-25 20:15 ` [PATCH v8 21/24] drm/xe: Add ULLS migration job support to GuC submission Matthew Brost
2026-09-25 20:45   ` sashiko-bot
2026-09-25 20:15 ` [PATCH v8 22/24] drm/xe: Enter ULLS for migration jobs upon page fault or SVM prefetch Matthew Brost
2026-09-25 20:15 ` [PATCH v8 23/24] drm/xe: add migrate ULLS period configfs attribute Matthew Brost
2026-09-25 20:15 ` [PATCH v8 24/24] drm/xe: Document ULLS for migration jobs Matthew Brost
2026-09-25 21:02 ` ✗ CI.checkpatch: warning for CPU binds and ULLS on migration queue (rev10) Patchwork
2026-09-25 21:04 ` ✓ CI.KUnit: success " Patchwork
2026-09-25 22:12 ` ✓ Xe.CI.BAT: " Patchwork
2026-09-26  7:40 ` ✗ Xe.CI.FULL: failure " Patchwork

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=8edf915c-8322-45c6-a03d-ced5198c2fa9@intel.com \
    --to=himal.prasad.ghimiray@intel.com \
    --cc=dev@lankhorst.se \
    --cc=intel-xe@lists.freedesktop.org \
    --cc=matthew.brost@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox