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> } > > +/* > + * intel_dmc_configure_dc_balance_event() - Configure event > + * for dc balance enable/disable > + * @display: display instance > + * @pipe: pipe which register use to block > + * @enable: enable/disable > + */ > +void intel_dmc_configure_dc_balance_event(struct intel_display *display, > + enum pipe pipe, bool enable) > +{ > + enum intel_dmc_id dmc_id = PIPE_TO_DMC_ID(pipe); > + > + dmc_configure_event(display, dmc_id, PIPEDMC_EVENT_ADAPTIVE_DCB_TRIGGER, enable); > +} > + > /** > * intel_dmc_block_pkgc() - block PKG C-state > * @display: display instance > diff --git a/drivers/gpu/drm/i915/display/intel_dmc.h b/drivers/gpu/drm/i915/display/intel_dmc.h > index 9c6a42fc820e..3d8a9a593319 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc.h > @@ -25,6 +25,8 @@ void intel_dmc_enable_pipe(const struct intel_crtc_state *crtc_state); > void intel_dmc_disable_pipe(const struct intel_crtc_state *crtc_state); > void intel_dmc_block_pkgc(struct intel_display *display, enum pipe pipe, > bool block); > +void intel_dmc_configure_dc_balance_event(struct intel_display *display, > + enum pipe pipe, bool enable); > void intel_dmc_start_pkgc_exit_at_start_of_undelayed_vblank(struct intel_display *display, > enum pipe pipe, bool enable); > void intel_dmc_fini(struct intel_display *display); > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index a23cb90b6b7e..74a6d5243f00 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -835,6 +835,7 @@ intel_vrr_enable_dc_balancing(const struct intel_crtc_state *crtc_state) > crtc_state->vrr.dc_balance.slope); > intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), > crtc_state->vrr.dc_balance.vblank_target); > + intel_dmc_configure_dc_balance_event(display, pipe, true); > intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), > ADAPTIVE_SYNC_COUNTER_EN); > intel_pipedmc_dcb_enable(NULL, crtc); > @@ -852,6 +853,7 @@ intel_vrr_disable_dc_balancing(const struct intel_crtc_state *old_crtc_state) > return; > > intel_pipedmc_dcb_disable(NULL, crtc); > + intel_dmc_configure_dc_balance_event(display, pipe, false); > intel_de_write(display, TRANS_ADAPTIVE_SYNC_DCB_CTL(cpu_transcoder), 0); > intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); > intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0);