From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 84222C3601E for ; Thu, 10 Apr 2025 17:16:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 49F4710E373; Thu, 10 Apr 2025 17:16:36 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="cVHC8eb8"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0500110E373 for ; Thu, 10 Apr 2025 17:16:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1744305395; x=1775841395; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=afSOJTITV9SY9q/JS/tf6xD9AI9LEdSaUh9POr5PtPY=; b=cVHC8eb8sImckvnEca6qpmZCORVSceUAg6gR3L5tjgvcExWpr6MJNzUB V7iCo6e6/ycGYQXmrSX0NJCHsbg+i1zoSTcajFcoQvRsuSK5ljJWZhTf+ VoTS9uwG6Yrp5Pty/G/vrmJ9Zt88kT6XJKi8XHtiRsDL51H6RMtv1lFqF nDHaumovzIGUi7g8yA55e22EQ2DKPheKqEkReN7s0SbnVUq8kBlFb2aYs uMl8e+14ClcHbMm7h/5xGZmsPuZWo/kEErMR1TmUegmiST5MPZ3wK+yZl 9jo5V/3uM3klQPz3lJ8eViIu8895R+Zuu4kH82CF2S2G4MUi98hD+p0uj g==; X-CSE-ConnectionGUID: 6S1kTLaET4+M77AyBQQmrQ== X-CSE-MsgGUID: y8ogWDt4RuWyI90AibXWgA== X-IronPort-AV: E=McAfee;i="6700,10204,11400"; a="45969066" X-IronPort-AV: E=Sophos;i="6.15,202,1739865600"; d="scan'208";a="45969066" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 10 Apr 2025 10:16:34 -0700 X-CSE-ConnectionGUID: gn7bnhCUQmehnU4m70TBKg== X-CSE-MsgGUID: LqX+bOR2S2WOayqXteVztw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,202,1739865600"; d="scan'208";a="129503320" Received: from irvmail002.ir.intel.com ([10.43.11.120]) by fmviesa010.fm.intel.com with ESMTP; 10 Apr 2025 10:16:32 -0700 Received: from [10.245.96.73] (mwajdecz-MOBL.ger.corp.intel.com [10.245.96.73]) by irvmail002.ir.intel.com (Postfix) with ESMTP id 73B9734975; Thu, 10 Apr 2025 18:16:31 +0100 (IST) Message-ID: <8f7c7bc8-2476-44e2-9821-b47f0edafaca@intel.com> Date: Thu, 10 Apr 2025 19:16:30 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v8 3/4] drm/xe/guc: Introduce enum with offsets for context register H2Gs To: Tomasz Lis , intel-xe@lists.freedesktop.org Cc: =?UTF-8?Q?Micha=C5=82_Winiarski?= , =?UTF-8?Q?Piotr_Pi=C3=B3rkowski?= , Matthew Brost , Lucas De Marchi References: <20250409211340.3046931-1-tomasz.lis@intel.com> <20250409211340.3046931-4-tomasz.lis@intel.com> Content-Language: en-US From: Michal Wajdeczko In-Reply-To: <20250409211340.3046931-4-tomasz.lis@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On 09.04.2025 23:13, Tomasz Lis wrote: > Some GuC messages are constructed with incrementing dword counter > rather than referencing specific DWORDs, as described in GuC interface > specification. > > This change introduces the definitions of DWORD numbers for parameters > which will need to be referenced in a CTB parser to be added in a > following patch. To ensure correctness of these DWORDs, verification > in form of asserts was added to the message construction code. > > v2: Renamed enum members, added ones for single context registration, > modified asserts to check values rather than indexes. > v3: Reordered assert args to take less lines > > Signed-off-by: Tomasz Lis > Suggested-by: Michal Wajdeczko > --- > drivers/gpu/drm/xe/abi/guc_actions_abi.h | 29 ++++++++++++++++++++++++ > drivers/gpu/drm/xe/xe_guc_submit.c | 17 ++++++++++++++ > 2 files changed, 46 insertions(+) > > diff --git a/drivers/gpu/drm/xe/abi/guc_actions_abi.h b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > index 448afb86e05c..64c71526356e 100644 > --- a/drivers/gpu/drm/xe/abi/guc_actions_abi.h > +++ b/drivers/gpu/drm/xe/abi/guc_actions_abi.h > @@ -161,6 +161,35 @@ enum xe_guc_preempt_options { > XE_GUC_PREEMPT_OPTION_DROP_SUBMIT_Q = 0x8, > }; > > +enum xe_guc_register_context_param_offsets { > + XE_GUC_REGISTER_CONTEXT_DATA_0_MBZ = 0, > + XE_GUC_REGISTER_CONTEXT_DATA_1_FLAGS, > + XE_GUC_REGISTER_CONTEXT_DATA_2_CONTEXT_INDEX, > + XE_GUC_REGISTER_CONTEXT_DATA_3_ENGINE_CLASS, > + XE_GUC_REGISTER_CONTEXT_DATA_4_ENGINE_SUBMIT_MASK, > + XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER, > + XE_GUC_REGISTER_CONTEXT_DATA_6_WQ_DESC_ADDR_UPPER, > + XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER, > + XE_GUC_REGISTER_CONTEXT_DATA_8_WQ_BUF_BASE_UPPER, > + XE_GUC_REGISTER_CONTEXT_DATA_9_WQ_BUF_SIZE, > + XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR, > +}; > + > +enum xe_guc_register_context_multi_lrc_param_offsets { > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_0_MBZ = 0, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_1_FLAGS, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_2_PARENT_CONTEXT, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_3_ENGINE_CLASS, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_4_ENGINE_SUBMIT_MASK, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_6_WQ_DESC_ADDR_UPPER, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_8_WQ_BUF_BASE_UPPER, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_9_WQ_BUF_SIZE, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS, > + XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR, > +}; > + > enum xe_guc_report_status { > XE_GUC_REPORT_STATUS_UNKNOWN = 0x0, > XE_GUC_REPORT_STATUS_ACKED = 0x1, > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > index 813c3c0bb250..cfc65f21b2f7 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > @@ -487,6 +487,15 @@ static void __register_mlrc_exec_queue(struct xe_guc *guc, > action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); > } > > + /* explicitly checks some fields that we might fixup later */ > + xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo == > + action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_5_WQ_DESC_ADDR_LOWER]); > + xe_gt_assert(guc_to_gt(guc), info->wq_base_lo == > + action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_7_WQ_BUF_BASE_LOWER]); > + xe_gt_assert(guc_to_gt(guc), q->width == > + action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_10_NUM_CTXS]); > + xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo == > + action[XE_GUC_REGISTER_CONTEXT_MULTI_LRC_DATA_11_HW_LRC_ADDR]); > xe_gt_assert(guc_to_gt(guc), len <= MAX_MLRC_REG_SIZE); > #undef MAX_MLRC_REG_SIZE > > @@ -511,6 +520,14 @@ static void __register_exec_queue(struct xe_guc *guc, > info->hwlrca_hi, > }; > > + /* explicitly checks some fields that we might fixup later */ > + xe_gt_assert(guc_to_gt(guc), info->wq_desc_lo == > + action[XE_GUC_REGISTER_CONTEXT_DATA_5_WQ_DESC_ADDR_LOWER]); > + xe_gt_assert(guc_to_gt(guc), info->wq_base_lo == > + action[XE_GUC_REGISTER_CONTEXT_DATA_7_WQ_BUF_BASE_LOWER]); > + xe_gt_assert(guc_to_gt(guc), info->hwlrca_lo == > + action[XE_GUC_REGISTER_CONTEXT_DATA_10_HW_LRC_ADDR]); > + > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); > } > LGTM, Reviewed-by: Michal Wajdeczko