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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by SA1PR11MB8319.namprd11.prod.outlook.com (2603:10b6:806:38c::16) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9275.16; Wed, 5 Nov 2025 04:54:16 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%7]) with mapi id 15.20.9253.013; Wed, 5 Nov 2025 04:54:16 +0000 Message-ID: <9316274c-2379-4e96-be4a-26b36406a5f0@intel.com> Date: Wed, 5 Nov 2025 10:24:10 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [RESEND, 11/22] drm/i915/vrr: Add function reset DC balance accumulated params To: Mitul Golani , CC: , , References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-12-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20251103053002.3002695-12-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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This helps to give a > fresh start when VRR is re-enabled. > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++++ > drivers/gpu/drm/i915/display/intel_vrr.h | 2 ++ > 3 files changed, 16 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index 323293f4bf6d..b256517d58cf 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -1149,6 +1149,7 @@ static void intel_pre_plane_update(struct intel_atomic_state *state, > if (intel_crtc_vrr_disabling(state, crtc)) { > intel_vrr_disable(old_crtc_state); > intel_vrr_dcb_reset_flip_count(old_crtc_state, crtc); > + intel_vrr_dcb_balance_reset(old_crtc_state, crtc); Lets have both the reset functions in the intel_vrr_dcb_balance_reset(). Move this patch before the dcb_flip_count introduction patch. Call the function to reset the flip_count from intel_vrr_dcb_balance_reset() Regards, Ankit > intel_crtc_update_active_timings(old_crtc_state, false); > } > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 2ae27751e5b4..6168caff9cf0 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -639,6 +639,19 @@ void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state, > intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), 0); > } > > +void > +intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum pipe pipe = crtc->pipe; > + > + if (!crtc_state->vrr.dc_balance.enable) > + return; > + > + intel_de_write(display, PIPEDMC_DCB_BALANCE_RESET(pipe), 0); > +} > + > void intel_vrr_send_push(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state) > { > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h > index 8f97525b8e2d..a713d1a1e3dd 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h > @@ -44,6 +44,8 @@ void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, > struct intel_crtc *crtc); > void intel_vrr_dcb_reset_flip_count(const struct intel_crtc_state *crtc_state, > struct intel_crtc *crtc); > +void intel_vrr_dcb_balance_reset(const struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc); > bool intel_vrr_always_use_vrr_tg(struct intel_display *display); > int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state); > int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state);