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From: "Mallesh, Koujalagi" <mallesh.koujalagi@intel.com>
To: Riana Tauro <riana.tauro@intel.com>, <intel-xe@lists.freedesktop.org>
Cc: <anshuman.gupta@intel.com>, <rodrigo.vivi@intel.com>,
	<aravind.iddamsetty@linux.intel.com>, <raag.jadav@intel.com>,
	<ravi.kishore.koppuravuri@intel.com>, <tejas.upadhyay@intel.com>
Subject: Re: [PATCH v3 5/7] drm/xe/xe_ras: Add a flag for uncorrectable internal error
Date: Tue, 3 Nov 2026 13:49:14 +0530	[thread overview]
Message-ID: <93b09b3e-77a2-489d-bb6b-e0ddd8628f62@intel.com> (raw)
In-Reply-To: <20261103060929.1586783-14-riana.tauro@intel.com>


On 03-11-2026 11:39 am, Riana Tauro wrote:
> Introduce a flag with get/set accessors to record when an
> uncorrectable internal error was reported via AER.
>
> Signed-off-by: Riana Tauro <riana.tauro@intel.com>
LGTM,
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> v2: add PCI_POSSIBLE_ERROR
>      fix kernel-doc
>      rename aer_path to internal error
> ---
>   drivers/gpu/drm/xe/xe_pci_error.c | 26 ++++++++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_ras.c       | 20 ++++++++++++++++++++
>   drivers/gpu/drm/xe/xe_ras.h       |  2 ++
>   drivers/gpu/drm/xe/xe_ras_types.h |  2 ++
>   4 files changed, 50 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/xe_pci_error.c b/drivers/gpu/drm/xe/xe_pci_error.c
> index 9bf0da3a3d15..4ade392b47be 100644
> --- a/drivers/gpu/drm/xe/xe_pci_error.c
> +++ b/drivers/gpu/drm/xe/xe_pci_error.c
> @@ -54,6 +54,29 @@ static pci_ers_result_t ras_action_to_pci_result(struct pci_dev *pdev, u8 action
>   	}
>   }
>   
> +static bool is_aer_internal_error(struct pci_dev *pdev)
> +{
> +	struct pci_dev *usp;
> +	u16 aer_cap;
> +	u32 status;
> +
> +	usp = xe_pci_get_usp_dev(pdev);
> +	if (!usp)
> +		return false;
> +
> +	aer_cap = pci_find_ext_capability(usp, PCI_EXT_CAP_ID_ERR);
> +	if (!aer_cap) {
> +		dev_warn_once(&usp->dev, "AER capability unavailable\n");
> +		return false;
> +	}
> +
> +	pci_read_config_dword(usp, aer_cap + PCI_ERR_UNCOR_STATUS, &status);
> +	if (PCI_POSSIBLE_ERROR(status))
> +		return false;
> +
> +	return status & PCI_ERR_UNC_INTN;
> +}
> +
>   static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state)
>   {
>   	struct xe_device *xe = pdev_to_xe_device(pdev);
> @@ -67,6 +90,9 @@ static pci_ers_result_t xe_pci_error_detected(struct pci_dev *pdev, pci_channel_
>   	if (xe_survivability_mode_is_boot_enabled(xe) || xe_wedged(xe))
>   		return PCI_ERS_RESULT_DISCONNECT;
>   
> +	if (is_aer_internal_error(pdev))
> +		xe_ras_set_aer_internal_error(xe);
> +
>   	switch (state) {
>   	case pci_channel_io_normal:
>   		return PCI_ERS_RESULT_CAN_RECOVER;
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> index 3aea4969af13..58a0b5fa676d 100644
> --- a/drivers/gpu/drm/xe/xe_ras.c
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -1253,6 +1253,26 @@ u32 xe_ras_get_max_pages(struct xe_device *xe)
>   	return xe->ras.state.max_pages;
>   }
>   
> +/**
> + * xe_ras_is_aer_internal_error() - Check if an uncorrectable internal error was reported via AER
> + * @xe: xe device instance
> + *
> + * Return: true if an uncorrectable internal error was reported via AER, false otherwise.
> + */
> +bool xe_ras_is_aer_internal_error(struct xe_device *xe)
> +{
> +	return xe->ras.state.aer_internal_error;
> +}
> +
> +/**
> + * xe_ras_set_aer_internal_error() - Set if an uncorrectable internal error is reported via AER
> + * @xe: xe device instance
> + */
> +void xe_ras_set_aer_internal_error(struct xe_device *xe)
> +{
> +	xe->ras.state.aer_internal_error = true;
> +}
> +
>   /**
>    * xe_ras_init - Initialize Xe RAS
>    * @xe: xe device instance
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> index c44fa172011f..f7b587ac84e3 100644
> --- a/drivers/gpu/drm/xe/xe_ras.h
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -25,5 +25,7 @@ bool xe_ras_get_disable_vram_page_offline(struct xe_device *xe);
>   u32 xe_ras_get_max_pages(struct xe_device *xe);
>   int xe_ras_get_counter_response(struct xe_device *xe, const struct xe_ras_error_class *counter,
>   				struct xe_ras_get_counter_response *response);
> +bool xe_ras_is_aer_internal_error(struct xe_device *xe);
> +void xe_ras_set_aer_internal_error(struct xe_device *xe);
>   
>   #endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> index a86f9d2b8c92..0ff5803d495b 100644
> --- a/drivers/gpu/drm/xe/xe_ras_types.h
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -414,6 +414,8 @@ struct xe_ras_set_health_response {
>    * struct xe_ras_state - RAS device and firmware state
>    */
>   struct xe_ras_state {
> +	/** @aer_internal_error: true if an uncorrectable internal error was reported via AER */
> +	bool aer_internal_error;
>   	/** @disable_vram_page_offline: cached configfs policy, immutable after init */
>   	bool disable_vram_page_offline;
>   	/** @max_pages: Total number of pages that can be stored by firmware */

  reply	other threads:[~2026-11-03  8:19 UTC|newest]

Thread overview: 23+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-03  6:09 [PATCH v3 0/7] Handle non-fatal errors routed via IRQ Riana Tauro
2026-11-03  6:09 ` [PATCH v3 1/7] drm/xe/hw_error: Reuse CSC worker for generic error handling Riana Tauro
2026-11-03  6:27   ` Mallesh, Koujalagi
2026-11-03  6:09 ` [PATCH v3 2/7] drm/xe/hw_error: Initialize hw_error_work per tile Riana Tauro
2026-11-03  6:23   ` sashiko-bot
2026-11-03  6:42     ` Tauro, Riana
2026-11-04  9:31   ` Mallesh, Koujalagi
2026-11-04 12:58     ` Tauro, Riana
2026-11-03  6:09 ` [PATCH v3 3/7] drm/xe/ras: Treat non-fatal PCIe errors as recovered Riana Tauro
2026-11-03  6:19   ` Mallesh, Koujalagi
2026-11-03  6:09 ` [PATCH v3 4/7] drm/xe/pci: Add upstream switch port lookup helper Riana Tauro
2026-11-03  6:09 ` [PATCH v3 5/7] drm/xe/xe_ras: Add a flag for uncorrectable internal error Riana Tauro
2026-11-03  8:19   ` Mallesh, Koujalagi [this message]
2026-11-03  6:09 ` [PATCH v3 6/7] drm/xe: Add support for wa_14028434957 Riana Tauro
2026-11-03  6:33   ` sashiko-bot
2026-11-03  6:45     ` Tauro, Riana
2026-11-04 10:38   ` Mallesh, Koujalagi
2026-11-04 10:44     ` Tauro, Riana
2026-11-03  6:09 ` [PATCH v3 7/7] drm/xe/xe_ras: Skip double-bit ECC page offlining on AER path Riana Tauro
2026-11-03  6:23   ` sashiko-bot
2026-11-03  7:32 ` ✓ CI.KUnit: success for Handle non-fatal errors routed via IRQ (rev3) Patchwork
2026-11-03  8:05 ` ✓ Xe.CI.BAT: " Patchwork
2026-11-03 13:34 ` ✓ Xe.CI.FULL: " Patchwork

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