* [PATCH v5 0/3] Introduce Xe Correctable Error Handling
@ 2026-04-07 11:06 Raag Jadav
2026-04-07 11:06 ` [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
` (6 more replies)
0 siblings, 7 replies; 14+ messages in thread
From: Raag Jadav @ 2026-04-07 11:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
This series builds on top of system controller series[1] and adds initial
support for correctable error handling in xe. This serves as a foundation
for RAS infrastructure and will be further extended to facilitate other
RAS features.
Detailed description in commit message.
[1] https://patchwork.freedesktop.org/series/163196/
v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
Handle unexpected response length (Mallesh)
v3: Handle event flood (Mallesh)
v4: Handle IRQ before sysctrl initialization (Mallesh)
Fix Severity/Component logging (Mallesh)
s/xe_ras_error/xe_ras_error_class (Riana)
v5: Handle unexpected counter threshold crossed (Mallesh)
Raag Jadav (3):
drm/xe/sysctrl: Add system controller interrupt handler
drm/xe/sysctrl: Add system controller event support
drm/xe/ras: Introduce correctable error handling
drivers/gpu/drm/xe/Makefile | 2 +
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/xe_irq.c | 2 +
drivers/gpu/drm/xe/xe_ras.c | 96 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 14 +++
drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl.c | 46 ++++++++--
drivers/gpu/drm/xe/xe_sysctrl.h | 2 +
drivers/gpu/drm/xe/xe_sysctrl_event.c | 89 +++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 +++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 ++
12 files changed, 388 insertions(+), 6 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_ras.c
create mode 100644 drivers/gpu/drm/xe/xe_ras.h
create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
--
2.43.0
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
@ 2026-04-07 11:06 ` Raag Jadav
2026-04-09 5:04 ` Tauro, Riana
2026-04-07 11:06 ` [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support Raag Jadav
` (5 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Raag Jadav @ 2026-04-07 11:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
Add system controller interrupt handler which is denoted by 11th bit in
GFX master interrupt register. While at it, add worker for scheduling
system controller work.
Co-developed-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Soham Purkait <soham.purkait@intel.com>
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
---
v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
v4: Handle IRQ before sysctrl initialization (Mallesh)
---
drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
drivers/gpu/drm/xe/xe_irq.c | 2 ++
drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
5 files changed, 44 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
index 9d74f454d3ff..1d6b976c4de0 100644
--- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
+++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
@@ -22,6 +22,7 @@
#define DISPLAY_IRQ REG_BIT(16)
#define SOC_H2DMEMINT_IRQ REG_BIT(13)
#define I2C_IRQ REG_BIT(12)
+#define SYSCTRL_IRQ REG_BIT(11)
#define GT_DW_IRQ(x) REG_BIT(x)
/*
diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
index 9a775c6588dc..e9f0b3cad06d 100644
--- a/drivers/gpu/drm/xe/xe_irq.c
+++ b/drivers/gpu/drm/xe/xe_irq.c
@@ -24,6 +24,7 @@
#include "xe_mmio.h"
#include "xe_pxp.h"
#include "xe_sriov.h"
+#include "xe_sysctrl.h"
#include "xe_tile.h"
/*
@@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
xe_heci_csc_irq_handler(xe, master_ctl);
xe_display_irq_handler(xe, master_ctl);
xe_i2c_irq_handler(xe, master_ctl);
+ xe_sysctrl_irq_handler(xe, master_ctl);
xe_mert_irq_handler(xe, master_ctl);
gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index 2bcef304eb9a..afa9654668a2 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -8,6 +8,7 @@
#include <drm/drm_managed.h>
+#include "regs/xe_irq_regs.h"
#include "regs/xe_sysctrl_regs.h"
#include "xe_device.h"
#include "xe_mmio.h"
@@ -30,10 +31,16 @@
static void sysctrl_fini(void *arg)
{
struct xe_device *xe = arg;
+ struct xe_sysctrl *sc = &xe->sc;
+ cancel_work_sync(&sc->work);
xe->soc_remapper.set_sysctrl_region(xe, 0);
}
+static void xe_sysctrl_work(struct work_struct *work)
+{
+}
+
/**
* xe_sysctrl_init() - Initialize System Controller subsystem
* @xe: xe device instance
@@ -55,11 +62,7 @@ int xe_sysctrl_init(struct xe_device *xe)
if (!xe->info.has_sysctrl)
return 0;
- xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
-
- ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
- if (ret)
- return ret;
+ xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
if (!sc->mmio)
@@ -73,9 +76,33 @@ int xe_sysctrl_init(struct xe_device *xe)
if (ret)
return ret;
+ ret = devm_mutex_init(xe->drm.dev, &sc->work_lock);
+ if (ret)
+ return ret;
+
+ xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
xe_sysctrl_mailbox_init(sc);
+ INIT_WORK(&sc->work, xe_sysctrl_work);
- return 0;
+ return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
+}
+
+/**
+ * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
+ * @xe: xe device instance
+ * @master_ctl: interrupt register
+ *
+ * Handle interrupts generated by System Controller.
+ */
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
+{
+ struct xe_sysctrl *sc = &xe->sc;
+
+ if (!xe->info.has_sysctrl || !sc->work.func)
+ return;
+
+ if (master_ctl & SYSCTRL_IRQ)
+ schedule_work(&sc->work);
}
/**
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index f3b0f3716b2f..f7469bfc9324 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -17,6 +17,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
}
int xe_sysctrl_init(struct xe_device *xe);
+void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
void xe_sysctrl_pm_resume(struct xe_device *xe);
#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
index 8217f6befe70..13fbf2990280 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
@@ -8,6 +8,7 @@
#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/workqueue_types.h>
struct xe_mmio;
@@ -27,6 +28,12 @@ struct xe_sysctrl {
/** @phase_bit: Message boundary phase toggle bit (0 or 1) */
bool phase_bit;
+
+ /** @work: Pending events work */
+ struct work_struct work;
+
+ /** @work_lock: Mutex protecting pending events */
+ struct mutex work_lock;
};
#endif
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
2026-04-07 11:06 ` [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-04-07 11:06 ` Raag Jadav
2026-04-09 9:57 ` Tauro, Riana
2026-04-07 11:06 ` [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling Raag Jadav
` (4 subsequent siblings)
6 siblings, 1 reply; 14+ messages in thread
From: Raag Jadav @ 2026-04-07 11:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
System controller reports different types of events to GFX endpoint for
different usecases, add initial support for them. This will be further
extended to service those usecases.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
---
v2: Handle unexpected response length (Mallesh)
v3: Handle event flood (Mallesh)
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
drivers/gpu/drm/xe/xe_sysctrl_event.c | 88 +++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 ++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
6 files changed, 159 insertions(+)
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index ab1e0b3b332d..c0e820eeea30 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -125,6 +125,7 @@ xe-y += xe_bb.o \
xe_survivability_mode.o \
xe_sync.o \
xe_sysctrl.o \
+ xe_sysctrl_event.o \
xe_sysctrl_mailbox.o \
xe_tile.o \
xe_tile_sysfs.o \
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
index afa9654668a2..7003b1da6e46 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl.c
@@ -12,6 +12,7 @@
#include "regs/xe_sysctrl_regs.h"
#include "xe_device.h"
#include "xe_mmio.h"
+#include "xe_pm.h"
#include "xe_soc_remapper.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_mailbox.h"
@@ -39,6 +40,12 @@ static void sysctrl_fini(void *arg)
static void xe_sysctrl_work(struct work_struct *work)
{
+ struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
+ struct xe_device *xe = sc_to_xe(sc);
+
+ guard(xe_pm_runtime)(xe);
+ guard(mutex)(&sc->work_lock);
+ xe_sysctrl_event(sc);
}
/**
diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
index f7469bfc9324..090dffb6d55f 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl.h
@@ -16,6 +16,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
return container_of(sc, struct xe_device, sc);
}
+void xe_sysctrl_event(struct xe_sysctrl *sc);
int xe_sysctrl_init(struct xe_device *xe);
void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
void xe_sysctrl_pm_resume(struct xe_device *xe);
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
new file mode 100644
index 000000000000..8a2e44f4f5e0
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -0,0 +1,88 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_device.h"
+#include "xe_irq.h"
+#include "xe_printk.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+#include "xe_sysctrl_mailbox.h"
+#include "xe_sysctrl_mailbox_types.h"
+
+static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
+ struct xe_sysctrl_mailbox_command *command)
+{
+ struct xe_sysctrl_event_response response;
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 count = 0;
+ size_t len;
+ int ret;
+
+ command->data_out = &response;
+ command->data_out_len = sizeof(response);
+
+ do {
+ memset(&response, 0, sizeof(response));
+
+ ret = xe_sysctrl_send_command(sc, command, &len);
+ if (ret) {
+ xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
+ return;
+ }
+
+ if (len != sizeof(response)) {
+ xe_err(xe, "sysctrl: unexpected pending event response length %zu\n", len);
+ return;
+ }
+
+ if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
+ xe_warn(xe, "[RAS]: counter threshold crossed\n");
+ } else {
+ xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
+ return;
+ }
+
+ if (++count > XE_SYSCTRL_EVENT_FLOOD) {
+ xe_err(xe, "sysctrl: event flooding\n");
+ return;
+ }
+
+ xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
+ } while (response.count);
+}
+
+static void xe_sysctrl_event_request_prep(struct xe_device *xe,
+ struct xe_sysctrl_app_msg_hdr *header,
+ struct xe_sysctrl_event_request *request)
+{
+ struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
+
+ header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
+ REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
+
+ request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
+ request->fn = PCI_FUNC(pdev->devfn);
+}
+
+/**
+ * xe_sysctrl_event() - Handler for System Controller events
+ * @sc: System Controller instance
+ *
+ * Handle events generated by System Controller.
+ */
+void xe_sysctrl_event(struct xe_sysctrl *sc)
+{
+ struct xe_sysctrl_mailbox_command command = {};
+ struct xe_sysctrl_event_request request = {};
+ struct xe_sysctrl_app_msg_hdr header = {};
+
+ xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
+
+ command.header = header;
+ command.data_in = &request;
+ command.data_in_len = sizeof(request);
+
+ xe_sysctrl_get_pending_event(sc, &command);
+}
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
new file mode 100644
index 000000000000..9a26ad758a0b
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
+#define _XE_SYSCTRL_EVENT_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_SYSCTRL_EVENT_DATA_LEN 59
+
+/* Modify as needed */
+#define XE_SYSCTRL_EVENT_FLOOD 16
+
+enum xe_sysctrl_event {
+ XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
+};
+
+/**
+ * struct xe_sysctrl_event_request - Request structure for pending event
+ */
+struct xe_sysctrl_event_request {
+ /** @vector: MSI-X vector that was triggered */
+ u32 vector;
+ /** @fn: Function index (0-7) of PCIe device */
+ u32 fn:8;
+ /** @reserved: Reserved for future use */
+ u32 reserved:24;
+ /** @reserved2: Reserved for future use */
+ u32 reserved2[2];
+} __packed;
+
+/**
+ * struct xe_sysctrl_event_response - Response structure for pending event
+ */
+struct xe_sysctrl_event_response {
+ /** @count: Number of pending events */
+ u32 count;
+ /** @event: Pending event */
+ enum xe_sysctrl_event event;
+ /** @timestamp: Timestamp of most recent event */
+ u64 timestamp;
+ /** @extended: Event has extended payload */
+ u32 extended:1;
+ /** @reserved: Reserved for future use */
+ u32 reserved:31;
+ /** @data: Generic event data */
+ u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
+} __packed;
+
+#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
index 91460be9e22c..d59a825597d3 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
+++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
@@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
#define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
+/* Command groups */
+enum xe_sysctrl_group {
+ XE_SYSCTRL_GROUP_GFSP = 0x01,
+};
+
+/* Commands supported by GFSP group */
+enum xe_sysctrl_gfsp_cmd {
+ XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
+};
+
void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
int xe_sysctrl_send_command(struct xe_sysctrl *sc,
struct xe_sysctrl_mailbox_command *cmd,
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
2026-04-07 11:06 ` [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-04-07 11:06 ` [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-04-07 11:06 ` Raag Jadav
2026-04-08 12:25 ` Mallesh, Koujalagi
2026-04-09 10:14 ` Tauro, Riana
2026-04-07 12:10 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev5) Patchwork
` (3 subsequent siblings)
6 siblings, 2 replies; 14+ messages in thread
From: Raag Jadav @ 2026-04-07 11:06 UTC (permalink / raw)
To: intel-xe
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty, Raag Jadav
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
---
v4: Fix Severity/Component logging (Mallesh)
s/xe_ras_error/xe_ras_error_class (Riana)
v5: Handle unexpected counter threshold crossed (Mallesh)
---
drivers/gpu/drm/xe/Makefile | 1 +
drivers/gpu/drm/xe/xe_ras.c | 96 +++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_ras.h | 14 ++++
drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++
drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
5 files changed, 186 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/xe/xe_ras.c
create mode 100644 drivers/gpu/drm/xe/xe_ras.h
create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index c0e820eeea30..f66561977a45 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -113,6 +113,7 @@ xe-y += xe_bb.o \
xe_pxp_submit.o \
xe_query.o \
xe_range_fence.o \
+ xe_ras.o \
xe_reg_sr.o \
xe_reg_whitelist.o \
xe_ring_ops.o \
diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
new file mode 100644
index 000000000000..6f84ade02057
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.c
@@ -0,0 +1,96 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#include "xe_printk.h"
+#include "xe_ras.h"
+#include "xe_ras_types.h"
+#include "xe_sysctrl.h"
+#include "xe_sysctrl_event_types.h"
+
+/* Severity of detected errors */
+enum xe_ras_severity {
+ XE_RAS_SEV_NOT_SUPPORTED = 0,
+ XE_RAS_SEV_CORRECTABLE,
+ XE_RAS_SEV_UNCORRECTABLE,
+ XE_RAS_SEV_INFORMATIONAL,
+ XE_RAS_SEV_MAX
+};
+
+/* Major IP blocks/components where errors can originate */
+enum xe_ras_component {
+ XE_RAS_COMP_NOT_SUPPORTED = 0,
+ XE_RAS_COMP_DEVICE_MEMORY,
+ XE_RAS_COMP_CORE_COMPUTE,
+ XE_RAS_COMP_RESERVED,
+ XE_RAS_COMP_PCIE,
+ XE_RAS_COMP_FABRIC,
+ XE_RAS_COMP_SOC_INTERNAL,
+ XE_RAS_COMP_MAX
+};
+
+static const char *const xe_ras_severities[] = {
+ [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_SEV_CORRECTABLE] = "Correctable",
+ [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
+ [XE_RAS_SEV_INFORMATIONAL] = "Informational",
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
+
+static const char *const xe_ras_components[] = {
+ [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
+ [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
+ [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
+ [XE_RAS_COMP_RESERVED] = "Reserved",
+ [XE_RAS_COMP_PCIE] = "PCIe",
+ [XE_RAS_COMP_FABRIC] = "Fabric",
+ [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
+
+static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
+{
+ if (sev >= XE_RAS_SEV_MAX)
+ sev = XE_RAS_SEV_NOT_SUPPORTED;
+
+ return xe_ras_severities[sev];
+}
+
+static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
+{
+ if (comp >= XE_RAS_COMP_MAX)
+ comp = XE_RAS_COMP_NOT_SUPPORTED;
+
+ return xe_ras_components[comp];
+}
+
+void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
+{
+ struct xe_ras_threshold_crossed_data *pending = (void *)&response->data;
+ struct xe_ras_error_class *errors = pending->counters;
+ struct xe_device *xe = sc_to_xe(sc);
+ u32 ncounters = pending->ncounters;
+ u32 cid, sev, comp, inst, cause;
+ u8 tile;
+
+ if (!ncounters || ncounters >= XE_RAS_NUM_COUNTERS) {
+ xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters);
+ return;
+ }
+
+ BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending));
+ xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters);
+
+ for (cid = 0; cid < ncounters; cid++) {
+ sev = errors[cid].common.severity;
+ comp = errors[cid].common.component;
+
+ tile = errors[cid].product.unit.tile;
+ inst = errors[cid].product.unit.instance;
+ cause = errors[cid].product.cause.cause;
+
+ xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
+ tile, inst, comp_to_str(xe, comp), sev_to_str(xe, sev), cause);
+ }
+}
diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
new file mode 100644
index 000000000000..92ee93d4e877
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_H_
+#define _XE_RAS_H_
+
+struct xe_sysctrl;
+struct xe_sysctrl_event_response;
+
+void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
new file mode 100644
index 000000000000..0e3ba9e81538
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_ras_types.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2026 Intel Corporation
+ */
+
+#ifndef _XE_RAS_TYPES_H_
+#define _XE_RAS_TYPES_H_
+
+#include <linux/types.h>
+
+#define XE_RAS_NUM_COUNTERS 16
+
+/**
+ * struct xe_ras_error_common - Error fields that are common across all products
+ */
+struct xe_ras_error_common {
+ /** @severity: Error severity */
+ u8 severity;
+ /** @component: IP block where error originated */
+ u8 component;
+} __packed;
+
+/**
+ * struct xe_ras_error_unit - Error unit information
+ */
+struct xe_ras_error_unit {
+ /** @tile: Tile identifier */
+ u8 tile;
+ /** @instance: Instance identifier specific to IP */
+ u32 instance;
+} __packed;
+
+/**
+ * struct xe_ras_error_cause - Error cause information
+ */
+struct xe_ras_error_cause {
+ /** @cause: Cause/checker */
+ u32 cause;
+ /** @reserved: For future use */
+ u8 reserved;
+} __packed;
+
+/**
+ * struct xe_ras_error_product - Error fields that are specific to the product
+ */
+struct xe_ras_error_product {
+ /** @unit: Unit within IP block */
+ struct xe_ras_error_unit unit;
+ /** @cause: Cause/checker */
+ struct xe_ras_error_cause cause;
+} __packed;
+
+/**
+ * struct xe_ras_error_class - Combines common and product-specific parts
+ */
+struct xe_ras_error_class {
+ /** @common: Common error type and component */
+ struct xe_ras_error_common common;
+ /** @product: Product-specific unit and cause */
+ struct xe_ras_error_product product;
+} __packed;
+
+/**
+ * struct xe_ras_threshold_crossed_data - Data for threshold crossed event
+ */
+struct xe_ras_threshold_crossed_data {
+ /** @ncounters: Number of error counters that crossed thresholds */
+ u32 ncounters;
+ /** @counters: Array of error counters that crossed threshold */
+ struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
+} __packed;
+
+#endif
diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
index 8a2e44f4f5e0..139ecd4aafcd 100644
--- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
+++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
@@ -6,6 +6,7 @@
#include "xe_device.h"
#include "xe_irq.h"
#include "xe_printk.h"
+#include "xe_ras.h"
#include "xe_sysctrl.h"
#include "xe_sysctrl_event_types.h"
#include "xe_sysctrl_mailbox.h"
@@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
}
if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
- xe_warn(xe, "[RAS]: counter threshold crossed\n");
+ xe_ras_threshold_crossed(sc, &response);
} else {
xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
return;
--
2.43.0
^ permalink raw reply related [flat|nested] 14+ messages in thread
* ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev5)
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
` (2 preceding siblings ...)
2026-04-07 11:06 ` [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-04-07 12:10 ` Patchwork
2026-04-07 12:11 ` ✓ CI.KUnit: success " Patchwork
` (2 subsequent siblings)
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-04-07 12:10 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev5)
URL : https://patchwork.freedesktop.org/series/160184/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
1f57ba1afceae32108bd24770069f764d940a0e4
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 1c90ff8d3c90471d1fd9e5e4d1b306e1ca2c9ee6
Author: Raag Jadav <raag.jadav@intel.com>
Date: Tue Apr 7 16:36:29 2026 +0530
drm/xe/ras: Introduce correctable error handling
Add initial support for correctable error handling which is serviced
using system controller event. Currently we only log the errors in
dmesg but this serves as a foundation for RAS infrastructure and will
be further extended to facilitate other RAS features.
Signed-off-by: Raag Jadav <raag.jadav@intel.com>
+ /mt/dim checkpatch 87b52c2ff4f00eff41866d728f82d2b109c397f7 drm-intel
fe42aac0a529 drm/xe/sysctrl: Add system controller interrupt handler
0763f39dae65 drm/xe/sysctrl: Add system controller event support
-:63: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#63:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 189 lines checked
1c90ff8d3c90 drm/xe/ras: Introduce correctable error handling
-:26: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#26:
new file mode 100644
-:69: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#69: FILE: drivers/gpu/drm/xe/xe_ras.c:39:
+};
+static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
-:80: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#80: FILE: drivers/gpu/drm/xe/xe_ras.c:50:
+};
+static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
total: 0 errors, 1 warnings, 2 checks, 205 lines checked
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ CI.KUnit: success for Introduce Xe Correctable Error Handling (rev5)
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
` (3 preceding siblings ...)
2026-04-07 12:10 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev5) Patchwork
@ 2026-04-07 12:11 ` Patchwork
2026-04-07 12:50 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-07 14:29 ` ✓ Xe.CI.FULL: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-04-07 12:11 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev5)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[12:10:36] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:10:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:11:12] Starting KUnit Kernel (1/1)...
[12:11:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:11:12] ================== guc_buf (11 subtests) ===================
[12:11:12] [PASSED] test_smallest
[12:11:12] [PASSED] test_largest
[12:11:12] [PASSED] test_granular
[12:11:12] [PASSED] test_unique
[12:11:12] [PASSED] test_overlap
[12:11:12] [PASSED] test_reusable
[12:11:12] [PASSED] test_too_big
[12:11:12] [PASSED] test_flush
[12:11:12] [PASSED] test_lookup
[12:11:12] [PASSED] test_data
[12:11:12] [PASSED] test_class
[12:11:12] ===================== [PASSED] guc_buf =====================
[12:11:12] =================== guc_dbm (7 subtests) ===================
[12:11:12] [PASSED] test_empty
[12:11:12] [PASSED] test_default
[12:11:12] ======================== test_size ========================
[12:11:12] [PASSED] 4
[12:11:12] [PASSED] 8
[12:11:12] [PASSED] 32
[12:11:12] [PASSED] 256
[12:11:12] ==================== [PASSED] test_size ====================
[12:11:12] ======================= test_reuse ========================
[12:11:12] [PASSED] 4
[12:11:12] [PASSED] 8
[12:11:12] [PASSED] 32
[12:11:12] [PASSED] 256
[12:11:12] =================== [PASSED] test_reuse ====================
[12:11:12] =================== test_range_overlap ====================
[12:11:12] [PASSED] 4
[12:11:12] [PASSED] 8
[12:11:12] [PASSED] 32
[12:11:12] [PASSED] 256
[12:11:12] =============== [PASSED] test_range_overlap ================
[12:11:12] =================== test_range_compact ====================
[12:11:12] [PASSED] 4
[12:11:12] [PASSED] 8
[12:11:12] [PASSED] 32
[12:11:12] [PASSED] 256
[12:11:12] =============== [PASSED] test_range_compact ================
[12:11:12] ==================== test_range_spare =====================
[12:11:12] [PASSED] 4
[12:11:12] [PASSED] 8
[12:11:12] [PASSED] 32
[12:11:12] [PASSED] 256
[12:11:12] ================ [PASSED] test_range_spare =================
[12:11:12] ===================== [PASSED] guc_dbm =====================
[12:11:12] =================== guc_idm (6 subtests) ===================
[12:11:12] [PASSED] bad_init
[12:11:12] [PASSED] no_init
[12:11:12] [PASSED] init_fini
[12:11:12] [PASSED] check_used
[12:11:12] [PASSED] check_quota
[12:11:12] [PASSED] check_all
[12:11:12] ===================== [PASSED] guc_idm =====================
[12:11:12] ================== no_relay (3 subtests) ===================
[12:11:12] [PASSED] xe_drops_guc2pf_if_not_ready
[12:11:12] [PASSED] xe_drops_guc2vf_if_not_ready
[12:11:12] [PASSED] xe_rejects_send_if_not_ready
[12:11:12] ==================== [PASSED] no_relay =====================
[12:11:12] ================== pf_relay (14 subtests) ==================
[12:11:12] [PASSED] pf_rejects_guc2pf_too_short
[12:11:12] [PASSED] pf_rejects_guc2pf_too_long
[12:11:12] [PASSED] pf_rejects_guc2pf_no_payload
[12:11:12] [PASSED] pf_fails_no_payload
[12:11:12] [PASSED] pf_fails_bad_origin
[12:11:12] [PASSED] pf_fails_bad_type
[12:11:12] [PASSED] pf_txn_reports_error
[12:11:12] [PASSED] pf_txn_sends_pf2guc
[12:11:12] [PASSED] pf_sends_pf2guc
[12:11:12] [SKIPPED] pf_loopback_nop
[12:11:12] [SKIPPED] pf_loopback_echo
[12:11:12] [SKIPPED] pf_loopback_fail
[12:11:12] [SKIPPED] pf_loopback_busy
[12:11:12] [SKIPPED] pf_loopback_retry
[12:11:12] ==================== [PASSED] pf_relay =====================
[12:11:12] ================== vf_relay (3 subtests) ===================
[12:11:12] [PASSED] vf_rejects_guc2vf_too_short
[12:11:12] [PASSED] vf_rejects_guc2vf_too_long
[12:11:12] [PASSED] vf_rejects_guc2vf_no_payload
[12:11:12] ==================== [PASSED] vf_relay =====================
[12:11:12] ================ pf_gt_config (9 subtests) =================
[12:11:12] [PASSED] fair_contexts_1vf
[12:11:12] [PASSED] fair_doorbells_1vf
[12:11:12] [PASSED] fair_ggtt_1vf
[12:11:12] ====================== fair_vram_1vf ======================
[12:11:12] [PASSED] 3.50 GiB
[12:11:12] [PASSED] 11.5 GiB
[12:11:12] [PASSED] 15.5 GiB
[12:11:12] [PASSED] 31.5 GiB
[12:11:12] [PASSED] 63.5 GiB
[12:11:12] [PASSED] 1.91 GiB
[12:11:12] ================== [PASSED] fair_vram_1vf ==================
[12:11:12] ================ fair_vram_1vf_admin_only =================
[12:11:12] [PASSED] 3.50 GiB
[12:11:12] [PASSED] 11.5 GiB
[12:11:12] [PASSED] 15.5 GiB
[12:11:12] [PASSED] 31.5 GiB
[12:11:12] [PASSED] 63.5 GiB
[12:11:12] [PASSED] 1.91 GiB
[12:11:12] ============ [PASSED] fair_vram_1vf_admin_only =============
[12:11:12] ====================== fair_contexts ======================
[12:11:12] [PASSED] 1 VF
[12:11:12] [PASSED] 2 VFs
[12:11:12] [PASSED] 3 VFs
[12:11:12] [PASSED] 4 VFs
[12:11:12] [PASSED] 5 VFs
[12:11:12] [PASSED] 6 VFs
[12:11:12] [PASSED] 7 VFs
[12:11:12] [PASSED] 8 VFs
[12:11:12] [PASSED] 9 VFs
[12:11:12] [PASSED] 10 VFs
[12:11:12] [PASSED] 11 VFs
[12:11:12] [PASSED] 12 VFs
[12:11:12] [PASSED] 13 VFs
[12:11:12] [PASSED] 14 VFs
[12:11:12] [PASSED] 15 VFs
[12:11:12] [PASSED] 16 VFs
[12:11:12] [PASSED] 17 VFs
[12:11:12] [PASSED] 18 VFs
[12:11:12] [PASSED] 19 VFs
[12:11:12] [PASSED] 20 VFs
[12:11:12] [PASSED] 21 VFs
[12:11:12] [PASSED] 22 VFs
[12:11:12] [PASSED] 23 VFs
[12:11:12] [PASSED] 24 VFs
[12:11:12] [PASSED] 25 VFs
[12:11:12] [PASSED] 26 VFs
[12:11:12] [PASSED] 27 VFs
[12:11:12] [PASSED] 28 VFs
[12:11:12] [PASSED] 29 VFs
[12:11:12] [PASSED] 30 VFs
[12:11:12] [PASSED] 31 VFs
[12:11:12] [PASSED] 32 VFs
[12:11:12] [PASSED] 33 VFs
[12:11:12] [PASSED] 34 VFs
[12:11:12] [PASSED] 35 VFs
[12:11:12] [PASSED] 36 VFs
[12:11:12] [PASSED] 37 VFs
[12:11:12] [PASSED] 38 VFs
[12:11:12] [PASSED] 39 VFs
[12:11:12] [PASSED] 40 VFs
[12:11:12] [PASSED] 41 VFs
[12:11:12] [PASSED] 42 VFs
[12:11:12] [PASSED] 43 VFs
[12:11:12] [PASSED] 44 VFs
[12:11:12] [PASSED] 45 VFs
[12:11:12] [PASSED] 46 VFs
[12:11:12] [PASSED] 47 VFs
[12:11:12] [PASSED] 48 VFs
[12:11:12] [PASSED] 49 VFs
[12:11:12] [PASSED] 50 VFs
[12:11:12] [PASSED] 51 VFs
[12:11:12] [PASSED] 52 VFs
[12:11:12] [PASSED] 53 VFs
[12:11:12] [PASSED] 54 VFs
[12:11:12] [PASSED] 55 VFs
[12:11:12] [PASSED] 56 VFs
[12:11:12] [PASSED] 57 VFs
[12:11:12] [PASSED] 58 VFs
[12:11:12] [PASSED] 59 VFs
[12:11:12] [PASSED] 60 VFs
[12:11:12] [PASSED] 61 VFs
[12:11:12] [PASSED] 62 VFs
[12:11:12] [PASSED] 63 VFs
[12:11:12] ================== [PASSED] fair_contexts ==================
[12:11:12] ===================== fair_doorbells ======================
[12:11:12] [PASSED] 1 VF
[12:11:12] [PASSED] 2 VFs
[12:11:12] [PASSED] 3 VFs
[12:11:12] [PASSED] 4 VFs
[12:11:12] [PASSED] 5 VFs
[12:11:12] [PASSED] 6 VFs
[12:11:12] [PASSED] 7 VFs
[12:11:12] [PASSED] 8 VFs
[12:11:12] [PASSED] 9 VFs
[12:11:12] [PASSED] 10 VFs
[12:11:12] [PASSED] 11 VFs
[12:11:12] [PASSED] 12 VFs
[12:11:12] [PASSED] 13 VFs
[12:11:12] [PASSED] 14 VFs
[12:11:12] [PASSED] 15 VFs
[12:11:12] [PASSED] 16 VFs
[12:11:12] [PASSED] 17 VFs
[12:11:12] [PASSED] 18 VFs
[12:11:12] [PASSED] 19 VFs
[12:11:12] [PASSED] 20 VFs
[12:11:12] [PASSED] 21 VFs
[12:11:12] [PASSED] 22 VFs
[12:11:12] [PASSED] 23 VFs
[12:11:12] [PASSED] 24 VFs
[12:11:12] [PASSED] 25 VFs
[12:11:12] [PASSED] 26 VFs
[12:11:12] [PASSED] 27 VFs
[12:11:12] [PASSED] 28 VFs
[12:11:12] [PASSED] 29 VFs
[12:11:12] [PASSED] 30 VFs
[12:11:12] [PASSED] 31 VFs
[12:11:12] [PASSED] 32 VFs
[12:11:12] [PASSED] 33 VFs
[12:11:12] [PASSED] 34 VFs
[12:11:12] [PASSED] 35 VFs
[12:11:12] [PASSED] 36 VFs
[12:11:12] [PASSED] 37 VFs
[12:11:12] [PASSED] 38 VFs
[12:11:12] [PASSED] 39 VFs
[12:11:12] [PASSED] 40 VFs
[12:11:12] [PASSED] 41 VFs
[12:11:12] [PASSED] 42 VFs
[12:11:12] [PASSED] 43 VFs
[12:11:12] [PASSED] 44 VFs
[12:11:12] [PASSED] 45 VFs
[12:11:12] [PASSED] 46 VFs
[12:11:12] [PASSED] 47 VFs
[12:11:12] [PASSED] 48 VFs
[12:11:12] [PASSED] 49 VFs
[12:11:12] [PASSED] 50 VFs
[12:11:12] [PASSED] 51 VFs
[12:11:12] [PASSED] 52 VFs
[12:11:12] [PASSED] 53 VFs
[12:11:12] [PASSED] 54 VFs
[12:11:12] [PASSED] 55 VFs
[12:11:12] [PASSED] 56 VFs
[12:11:12] [PASSED] 57 VFs
[12:11:12] [PASSED] 58 VFs
[12:11:12] [PASSED] 59 VFs
[12:11:12] [PASSED] 60 VFs
[12:11:12] [PASSED] 61 VFs
[12:11:12] [PASSED] 62 VFs
[12:11:12] [PASSED] 63 VFs
[12:11:12] ================= [PASSED] fair_doorbells ==================
[12:11:12] ======================== fair_ggtt ========================
[12:11:12] [PASSED] 1 VF
[12:11:12] [PASSED] 2 VFs
[12:11:12] [PASSED] 3 VFs
[12:11:12] [PASSED] 4 VFs
[12:11:12] [PASSED] 5 VFs
[12:11:12] [PASSED] 6 VFs
[12:11:12] [PASSED] 7 VFs
[12:11:12] [PASSED] 8 VFs
[12:11:12] [PASSED] 9 VFs
[12:11:12] [PASSED] 10 VFs
[12:11:12] [PASSED] 11 VFs
[12:11:12] [PASSED] 12 VFs
[12:11:12] [PASSED] 13 VFs
[12:11:12] [PASSED] 14 VFs
[12:11:12] [PASSED] 15 VFs
[12:11:12] [PASSED] 16 VFs
[12:11:12] [PASSED] 17 VFs
[12:11:12] [PASSED] 18 VFs
[12:11:12] [PASSED] 19 VFs
[12:11:12] [PASSED] 20 VFs
[12:11:12] [PASSED] 21 VFs
[12:11:12] [PASSED] 22 VFs
[12:11:12] [PASSED] 23 VFs
[12:11:12] [PASSED] 24 VFs
[12:11:12] [PASSED] 25 VFs
[12:11:12] [PASSED] 26 VFs
[12:11:12] [PASSED] 27 VFs
[12:11:12] [PASSED] 28 VFs
[12:11:12] [PASSED] 29 VFs
[12:11:12] [PASSED] 30 VFs
[12:11:12] [PASSED] 31 VFs
[12:11:12] [PASSED] 32 VFs
[12:11:12] [PASSED] 33 VFs
[12:11:12] [PASSED] 34 VFs
[12:11:12] [PASSED] 35 VFs
[12:11:12] [PASSED] 36 VFs
[12:11:12] [PASSED] 37 VFs
[12:11:12] [PASSED] 38 VFs
[12:11:12] [PASSED] 39 VFs
[12:11:12] [PASSED] 40 VFs
[12:11:12] [PASSED] 41 VFs
[12:11:12] [PASSED] 42 VFs
[12:11:12] [PASSED] 43 VFs
[12:11:12] [PASSED] 44 VFs
[12:11:12] [PASSED] 45 VFs
[12:11:12] [PASSED] 46 VFs
[12:11:12] [PASSED] 47 VFs
[12:11:12] [PASSED] 48 VFs
[12:11:12] [PASSED] 49 VFs
[12:11:12] [PASSED] 50 VFs
[12:11:12] [PASSED] 51 VFs
[12:11:12] [PASSED] 52 VFs
[12:11:12] [PASSED] 53 VFs
[12:11:12] [PASSED] 54 VFs
[12:11:12] [PASSED] 55 VFs
[12:11:12] [PASSED] 56 VFs
[12:11:12] [PASSED] 57 VFs
[12:11:12] [PASSED] 58 VFs
[12:11:12] [PASSED] 59 VFs
[12:11:12] [PASSED] 60 VFs
[12:11:12] [PASSED] 61 VFs
[12:11:12] [PASSED] 62 VFs
[12:11:12] [PASSED] 63 VFs
[12:11:12] ==================== [PASSED] fair_ggtt ====================
[12:11:12] ======================== fair_vram ========================
[12:11:12] [PASSED] 1 VF
[12:11:12] [PASSED] 2 VFs
[12:11:12] [PASSED] 3 VFs
[12:11:12] [PASSED] 4 VFs
[12:11:12] [PASSED] 5 VFs
[12:11:12] [PASSED] 6 VFs
[12:11:12] [PASSED] 7 VFs
[12:11:12] [PASSED] 8 VFs
[12:11:12] [PASSED] 9 VFs
[12:11:12] [PASSED] 10 VFs
[12:11:12] [PASSED] 11 VFs
[12:11:12] [PASSED] 12 VFs
[12:11:12] [PASSED] 13 VFs
[12:11:12] [PASSED] 14 VFs
[12:11:12] [PASSED] 15 VFs
[12:11:12] [PASSED] 16 VFs
[12:11:12] [PASSED] 17 VFs
[12:11:12] [PASSED] 18 VFs
[12:11:12] [PASSED] 19 VFs
[12:11:12] [PASSED] 20 VFs
[12:11:12] [PASSED] 21 VFs
[12:11:12] [PASSED] 22 VFs
[12:11:12] [PASSED] 23 VFs
[12:11:12] [PASSED] 24 VFs
[12:11:12] [PASSED] 25 VFs
[12:11:12] [PASSED] 26 VFs
[12:11:12] [PASSED] 27 VFs
[12:11:12] [PASSED] 28 VFs
[12:11:12] [PASSED] 29 VFs
[12:11:12] [PASSED] 30 VFs
[12:11:12] [PASSED] 31 VFs
[12:11:12] [PASSED] 32 VFs
[12:11:12] [PASSED] 33 VFs
[12:11:12] [PASSED] 34 VFs
[12:11:12] [PASSED] 35 VFs
[12:11:12] [PASSED] 36 VFs
[12:11:12] [PASSED] 37 VFs
[12:11:12] [PASSED] 38 VFs
[12:11:12] [PASSED] 39 VFs
[12:11:12] [PASSED] 40 VFs
[12:11:12] [PASSED] 41 VFs
[12:11:12] [PASSED] 42 VFs
[12:11:12] [PASSED] 43 VFs
[12:11:12] [PASSED] 44 VFs
[12:11:12] [PASSED] 45 VFs
[12:11:12] [PASSED] 46 VFs
[12:11:12] [PASSED] 47 VFs
[12:11:12] [PASSED] 48 VFs
[12:11:12] [PASSED] 49 VFs
[12:11:12] [PASSED] 50 VFs
[12:11:12] [PASSED] 51 VFs
[12:11:12] [PASSED] 52 VFs
[12:11:12] [PASSED] 53 VFs
[12:11:12] [PASSED] 54 VFs
[12:11:12] [PASSED] 55 VFs
[12:11:12] [PASSED] 56 VFs
[12:11:12] [PASSED] 57 VFs
[12:11:12] [PASSED] 58 VFs
[12:11:12] [PASSED] 59 VFs
[12:11:12] [PASSED] 60 VFs
[12:11:12] [PASSED] 61 VFs
[12:11:12] [PASSED] 62 VFs
[12:11:12] [PASSED] 63 VFs
[12:11:12] ==================== [PASSED] fair_vram ====================
[12:11:12] ================== [PASSED] pf_gt_config ===================
[12:11:12] ===================== lmtt (1 subtest) =====================
[12:11:12] ======================== test_ops =========================
[12:11:12] [PASSED] 2-level
[12:11:12] [PASSED] multi-level
[12:11:12] ==================== [PASSED] test_ops =====================
[12:11:12] ====================== [PASSED] lmtt =======================
[12:11:12] ================= pf_service (11 subtests) =================
[12:11:12] [PASSED] pf_negotiate_any
[12:11:12] [PASSED] pf_negotiate_base_match
[12:11:12] [PASSED] pf_negotiate_base_newer
[12:11:12] [PASSED] pf_negotiate_base_next
[12:11:12] [SKIPPED] pf_negotiate_base_older
[12:11:12] [PASSED] pf_negotiate_base_prev
[12:11:12] [PASSED] pf_negotiate_latest_match
[12:11:12] [PASSED] pf_negotiate_latest_newer
[12:11:12] [PASSED] pf_negotiate_latest_next
[12:11:12] [SKIPPED] pf_negotiate_latest_older
[12:11:12] [SKIPPED] pf_negotiate_latest_prev
[12:11:12] =================== [PASSED] pf_service ====================
[12:11:12] ================= xe_guc_g2g (2 subtests) ==================
[12:11:12] ============== xe_live_guc_g2g_kunit_default ==============
[12:11:12] ========= [SKIPPED] xe_live_guc_g2g_kunit_default ==========
[12:11:12] ============== xe_live_guc_g2g_kunit_allmem ===============
[12:11:12] ========== [SKIPPED] xe_live_guc_g2g_kunit_allmem ==========
[12:11:12] =================== [SKIPPED] xe_guc_g2g ===================
[12:11:12] =================== xe_mocs (2 subtests) ===================
[12:11:12] ================ xe_live_mocs_kernel_kunit ================
[12:11:12] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[12:11:12] ================ xe_live_mocs_reset_kunit =================
[12:11:12] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[12:11:12] ==================== [SKIPPED] xe_mocs =====================
[12:11:12] ================= xe_migrate (2 subtests) ==================
[12:11:12] ================= xe_migrate_sanity_kunit =================
[12:11:12] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[12:11:12] ================== xe_validate_ccs_kunit ==================
[12:11:12] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[12:11:12] =================== [SKIPPED] xe_migrate ===================
[12:11:12] ================== xe_dma_buf (1 subtest) ==================
[12:11:12] ==================== xe_dma_buf_kunit =====================
[12:11:12] ================ [SKIPPED] xe_dma_buf_kunit ================
[12:11:12] =================== [SKIPPED] xe_dma_buf ===================
[12:11:12] ================= xe_bo_shrink (1 subtest) =================
[12:11:12] =================== xe_bo_shrink_kunit ====================
[12:11:12] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[12:11:12] ================== [SKIPPED] xe_bo_shrink ==================
[12:11:12] ==================== xe_bo (2 subtests) ====================
[12:11:12] ================== xe_ccs_migrate_kunit ===================
[12:11:12] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[12:11:12] ==================== xe_bo_evict_kunit ====================
[12:11:12] =============== [SKIPPED] xe_bo_evict_kunit ================
[12:11:12] ===================== [SKIPPED] xe_bo ======================
[12:11:12] ==================== args (13 subtests) ====================
[12:11:12] [PASSED] count_args_test
[12:11:12] [PASSED] call_args_example
[12:11:12] [PASSED] call_args_test
[12:11:12] [PASSED] drop_first_arg_example
[12:11:12] [PASSED] drop_first_arg_test
[12:11:12] [PASSED] first_arg_example
[12:11:12] [PASSED] first_arg_test
[12:11:12] [PASSED] last_arg_example
[12:11:12] [PASSED] last_arg_test
[12:11:12] [PASSED] pick_arg_example
[12:11:12] [PASSED] if_args_example
[12:11:12] [PASSED] if_args_test
[12:11:12] [PASSED] sep_comma_example
[12:11:12] ====================== [PASSED] args =======================
[12:11:12] =================== xe_pci (3 subtests) ====================
[12:11:12] ==================== check_graphics_ip ====================
[12:11:12] [PASSED] 12.00 Xe_LP
[12:11:12] [PASSED] 12.10 Xe_LP+
[12:11:12] [PASSED] 12.55 Xe_HPG
[12:11:12] [PASSED] 12.60 Xe_HPC
[12:11:12] [PASSED] 12.70 Xe_LPG
[12:11:12] [PASSED] 12.71 Xe_LPG
[12:11:12] [PASSED] 12.74 Xe_LPG+
[12:11:12] [PASSED] 20.01 Xe2_HPG
[12:11:12] [PASSED] 20.02 Xe2_HPG
[12:11:12] [PASSED] 20.04 Xe2_LPG
[12:11:12] [PASSED] 30.00 Xe3_LPG
[12:11:12] [PASSED] 30.01 Xe3_LPG
[12:11:12] [PASSED] 30.03 Xe3_LPG
[12:11:12] [PASSED] 30.04 Xe3_LPG
[12:11:12] [PASSED] 30.05 Xe3_LPG
[12:11:12] [PASSED] 35.10 Xe3p_LPG
[12:11:12] [PASSED] 35.11 Xe3p_XPC
[12:11:12] ================ [PASSED] check_graphics_ip ================
[12:11:12] ===================== check_media_ip ======================
[12:11:12] [PASSED] 12.00 Xe_M
[12:11:12] [PASSED] 12.55 Xe_HPM
[12:11:12] [PASSED] 13.00 Xe_LPM+
[12:11:12] [PASSED] 13.01 Xe2_HPM
[12:11:12] [PASSED] 20.00 Xe2_LPM
[12:11:12] [PASSED] 30.00 Xe3_LPM
[12:11:12] [PASSED] 30.02 Xe3_LPM
[12:11:12] [PASSED] 35.00 Xe3p_LPM
[12:11:12] [PASSED] 35.03 Xe3p_HPM
[12:11:12] ================= [PASSED] check_media_ip ==================
[12:11:12] =================== check_platform_desc ===================
[12:11:12] [PASSED] 0x9A60 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A68 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A70 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A40 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A49 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A59 (TIGERLAKE)
[12:11:12] [PASSED] 0x9A78 (TIGERLAKE)
[12:11:12] [PASSED] 0x9AC0 (TIGERLAKE)
[12:11:12] [PASSED] 0x9AC9 (TIGERLAKE)
[12:11:12] [PASSED] 0x9AD9 (TIGERLAKE)
[12:11:12] [PASSED] 0x9AF8 (TIGERLAKE)
[12:11:12] [PASSED] 0x4C80 (ROCKETLAKE)
[12:11:12] [PASSED] 0x4C8A (ROCKETLAKE)
[12:11:12] [PASSED] 0x4C8B (ROCKETLAKE)
[12:11:12] [PASSED] 0x4C8C (ROCKETLAKE)
[12:11:12] [PASSED] 0x4C90 (ROCKETLAKE)
[12:11:12] [PASSED] 0x4C9A (ROCKETLAKE)
[12:11:12] [PASSED] 0x4680 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4682 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4688 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x468A (ALDERLAKE_S)
[12:11:12] [PASSED] 0x468B (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4690 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4692 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4693 (ALDERLAKE_S)
[12:11:12] [PASSED] 0x46A0 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46A1 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46A2 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46A3 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46A6 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46A8 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46AA (ALDERLAKE_P)
[12:11:12] [PASSED] 0x462A (ALDERLAKE_P)
[12:11:12] [PASSED] 0x4626 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x4628 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46B0 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46B1 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46B2 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46B3 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46C0 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46C1 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46C2 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46C3 (ALDERLAKE_P)
[12:11:12] [PASSED] 0x46D0 (ALDERLAKE_N)
[12:11:12] [PASSED] 0x46D1 (ALDERLAKE_N)
[12:11:12] [PASSED] 0x46D2 (ALDERLAKE_N)
[12:11:12] [PASSED] 0x46D3 (ALDERLAKE_N)
[12:11:12] [PASSED] 0x46D4 (ALDERLAKE_N)
[12:11:12] [PASSED] 0xA721 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7A1 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7A9 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7AC (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7AD (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA720 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7A0 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7A8 (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7AA (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA7AB (ALDERLAKE_P)
[12:11:12] [PASSED] 0xA780 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA781 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA782 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA783 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA788 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA789 (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA78A (ALDERLAKE_S)
[12:11:12] [PASSED] 0xA78B (ALDERLAKE_S)
[12:11:12] [PASSED] 0x4905 (DG1)
[12:11:12] [PASSED] 0x4906 (DG1)
[12:11:12] [PASSED] 0x4907 (DG1)
[12:11:12] [PASSED] 0x4908 (DG1)
[12:11:12] [PASSED] 0x4909 (DG1)
[12:11:12] [PASSED] 0x56C0 (DG2)
[12:11:12] [PASSED] 0x56C2 (DG2)
[12:11:12] [PASSED] 0x56C1 (DG2)
[12:11:12] [PASSED] 0x7D51 (METEORLAKE)
[12:11:12] [PASSED] 0x7DD1 (METEORLAKE)
[12:11:12] [PASSED] 0x7D41 (METEORLAKE)
[12:11:12] [PASSED] 0x7D67 (METEORLAKE)
[12:11:12] [PASSED] 0xB640 (METEORLAKE)
[12:11:12] [PASSED] 0x56A0 (DG2)
[12:11:12] [PASSED] 0x56A1 (DG2)
[12:11:12] [PASSED] 0x56A2 (DG2)
[12:11:12] [PASSED] 0x56BE (DG2)
[12:11:12] [PASSED] 0x56BF (DG2)
[12:11:12] [PASSED] 0x5690 (DG2)
[12:11:12] [PASSED] 0x5691 (DG2)
[12:11:12] [PASSED] 0x5692 (DG2)
[12:11:12] [PASSED] 0x56A5 (DG2)
[12:11:12] [PASSED] 0x56A6 (DG2)
[12:11:12] [PASSED] 0x56B0 (DG2)
[12:11:12] [PASSED] 0x56B1 (DG2)
[12:11:12] [PASSED] 0x56BA (DG2)
[12:11:12] [PASSED] 0x56BB (DG2)
[12:11:12] [PASSED] 0x56BC (DG2)
[12:11:12] [PASSED] 0x56BD (DG2)
[12:11:12] [PASSED] 0x5693 (DG2)
[12:11:12] [PASSED] 0x5694 (DG2)
[12:11:12] [PASSED] 0x5695 (DG2)
[12:11:12] [PASSED] 0x56A3 (DG2)
[12:11:12] [PASSED] 0x56A4 (DG2)
[12:11:12] [PASSED] 0x56B2 (DG2)
[12:11:12] [PASSED] 0x56B3 (DG2)
[12:11:12] [PASSED] 0x5696 (DG2)
[12:11:12] [PASSED] 0x5697 (DG2)
[12:11:12] [PASSED] 0xB69 (PVC)
[12:11:12] [PASSED] 0xB6E (PVC)
[12:11:12] [PASSED] 0xBD4 (PVC)
[12:11:12] [PASSED] 0xBD5 (PVC)
[12:11:12] [PASSED] 0xBD6 (PVC)
[12:11:12] [PASSED] 0xBD7 (PVC)
[12:11:12] [PASSED] 0xBD8 (PVC)
[12:11:12] [PASSED] 0xBD9 (PVC)
[12:11:12] [PASSED] 0xBDA (PVC)
[12:11:12] [PASSED] 0xBDB (PVC)
[12:11:12] [PASSED] 0xBE0 (PVC)
[12:11:12] [PASSED] 0xBE1 (PVC)
[12:11:12] [PASSED] 0xBE5 (PVC)
[12:11:12] [PASSED] 0x7D40 (METEORLAKE)
[12:11:12] [PASSED] 0x7D45 (METEORLAKE)
[12:11:12] [PASSED] 0x7D55 (METEORLAKE)
[12:11:12] [PASSED] 0x7D60 (METEORLAKE)
[12:11:12] [PASSED] 0x7DD5 (METEORLAKE)
[12:11:12] [PASSED] 0x6420 (LUNARLAKE)
[12:11:12] [PASSED] 0x64A0 (LUNARLAKE)
[12:11:12] [PASSED] 0x64B0 (LUNARLAKE)
[12:11:12] [PASSED] 0xE202 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE209 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE20B (BATTLEMAGE)
[12:11:12] [PASSED] 0xE20C (BATTLEMAGE)
[12:11:12] [PASSED] 0xE20D (BATTLEMAGE)
[12:11:12] [PASSED] 0xE210 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE211 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE212 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE216 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE220 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE221 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE222 (BATTLEMAGE)
[12:11:12] [PASSED] 0xE223 (BATTLEMAGE)
[12:11:12] [PASSED] 0xB080 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB081 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB082 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB083 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB084 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB085 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB086 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB087 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB08F (PANTHERLAKE)
[12:11:12] [PASSED] 0xB090 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB0A0 (PANTHERLAKE)
[12:11:12] [PASSED] 0xB0B0 (PANTHERLAKE)
[12:11:12] [PASSED] 0xFD80 (PANTHERLAKE)
[12:11:12] [PASSED] 0xFD81 (PANTHERLAKE)
[12:11:12] [PASSED] 0xD740 (NOVALAKE_S)
[12:11:12] [PASSED] 0xD741 (NOVALAKE_S)
[12:11:12] [PASSED] 0xD742 (NOVALAKE_S)
[12:11:12] [PASSED] 0xD743 (NOVALAKE_S)
[12:11:12] [PASSED] 0xD744 (NOVALAKE_S)
[12:11:12] [PASSED] 0xD745 (NOVALAKE_S)
[12:11:12] [PASSED] 0x674C (CRESCENTISLAND)
[12:11:12] [PASSED] 0xD750 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD751 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD752 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD753 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD754 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD755 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD756 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD757 (NOVALAKE_P)
[12:11:12] [PASSED] 0xD75F (NOVALAKE_P)
[12:11:12] =============== [PASSED] check_platform_desc ===============
[12:11:12] ===================== [PASSED] xe_pci ======================
[12:11:12] =================== xe_rtp (2 subtests) ====================
[12:11:12] =============== xe_rtp_process_to_sr_tests ================
[12:11:12] [PASSED] coalesce-same-reg
[12:11:12] [PASSED] no-match-no-add
[12:11:12] [PASSED] match-or
[12:11:12] [PASSED] match-or-xfail
[12:11:12] [PASSED] no-match-no-add-multiple-rules
[12:11:12] [PASSED] two-regs-two-entries
[12:11:12] [PASSED] clr-one-set-other
[12:11:12] [PASSED] set-field
[12:11:12] [PASSED] conflict-duplicate
stty: 'standard input': Inappropriate ioctl for device
[12:11:12] [PASSED] conflict-not-disjoint
[12:11:12] [PASSED] conflict-reg-type
[12:11:12] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[12:11:12] ================== xe_rtp_process_tests ===================
[12:11:12] [PASSED] active1
[12:11:12] [PASSED] active2
[12:11:12] [PASSED] active-inactive
[12:11:12] [PASSED] inactive-active
[12:11:12] [PASSED] inactive-1st_or_active-inactive
[12:11:12] [PASSED] inactive-2nd_or_active-inactive
[12:11:12] [PASSED] inactive-last_or_active-inactive
[12:11:12] [PASSED] inactive-no_or_active-inactive
[12:11:12] ============== [PASSED] xe_rtp_process_tests ===============
[12:11:12] ===================== [PASSED] xe_rtp ======================
[12:11:12] ==================== xe_wa (1 subtest) =====================
[12:11:12] ======================== xe_wa_gt =========================
[12:11:12] [PASSED] TIGERLAKE B0
[12:11:12] [PASSED] DG1 A0
[12:11:12] [PASSED] DG1 B0
[12:11:12] [PASSED] ALDERLAKE_S A0
[12:11:12] [PASSED] ALDERLAKE_S B0
[12:11:12] [PASSED] ALDERLAKE_S C0
[12:11:12] [PASSED] ALDERLAKE_S D0
[12:11:12] [PASSED] ALDERLAKE_P A0
[12:11:12] [PASSED] ALDERLAKE_P B0
[12:11:12] [PASSED] ALDERLAKE_P C0
[12:11:12] [PASSED] ALDERLAKE_S RPLS D0
[12:11:12] [PASSED] ALDERLAKE_P RPLU E0
[12:11:12] [PASSED] DG2 G10 C0
[12:11:12] [PASSED] DG2 G11 B1
[12:11:12] [PASSED] DG2 G12 A1
[12:11:12] [PASSED] METEORLAKE 12.70(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:11:12] [PASSED] METEORLAKE 12.71(Xe_LPG) A0 13.00(Xe_LPM+) A0
[12:11:12] [PASSED] METEORLAKE 12.74(Xe_LPG+) A0 13.00(Xe_LPM+) A0
[12:11:12] [PASSED] LUNARLAKE 20.04(Xe2_LPG) A0 20.00(Xe2_LPM) A0
[12:11:12] [PASSED] LUNARLAKE 20.04(Xe2_LPG) B0 20.00(Xe2_LPM) A0
[12:11:12] [PASSED] BATTLEMAGE 20.01(Xe2_HPG) A0 13.01(Xe2_HPM) A1
[12:11:12] [PASSED] PANTHERLAKE 30.00(Xe3_LPG) A0 30.00(Xe3_LPM) A0
[12:11:12] ==================== [PASSED] xe_wa_gt =====================
[12:11:12] ====================== [PASSED] xe_wa ======================
[12:11:12] ============================================================
[12:11:12] Testing complete. Ran 597 tests: passed: 579, skipped: 18
[12:11:12] Elapsed time: 36.356s total, 4.240s configuring, 31.499s building, 0.590s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[12:11:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:11:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:11:38] Starting KUnit Kernel (1/1)...
[12:11:38] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:11:38] ============ drm_test_pick_cmdline (2 subtests) ============
[12:11:38] [PASSED] drm_test_pick_cmdline_res_1920_1080_60
[12:11:38] =============== drm_test_pick_cmdline_named ===============
[12:11:38] [PASSED] NTSC
[12:11:38] [PASSED] NTSC-J
[12:11:38] [PASSED] PAL
[12:11:38] [PASSED] PAL-M
[12:11:38] =========== [PASSED] drm_test_pick_cmdline_named ===========
[12:11:38] ============== [PASSED] drm_test_pick_cmdline ==============
[12:11:38] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[12:11:38] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[12:11:38] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[12:11:38] =========== drm_validate_clone_mode (2 subtests) ===========
[12:11:38] ============== drm_test_check_in_clone_mode ===============
[12:11:38] [PASSED] in_clone_mode
[12:11:38] [PASSED] not_in_clone_mode
[12:11:38] ========== [PASSED] drm_test_check_in_clone_mode ===========
[12:11:38] =============== drm_test_check_valid_clones ===============
[12:11:38] [PASSED] not_in_clone_mode
[12:11:38] [PASSED] valid_clone
[12:11:38] [PASSED] invalid_clone
[12:11:38] =========== [PASSED] drm_test_check_valid_clones ===========
[12:11:38] ============= [PASSED] drm_validate_clone_mode =============
[12:11:38] ============= drm_validate_modeset (1 subtest) =============
[12:11:38] [PASSED] drm_test_check_connector_changed_modeset
[12:11:38] ============== [PASSED] drm_validate_modeset ===============
[12:11:38] ====== drm_test_bridge_get_current_state (2 subtests) ======
[12:11:38] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[12:11:38] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[12:11:38] ======== [PASSED] drm_test_bridge_get_current_state ========
[12:11:38] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[12:11:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[12:11:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[12:11:38] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[12:11:38] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[12:11:38] ============== drm_bridge_alloc (2 subtests) ===============
[12:11:38] [PASSED] drm_test_drm_bridge_alloc_basic
[12:11:38] [PASSED] drm_test_drm_bridge_alloc_get_put
[12:11:38] ================ [PASSED] drm_bridge_alloc =================
[12:11:38] ============= drm_cmdline_parser (40 subtests) =============
[12:11:38] [PASSED] drm_test_cmdline_force_d_only
[12:11:38] [PASSED] drm_test_cmdline_force_D_only_dvi
[12:11:38] [PASSED] drm_test_cmdline_force_D_only_hdmi
[12:11:38] [PASSED] drm_test_cmdline_force_D_only_not_digital
[12:11:38] [PASSED] drm_test_cmdline_force_e_only
[12:11:38] [PASSED] drm_test_cmdline_res
[12:11:38] [PASSED] drm_test_cmdline_res_vesa
[12:11:38] [PASSED] drm_test_cmdline_res_vesa_rblank
[12:11:38] [PASSED] drm_test_cmdline_res_rblank
[12:11:38] [PASSED] drm_test_cmdline_res_bpp
[12:11:38] [PASSED] drm_test_cmdline_res_refresh
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[12:11:38] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[12:11:38] [PASSED] drm_test_cmdline_res_margins_force_on
[12:11:38] [PASSED] drm_test_cmdline_res_vesa_margins
[12:11:38] [PASSED] drm_test_cmdline_name
[12:11:38] [PASSED] drm_test_cmdline_name_bpp
[12:11:38] [PASSED] drm_test_cmdline_name_option
[12:11:38] [PASSED] drm_test_cmdline_name_bpp_option
[12:11:38] [PASSED] drm_test_cmdline_rotate_0
[12:11:38] [PASSED] drm_test_cmdline_rotate_90
[12:11:38] [PASSED] drm_test_cmdline_rotate_180
[12:11:38] [PASSED] drm_test_cmdline_rotate_270
[12:11:38] [PASSED] drm_test_cmdline_hmirror
[12:11:38] [PASSED] drm_test_cmdline_vmirror
[12:11:38] [PASSED] drm_test_cmdline_margin_options
[12:11:38] [PASSED] drm_test_cmdline_multiple_options
[12:11:38] [PASSED] drm_test_cmdline_bpp_extra_and_option
[12:11:38] [PASSED] drm_test_cmdline_extra_and_option
[12:11:38] [PASSED] drm_test_cmdline_freestanding_options
[12:11:38] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[12:11:38] [PASSED] drm_test_cmdline_panel_orientation
[12:11:38] ================ drm_test_cmdline_invalid =================
[12:11:38] [PASSED] margin_only
[12:11:38] [PASSED] interlace_only
[12:11:38] [PASSED] res_missing_x
[12:11:38] [PASSED] res_missing_y
[12:11:38] [PASSED] res_bad_y
[12:11:38] [PASSED] res_missing_y_bpp
[12:11:38] [PASSED] res_bad_bpp
[12:11:38] [PASSED] res_bad_refresh
[12:11:38] [PASSED] res_bpp_refresh_force_on_off
[12:11:38] [PASSED] res_invalid_mode
[12:11:38] [PASSED] res_bpp_wrong_place_mode
[12:11:38] [PASSED] name_bpp_refresh
[12:11:38] [PASSED] name_refresh
[12:11:38] [PASSED] name_refresh_wrong_mode
[12:11:38] [PASSED] name_refresh_invalid_mode
[12:11:38] [PASSED] rotate_multiple
[12:11:38] [PASSED] rotate_invalid_val
[12:11:38] [PASSED] rotate_truncated
[12:11:38] [PASSED] invalid_option
[12:11:38] [PASSED] invalid_tv_option
[12:11:38] [PASSED] truncated_tv_option
[12:11:38] ============ [PASSED] drm_test_cmdline_invalid =============
[12:11:38] =============== drm_test_cmdline_tv_options ===============
[12:11:38] [PASSED] NTSC
[12:11:38] [PASSED] NTSC_443
[12:11:38] [PASSED] NTSC_J
[12:11:38] [PASSED] PAL
[12:11:38] [PASSED] PAL_M
[12:11:38] [PASSED] PAL_N
[12:11:38] [PASSED] SECAM
[12:11:38] [PASSED] MONO_525
[12:11:38] [PASSED] MONO_625
[12:11:38] =========== [PASSED] drm_test_cmdline_tv_options ===========
[12:11:38] =============== [PASSED] drm_cmdline_parser ================
[12:11:38] ========== drmm_connector_hdmi_init (20 subtests) ==========
[12:11:38] [PASSED] drm_test_connector_hdmi_init_valid
[12:11:38] [PASSED] drm_test_connector_hdmi_init_bpc_8
[12:11:38] [PASSED] drm_test_connector_hdmi_init_bpc_10
[12:11:38] [PASSED] drm_test_connector_hdmi_init_bpc_12
[12:11:38] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[12:11:38] [PASSED] drm_test_connector_hdmi_init_bpc_null
[12:11:38] [PASSED] drm_test_connector_hdmi_init_formats_empty
[12:11:38] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[12:11:38] === drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:11:38] [PASSED] supported_formats=0x9 yuv420_allowed=1
[12:11:38] [PASSED] supported_formats=0x9 yuv420_allowed=0
[12:11:38] [PASSED] supported_formats=0x5 yuv420_allowed=1
[12:11:38] [PASSED] supported_formats=0x5 yuv420_allowed=0
[12:11:38] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[12:11:38] [PASSED] drm_test_connector_hdmi_init_null_ddc
[12:11:38] [PASSED] drm_test_connector_hdmi_init_null_product
[12:11:38] [PASSED] drm_test_connector_hdmi_init_null_vendor
[12:11:38] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[12:11:38] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[12:11:38] [PASSED] drm_test_connector_hdmi_init_product_valid
[12:11:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[12:11:38] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[12:11:38] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[12:11:38] ========= drm_test_connector_hdmi_init_type_valid =========
[12:11:38] [PASSED] HDMI-A
[12:11:38] [PASSED] HDMI-B
[12:11:38] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[12:11:38] ======== drm_test_connector_hdmi_init_type_invalid ========
[12:11:38] [PASSED] Unknown
[12:11:38] [PASSED] VGA
[12:11:38] [PASSED] DVI-I
[12:11:38] [PASSED] DVI-D
[12:11:38] [PASSED] DVI-A
[12:11:38] [PASSED] Composite
[12:11:38] [PASSED] SVIDEO
[12:11:38] [PASSED] LVDS
[12:11:38] [PASSED] Component
[12:11:38] [PASSED] DIN
[12:11:38] [PASSED] DP
[12:11:38] [PASSED] TV
[12:11:38] [PASSED] eDP
[12:11:38] [PASSED] Virtual
[12:11:38] [PASSED] DSI
[12:11:38] [PASSED] DPI
[12:11:38] [PASSED] Writeback
[12:11:38] [PASSED] SPI
[12:11:38] [PASSED] USB
[12:11:38] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[12:11:38] ============ [PASSED] drmm_connector_hdmi_init =============
[12:11:38] ============= drmm_connector_init (3 subtests) =============
[12:11:38] [PASSED] drm_test_drmm_connector_init
[12:11:38] [PASSED] drm_test_drmm_connector_init_null_ddc
[12:11:38] ========= drm_test_drmm_connector_init_type_valid =========
[12:11:38] [PASSED] Unknown
[12:11:38] [PASSED] VGA
[12:11:38] [PASSED] DVI-I
[12:11:38] [PASSED] DVI-D
[12:11:38] [PASSED] DVI-A
[12:11:38] [PASSED] Composite
[12:11:38] [PASSED] SVIDEO
[12:11:38] [PASSED] LVDS
[12:11:38] [PASSED] Component
[12:11:38] [PASSED] DIN
[12:11:38] [PASSED] DP
[12:11:38] [PASSED] HDMI-A
[12:11:38] [PASSED] HDMI-B
[12:11:38] [PASSED] TV
[12:11:38] [PASSED] eDP
[12:11:38] [PASSED] Virtual
[12:11:38] [PASSED] DSI
[12:11:38] [PASSED] DPI
[12:11:38] [PASSED] Writeback
[12:11:38] [PASSED] SPI
[12:11:38] [PASSED] USB
[12:11:38] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[12:11:38] =============== [PASSED] drmm_connector_init ===============
[12:11:38] ========= drm_connector_dynamic_init (6 subtests) ==========
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_init
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_init_properties
[12:11:38] ===== drm_test_drm_connector_dynamic_init_type_valid ======
[12:11:38] [PASSED] Unknown
[12:11:38] [PASSED] VGA
[12:11:38] [PASSED] DVI-I
[12:11:38] [PASSED] DVI-D
[12:11:38] [PASSED] DVI-A
[12:11:38] [PASSED] Composite
[12:11:38] [PASSED] SVIDEO
[12:11:38] [PASSED] LVDS
[12:11:38] [PASSED] Component
[12:11:38] [PASSED] DIN
[12:11:38] [PASSED] DP
[12:11:38] [PASSED] HDMI-A
[12:11:38] [PASSED] HDMI-B
[12:11:38] [PASSED] TV
[12:11:38] [PASSED] eDP
[12:11:38] [PASSED] Virtual
[12:11:38] [PASSED] DSI
[12:11:38] [PASSED] DPI
[12:11:38] [PASSED] Writeback
[12:11:38] [PASSED] SPI
[12:11:38] [PASSED] USB
[12:11:38] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[12:11:38] ======== drm_test_drm_connector_dynamic_init_name =========
[12:11:38] [PASSED] Unknown
[12:11:38] [PASSED] VGA
[12:11:38] [PASSED] DVI-I
[12:11:38] [PASSED] DVI-D
[12:11:38] [PASSED] DVI-A
[12:11:38] [PASSED] Composite
[12:11:38] [PASSED] SVIDEO
[12:11:38] [PASSED] LVDS
[12:11:38] [PASSED] Component
[12:11:38] [PASSED] DIN
[12:11:38] [PASSED] DP
[12:11:38] [PASSED] HDMI-A
[12:11:38] [PASSED] HDMI-B
[12:11:38] [PASSED] TV
[12:11:38] [PASSED] eDP
[12:11:38] [PASSED] Virtual
[12:11:38] [PASSED] DSI
[12:11:38] [PASSED] DPI
[12:11:38] [PASSED] Writeback
[12:11:38] [PASSED] SPI
[12:11:38] [PASSED] USB
[12:11:38] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[12:11:38] =========== [PASSED] drm_connector_dynamic_init ============
[12:11:38] ==== drm_connector_dynamic_register_early (4 subtests) =====
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[12:11:38] ====== [PASSED] drm_connector_dynamic_register_early =======
[12:11:38] ======= drm_connector_dynamic_register (7 subtests) ========
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[12:11:38] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[12:11:38] ========= [PASSED] drm_connector_dynamic_register ==========
[12:11:38] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[12:11:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[12:11:38] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[12:11:38] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[12:11:38] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[12:11:38] ========== drm_test_get_tv_mode_from_name_valid ===========
[12:11:38] [PASSED] NTSC
[12:11:38] [PASSED] NTSC-443
[12:11:38] [PASSED] NTSC-J
[12:11:38] [PASSED] PAL
[12:11:38] [PASSED] PAL-M
[12:11:38] [PASSED] PAL-N
[12:11:38] [PASSED] SECAM
[12:11:38] [PASSED] Mono
[12:11:38] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[12:11:38] [PASSED] drm_test_get_tv_mode_from_name_truncated
[12:11:38] ============ [PASSED] drm_get_tv_mode_from_name ============
[12:11:38] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[12:11:38] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[12:11:38] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[12:11:38] [PASSED] VIC 96
[12:11:38] [PASSED] VIC 97
[12:11:38] [PASSED] VIC 101
[12:11:38] [PASSED] VIC 102
[12:11:38] [PASSED] VIC 106
[12:11:38] [PASSED] VIC 107
[12:11:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[12:11:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[12:11:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[12:11:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[12:11:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[12:11:38] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[12:11:38] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[12:11:38] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[12:11:38] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[12:11:38] [PASSED] Automatic
[12:11:38] [PASSED] Full
[12:11:38] [PASSED] Limited 16:235
[12:11:38] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[12:11:38] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[12:11:38] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[12:11:38] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[12:11:38] === drm_test_drm_hdmi_connector_get_output_format_name ====
[12:11:38] [PASSED] RGB
[12:11:38] [PASSED] YUV 4:2:0
[12:11:38] [PASSED] YUV 4:2:2
[12:11:38] [PASSED] YUV 4:4:4
[12:11:38] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[12:11:38] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[12:11:38] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[12:11:38] ============= drm_damage_helper (21 subtests) ==============
[12:11:38] [PASSED] drm_test_damage_iter_no_damage
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_src_moved
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_not_visible
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[12:11:38] [PASSED] drm_test_damage_iter_no_damage_no_fb
[12:11:38] [PASSED] drm_test_damage_iter_simple_damage
[12:11:38] [PASSED] drm_test_damage_iter_single_damage
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_outside_src
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_src_moved
[12:11:38] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[12:11:38] [PASSED] drm_test_damage_iter_damage
[12:11:38] [PASSED] drm_test_damage_iter_damage_one_intersect
[12:11:38] [PASSED] drm_test_damage_iter_damage_one_outside
[12:11:38] [PASSED] drm_test_damage_iter_damage_src_moved
[12:11:38] [PASSED] drm_test_damage_iter_damage_not_visible
[12:11:38] ================ [PASSED] drm_damage_helper ================
[12:11:38] ============== drm_dp_mst_helper (3 subtests) ==============
[12:11:38] ============== drm_test_dp_mst_calc_pbn_mode ==============
[12:11:38] [PASSED] Clock 154000 BPP 30 DSC disabled
[12:11:38] [PASSED] Clock 234000 BPP 30 DSC disabled
[12:11:38] [PASSED] Clock 297000 BPP 24 DSC disabled
[12:11:38] [PASSED] Clock 332880 BPP 24 DSC enabled
[12:11:38] [PASSED] Clock 324540 BPP 24 DSC enabled
[12:11:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[12:11:38] ============== drm_test_dp_mst_calc_pbn_div ===============
[12:11:38] [PASSED] Link rate 2000000 lane count 4
[12:11:38] [PASSED] Link rate 2000000 lane count 2
[12:11:38] [PASSED] Link rate 2000000 lane count 1
[12:11:38] [PASSED] Link rate 1350000 lane count 4
[12:11:38] [PASSED] Link rate 1350000 lane count 2
[12:11:38] [PASSED] Link rate 1350000 lane count 1
[12:11:38] [PASSED] Link rate 1000000 lane count 4
[12:11:38] [PASSED] Link rate 1000000 lane count 2
[12:11:38] [PASSED] Link rate 1000000 lane count 1
[12:11:38] [PASSED] Link rate 810000 lane count 4
[12:11:38] [PASSED] Link rate 810000 lane count 2
[12:11:38] [PASSED] Link rate 810000 lane count 1
[12:11:38] [PASSED] Link rate 540000 lane count 4
[12:11:38] [PASSED] Link rate 540000 lane count 2
[12:11:38] [PASSED] Link rate 540000 lane count 1
[12:11:38] [PASSED] Link rate 270000 lane count 4
[12:11:38] [PASSED] Link rate 270000 lane count 2
[12:11:38] [PASSED] Link rate 270000 lane count 1
[12:11:38] [PASSED] Link rate 162000 lane count 4
[12:11:38] [PASSED] Link rate 162000 lane count 2
[12:11:38] [PASSED] Link rate 162000 lane count 1
[12:11:38] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[12:11:38] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[12:11:38] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[12:11:38] [PASSED] DP_POWER_UP_PHY with port number
[12:11:38] [PASSED] DP_POWER_DOWN_PHY with port number
[12:11:38] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[12:11:38] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[12:11:38] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[12:11:38] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[12:11:38] [PASSED] DP_QUERY_PAYLOAD with port number
[12:11:38] [PASSED] DP_QUERY_PAYLOAD with VCPI
[12:11:38] [PASSED] DP_REMOTE_DPCD_READ with port number
[12:11:38] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[12:11:38] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[12:11:38] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[12:11:38] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[12:11:38] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[12:11:38] [PASSED] DP_REMOTE_I2C_READ with port number
[12:11:38] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[12:11:38] [PASSED] DP_REMOTE_I2C_READ with transactions array
[12:11:38] [PASSED] DP_REMOTE_I2C_WRITE with port number
[12:11:38] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[12:11:38] [PASSED] DP_REMOTE_I2C_WRITE with data array
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[12:11:38] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[12:11:38] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[12:11:38] ================ [PASSED] drm_dp_mst_helper ================
[12:11:38] ================== drm_exec (7 subtests) ===================
[12:11:38] [PASSED] sanitycheck
[12:11:38] [PASSED] test_lock
[12:11:38] [PASSED] test_lock_unlock
[12:11:38] [PASSED] test_duplicates
[12:11:38] [PASSED] test_prepare
[12:11:38] [PASSED] test_prepare_array
[12:11:38] [PASSED] test_multiple_loops
[12:11:38] ==================== [PASSED] drm_exec =====================
[12:11:38] =========== drm_format_helper_test (17 subtests) ===========
[12:11:38] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[12:11:38] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[12:11:38] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[12:11:38] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[12:11:38] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[12:11:38] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[12:11:38] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[12:11:38] ============= drm_test_fb_xrgb8888_to_bgr888 ==============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[12:11:38] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[12:11:38] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[12:11:38] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[12:11:38] ============== drm_test_fb_xrgb8888_to_mono ===============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[12:11:38] ==================== drm_test_fb_swab =====================
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ================ [PASSED] drm_test_fb_swab =================
[12:11:38] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[12:11:38] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[12:11:38] [PASSED] single_pixel_source_buffer
[12:11:38] [PASSED] single_pixel_clip_rectangle
[12:11:38] [PASSED] well_known_colors
[12:11:38] [PASSED] destination_pitch
[12:11:38] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[12:11:38] ================= drm_test_fb_clip_offset =================
[12:11:38] [PASSED] pass through
[12:11:38] [PASSED] horizontal offset
[12:11:38] [PASSED] vertical offset
[12:11:38] [PASSED] horizontal and vertical offset
[12:11:38] [PASSED] horizontal offset (custom pitch)
[12:11:38] [PASSED] vertical offset (custom pitch)
[12:11:38] [PASSED] horizontal and vertical offset (custom pitch)
[12:11:38] ============= [PASSED] drm_test_fb_clip_offset =============
[12:11:38] =================== drm_test_fb_memcpy ====================
[12:11:38] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[12:11:38] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[12:11:38] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[12:11:38] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[12:11:38] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[12:11:38] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[12:11:38] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[12:11:38] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[12:11:38] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[12:11:38] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[12:11:38] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[12:11:38] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[12:11:38] =============== [PASSED] drm_test_fb_memcpy ================
[12:11:38] ============= [PASSED] drm_format_helper_test ==============
[12:11:38] ================= drm_format (18 subtests) =================
[12:11:38] [PASSED] drm_test_format_block_width_invalid
[12:11:38] [PASSED] drm_test_format_block_width_one_plane
[12:11:38] [PASSED] drm_test_format_block_width_two_plane
[12:11:38] [PASSED] drm_test_format_block_width_three_plane
[12:11:38] [PASSED] drm_test_format_block_width_tiled
[12:11:38] [PASSED] drm_test_format_block_height_invalid
[12:11:38] [PASSED] drm_test_format_block_height_one_plane
[12:11:38] [PASSED] drm_test_format_block_height_two_plane
[12:11:38] [PASSED] drm_test_format_block_height_three_plane
[12:11:38] [PASSED] drm_test_format_block_height_tiled
[12:11:38] [PASSED] drm_test_format_min_pitch_invalid
[12:11:38] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[12:11:38] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[12:11:38] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[12:11:38] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[12:11:38] [PASSED] drm_test_format_min_pitch_two_plane
[12:11:38] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[12:11:38] [PASSED] drm_test_format_min_pitch_tiled
[12:11:38] =================== [PASSED] drm_format ====================
[12:11:38] ============== drm_framebuffer (10 subtests) ===============
[12:11:38] ========== drm_test_framebuffer_check_src_coords ==========
[12:11:38] [PASSED] Success: source fits into fb
[12:11:38] [PASSED] Fail: overflowing fb with x-axis coordinate
[12:11:38] [PASSED] Fail: overflowing fb with y-axis coordinate
[12:11:38] [PASSED] Fail: overflowing fb with source width
[12:11:38] [PASSED] Fail: overflowing fb with source height
[12:11:38] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[12:11:38] [PASSED] drm_test_framebuffer_cleanup
[12:11:38] =============== drm_test_framebuffer_create ===============
[12:11:38] [PASSED] ABGR8888 normal sizes
[12:11:38] [PASSED] ABGR8888 max sizes
[12:11:38] [PASSED] ABGR8888 pitch greater than min required
[12:11:38] [PASSED] ABGR8888 pitch less than min required
[12:11:38] [PASSED] ABGR8888 Invalid width
[12:11:38] [PASSED] ABGR8888 Invalid buffer handle
[12:11:38] [PASSED] No pixel format
[12:11:38] [PASSED] ABGR8888 Width 0
[12:11:38] [PASSED] ABGR8888 Height 0
[12:11:38] [PASSED] ABGR8888 Out of bound height * pitch combination
[12:11:38] [PASSED] ABGR8888 Large buffer offset
[12:11:38] [PASSED] ABGR8888 Buffer offset for inexistent plane
[12:11:38] [PASSED] ABGR8888 Invalid flag
[12:11:38] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[12:11:38] [PASSED] ABGR8888 Valid buffer modifier
[12:11:38] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[12:11:38] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] NV12 Normal sizes
[12:11:38] [PASSED] NV12 Max sizes
[12:11:38] [PASSED] NV12 Invalid pitch
[12:11:38] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[12:11:38] [PASSED] NV12 different modifier per-plane
[12:11:38] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[12:11:38] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] NV12 Modifier for inexistent plane
[12:11:38] [PASSED] NV12 Handle for inexistent plane
[12:11:38] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[12:11:38] [PASSED] YVU420 Normal sizes
[12:11:38] [PASSED] YVU420 Max sizes
[12:11:38] [PASSED] YVU420 Invalid pitch
[12:11:38] [PASSED] YVU420 Different pitches
[12:11:38] [PASSED] YVU420 Different buffer offsets/pitches
[12:11:38] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[12:11:38] [PASSED] YVU420 Valid modifier
[12:11:38] [PASSED] YVU420 Different modifiers per plane
[12:11:38] [PASSED] YVU420 Modifier for inexistent plane
[12:11:38] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[12:11:38] [PASSED] X0L2 Normal sizes
[12:11:38] [PASSED] X0L2 Max sizes
[12:11:38] [PASSED] X0L2 Invalid pitch
[12:11:38] [PASSED] X0L2 Pitch greater than minimum required
[12:11:38] [PASSED] X0L2 Handle for inexistent plane
[12:11:38] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[12:11:38] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[12:11:38] [PASSED] X0L2 Valid modifier
[12:11:38] [PASSED] X0L2 Modifier for inexistent plane
[12:11:38] =========== [PASSED] drm_test_framebuffer_create ===========
[12:11:38] [PASSED] drm_test_framebuffer_free
[12:11:38] [PASSED] drm_test_framebuffer_init
[12:11:38] [PASSED] drm_test_framebuffer_init_bad_format
[12:11:38] [PASSED] drm_test_framebuffer_init_dev_mismatch
[12:11:38] [PASSED] drm_test_framebuffer_lookup
[12:11:38] [PASSED] drm_test_framebuffer_lookup_inexistent
[12:11:38] [PASSED] drm_test_framebuffer_modifiers_not_supported
[12:11:38] ================= [PASSED] drm_framebuffer =================
[12:11:38] ================ drm_gem_shmem (8 subtests) ================
[12:11:38] [PASSED] drm_gem_shmem_test_obj_create
[12:11:38] [PASSED] drm_gem_shmem_test_obj_create_private
[12:11:38] [PASSED] drm_gem_shmem_test_pin_pages
[12:11:38] [PASSED] drm_gem_shmem_test_vmap
[12:11:38] [PASSED] drm_gem_shmem_test_get_sg_table
[12:11:38] [PASSED] drm_gem_shmem_test_get_pages_sgt
[12:11:38] [PASSED] drm_gem_shmem_test_madvise
[12:11:38] [PASSED] drm_gem_shmem_test_purge
[12:11:38] ================== [PASSED] drm_gem_shmem ==================
[12:11:38] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[12:11:38] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420 =======
[12:11:38] [PASSED] Automatic
[12:11:38] [PASSED] Full
[12:11:38] [PASSED] Limited 16:235
[12:11:38] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[12:11:38] [PASSED] drm_test_check_disable_connector
[12:11:38] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[12:11:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[12:11:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[12:11:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[12:11:38] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[12:11:38] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[12:11:38] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[12:11:38] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[12:11:38] [PASSED] drm_test_check_output_bpc_dvi
[12:11:38] [PASSED] drm_test_check_output_bpc_format_vic_1
[12:11:38] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[12:11:38] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[12:11:38] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[12:11:38] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[12:11:38] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[12:11:38] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[12:11:38] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[12:11:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[12:11:38] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[12:11:38] [PASSED] drm_test_check_broadcast_rgb_value
[12:11:38] [PASSED] drm_test_check_bpc_8_value
[12:11:38] [PASSED] drm_test_check_bpc_10_value
[12:11:38] [PASSED] drm_test_check_bpc_12_value
[12:11:38] [PASSED] drm_test_check_format_value
[12:11:38] [PASSED] drm_test_check_tmds_char_value
[12:11:38] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[12:11:38] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[12:11:38] [PASSED] drm_test_check_mode_valid
[12:11:38] [PASSED] drm_test_check_mode_valid_reject
[12:11:38] [PASSED] drm_test_check_mode_valid_reject_rate
[12:11:38] [PASSED] drm_test_check_mode_valid_reject_max_clock
[12:11:38] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[12:11:38] = drm_atomic_helper_connector_hdmi_infoframes (5 subtests) =
[12:11:38] [PASSED] drm_test_check_infoframes
[12:11:38] [PASSED] drm_test_check_reject_avi_infoframe
[12:11:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_8
[12:11:38] [PASSED] drm_test_check_reject_hdr_infoframe_bpc_10
[12:11:38] [PASSED] drm_test_check_reject_audio_infoframe
[12:11:38] === [PASSED] drm_atomic_helper_connector_hdmi_infoframes ===
[12:11:38] ================= drm_managed (2 subtests) =================
[12:11:38] [PASSED] drm_test_managed_release_action
[12:11:38] [PASSED] drm_test_managed_run_action
[12:11:38] =================== [PASSED] drm_managed ===================
[12:11:38] =================== drm_mm (6 subtests) ====================
[12:11:38] [PASSED] drm_test_mm_init
[12:11:38] [PASSED] drm_test_mm_debug
[12:11:38] [PASSED] drm_test_mm_align32
[12:11:38] [PASSED] drm_test_mm_align64
[12:11:38] [PASSED] drm_test_mm_lowest
[12:11:38] [PASSED] drm_test_mm_highest
[12:11:38] ===================== [PASSED] drm_mm ======================
[12:11:38] ============= drm_modes_analog_tv (5 subtests) =============
[12:11:38] [PASSED] drm_test_modes_analog_tv_mono_576i
[12:11:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[12:11:38] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[12:11:38] [PASSED] drm_test_modes_analog_tv_pal_576i
[12:11:38] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[12:11:38] =============== [PASSED] drm_modes_analog_tv ===============
[12:11:38] ============== drm_plane_helper (2 subtests) ===============
[12:11:38] =============== drm_test_check_plane_state ================
[12:11:38] [PASSED] clipping_simple
[12:11:38] [PASSED] clipping_rotate_reflect
[12:11:38] [PASSED] positioning_simple
[12:11:38] [PASSED] upscaling
[12:11:38] [PASSED] downscaling
[12:11:38] [PASSED] rounding1
[12:11:38] [PASSED] rounding2
[12:11:38] [PASSED] rounding3
[12:11:38] [PASSED] rounding4
[12:11:38] =========== [PASSED] drm_test_check_plane_state ============
[12:11:38] =========== drm_test_check_invalid_plane_state ============
[12:11:38] [PASSED] positioning_invalid
[12:11:38] [PASSED] upscaling_invalid
[12:11:38] [PASSED] downscaling_invalid
[12:11:38] ======= [PASSED] drm_test_check_invalid_plane_state ========
[12:11:38] ================ [PASSED] drm_plane_helper =================
[12:11:38] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[12:11:38] ====== drm_test_connector_helper_tv_get_modes_check =======
[12:11:38] [PASSED] None
[12:11:38] [PASSED] PAL
[12:11:38] [PASSED] NTSC
[12:11:38] [PASSED] Both, NTSC Default
[12:11:38] [PASSED] Both, PAL Default
[12:11:38] [PASSED] Both, NTSC Default, with PAL on command-line
[12:11:38] [PASSED] Both, PAL Default, with NTSC on command-line
[12:11:38] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[12:11:39] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[12:11:39] ================== drm_rect (9 subtests) ===================
[12:11:39] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[12:11:39] [PASSED] drm_test_rect_clip_scaled_not_clipped
[12:11:39] [PASSED] drm_test_rect_clip_scaled_clipped
[12:11:39] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[12:11:39] ================= drm_test_rect_intersect =================
[12:11:39] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[12:11:39] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[12:11:39] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[12:11:39] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[12:11:39] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[12:11:39] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[12:11:39] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[12:11:39] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[12:11:39] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[12:11:39] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[12:11:39] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[12:11:39] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[12:11:39] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[12:11:39] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[12:11:39] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[12:11:39] ============= [PASSED] drm_test_rect_intersect =============
[12:11:39] ================ drm_test_rect_calc_hscale ================
[12:11:39] [PASSED] normal use
[12:11:39] [PASSED] out of max range
[12:11:39] [PASSED] out of min range
[12:11:39] [PASSED] zero dst
[12:11:39] [PASSED] negative src
[12:11:39] [PASSED] negative dst
[12:11:39] ============ [PASSED] drm_test_rect_calc_hscale ============
[12:11:39] ================ drm_test_rect_calc_vscale ================
[12:11:39] [PASSED] normal use
[12:11:39] [PASSED] out of max range
[12:11:39] [PASSED] out of min range
[12:11:39] [PASSED] zero dst
[12:11:39] [PASSED] negative src
[12:11:39] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[12:11:39] ============ [PASSED] drm_test_rect_calc_vscale ============
[12:11:39] ================== drm_test_rect_rotate ===================
[12:11:39] [PASSED] reflect-x
[12:11:39] [PASSED] reflect-y
[12:11:39] [PASSED] rotate-0
[12:11:39] [PASSED] rotate-90
[12:11:39] [PASSED] rotate-180
[12:11:39] [PASSED] rotate-270
[12:11:39] ============== [PASSED] drm_test_rect_rotate ===============
[12:11:39] ================ drm_test_rect_rotate_inv =================
[12:11:39] [PASSED] reflect-x
[12:11:39] [PASSED] reflect-y
[12:11:39] [PASSED] rotate-0
[12:11:39] [PASSED] rotate-90
[12:11:39] [PASSED] rotate-180
[12:11:39] [PASSED] rotate-270
[12:11:39] ============ [PASSED] drm_test_rect_rotate_inv =============
[12:11:39] ==================== [PASSED] drm_rect =====================
[12:11:39] ============ drm_sysfb_modeset_test (1 subtest) ============
[12:11:39] ============ drm_test_sysfb_build_fourcc_list =============
[12:11:39] [PASSED] no native formats
[12:11:39] [PASSED] XRGB8888 as native format
[12:11:39] [PASSED] remove duplicates
[12:11:39] [PASSED] convert alpha formats
[12:11:39] [PASSED] random formats
[12:11:39] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[12:11:39] ============= [PASSED] drm_sysfb_modeset_test ==============
[12:11:39] ================== drm_fixp (2 subtests) ===================
[12:11:39] [PASSED] drm_test_int2fixp
[12:11:39] [PASSED] drm_test_sm2fixp
[12:11:39] ==================== [PASSED] drm_fixp =====================
[12:11:39] ============================================================
[12:11:39] Testing complete. Ran 621 tests: passed: 621
[12:11:39] Elapsed time: 26.158s total, 1.707s configuring, 24.320s building, 0.130s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[12:11:39] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[12:11:40] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[12:11:50] Starting KUnit Kernel (1/1)...
[12:11:50] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[12:11:50] ================= ttm_device (5 subtests) ==================
[12:11:50] [PASSED] ttm_device_init_basic
[12:11:50] [PASSED] ttm_device_init_multiple
[12:11:50] [PASSED] ttm_device_fini_basic
[12:11:50] [PASSED] ttm_device_init_no_vma_man
[12:11:50] ================== ttm_device_init_pools ==================
[12:11:50] [PASSED] No DMA allocations, no DMA32 required
[12:11:50] [PASSED] DMA allocations, DMA32 required
[12:11:50] [PASSED] No DMA allocations, DMA32 required
[12:11:50] [PASSED] DMA allocations, no DMA32 required
[12:11:50] ============== [PASSED] ttm_device_init_pools ==============
[12:11:50] =================== [PASSED] ttm_device ====================
[12:11:50] ================== ttm_pool (8 subtests) ===================
[12:11:50] ================== ttm_pool_alloc_basic ===================
[12:11:50] [PASSED] One page
[12:11:50] [PASSED] More than one page
[12:11:50] [PASSED] Above the allocation limit
[12:11:50] [PASSED] One page, with coherent DMA mappings enabled
[12:11:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:11:50] ============== [PASSED] ttm_pool_alloc_basic ===============
[12:11:50] ============== ttm_pool_alloc_basic_dma_addr ==============
[12:11:50] [PASSED] One page
[12:11:50] [PASSED] More than one page
[12:11:50] [PASSED] Above the allocation limit
[12:11:50] [PASSED] One page, with coherent DMA mappings enabled
[12:11:50] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[12:11:50] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[12:11:50] [PASSED] ttm_pool_alloc_order_caching_match
[12:11:50] [PASSED] ttm_pool_alloc_caching_mismatch
[12:11:50] [PASSED] ttm_pool_alloc_order_mismatch
[12:11:50] [PASSED] ttm_pool_free_dma_alloc
[12:11:50] [PASSED] ttm_pool_free_no_dma_alloc
[12:11:50] [PASSED] ttm_pool_fini_basic
[12:11:50] ==================== [PASSED] ttm_pool =====================
[12:11:50] ================ ttm_resource (8 subtests) =================
[12:11:50] ================= ttm_resource_init_basic =================
[12:11:50] [PASSED] Init resource in TTM_PL_SYSTEM
[12:11:50] [PASSED] Init resource in TTM_PL_VRAM
[12:11:50] [PASSED] Init resource in a private placement
[12:11:50] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[12:11:50] ============= [PASSED] ttm_resource_init_basic =============
[12:11:50] [PASSED] ttm_resource_init_pinned
[12:11:50] [PASSED] ttm_resource_fini_basic
[12:11:50] [PASSED] ttm_resource_manager_init_basic
[12:11:50] [PASSED] ttm_resource_manager_usage_basic
[12:11:50] [PASSED] ttm_resource_manager_set_used_basic
[12:11:50] [PASSED] ttm_sys_man_alloc_basic
[12:11:50] [PASSED] ttm_sys_man_free_basic
[12:11:50] ================== [PASSED] ttm_resource ===================
[12:11:50] =================== ttm_tt (15 subtests) ===================
[12:11:50] ==================== ttm_tt_init_basic ====================
[12:11:50] [PASSED] Page-aligned size
[12:11:50] [PASSED] Extra pages requested
[12:11:50] ================ [PASSED] ttm_tt_init_basic ================
[12:11:50] [PASSED] ttm_tt_init_misaligned
[12:11:50] [PASSED] ttm_tt_fini_basic
[12:11:50] [PASSED] ttm_tt_fini_sg
[12:11:50] [PASSED] ttm_tt_fini_shmem
[12:11:50] [PASSED] ttm_tt_create_basic
[12:11:50] [PASSED] ttm_tt_create_invalid_bo_type
[12:11:50] [PASSED] ttm_tt_create_ttm_exists
[12:11:50] [PASSED] ttm_tt_create_failed
[12:11:50] [PASSED] ttm_tt_destroy_basic
[12:11:50] [PASSED] ttm_tt_populate_null_ttm
[12:11:50] [PASSED] ttm_tt_populate_populated_ttm
[12:11:50] [PASSED] ttm_tt_unpopulate_basic
[12:11:50] [PASSED] ttm_tt_unpopulate_empty_ttm
[12:11:50] [PASSED] ttm_tt_swapin_basic
[12:11:50] ===================== [PASSED] ttm_tt ======================
[12:11:50] =================== ttm_bo (14 subtests) ===================
[12:11:50] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[12:11:50] [PASSED] Cannot be interrupted and sleeps
[12:11:50] [PASSED] Cannot be interrupted, locks straight away
[12:11:50] [PASSED] Can be interrupted, sleeps
[12:11:50] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[12:11:50] [PASSED] ttm_bo_reserve_locked_no_sleep
[12:11:50] [PASSED] ttm_bo_reserve_no_wait_ticket
[12:11:50] [PASSED] ttm_bo_reserve_double_resv
[12:11:50] [PASSED] ttm_bo_reserve_interrupted
[12:11:50] [PASSED] ttm_bo_reserve_deadlock
[12:11:50] [PASSED] ttm_bo_unreserve_basic
[12:11:50] [PASSED] ttm_bo_unreserve_pinned
[12:11:50] [PASSED] ttm_bo_unreserve_bulk
[12:11:50] [PASSED] ttm_bo_fini_basic
[12:11:50] [PASSED] ttm_bo_fini_shared_resv
[12:11:50] [PASSED] ttm_bo_pin_basic
[12:11:50] [PASSED] ttm_bo_pin_unpin_resource
[12:11:50] [PASSED] ttm_bo_multiple_pin_one_unpin
[12:11:50] ===================== [PASSED] ttm_bo ======================
[12:11:50] ============== ttm_bo_validate (22 subtests) ===============
[12:11:50] ============== ttm_bo_init_reserved_sys_man ===============
[12:11:50] [PASSED] Buffer object for userspace
[12:11:50] [PASSED] Kernel buffer object
[12:11:50] [PASSED] Shared buffer object
[12:11:50] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[12:11:50] ============== ttm_bo_init_reserved_mock_man ==============
[12:11:50] [PASSED] Buffer object for userspace
[12:11:50] [PASSED] Kernel buffer object
[12:11:50] [PASSED] Shared buffer object
[12:11:50] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[12:11:50] [PASSED] ttm_bo_init_reserved_resv
[12:11:50] ================== ttm_bo_validate_basic ==================
[12:11:50] [PASSED] Buffer object for userspace
[12:11:50] [PASSED] Kernel buffer object
[12:11:50] [PASSED] Shared buffer object
[12:11:50] ============== [PASSED] ttm_bo_validate_basic ==============
[12:11:50] [PASSED] ttm_bo_validate_invalid_placement
[12:11:50] ============= ttm_bo_validate_same_placement ==============
[12:11:50] [PASSED] System manager
[12:11:50] [PASSED] VRAM manager
[12:11:50] ========= [PASSED] ttm_bo_validate_same_placement ==========
[12:11:50] [PASSED] ttm_bo_validate_failed_alloc
[12:11:50] [PASSED] ttm_bo_validate_pinned
[12:11:50] [PASSED] ttm_bo_validate_busy_placement
[12:11:50] ================ ttm_bo_validate_multihop =================
[12:11:50] [PASSED] Buffer object for userspace
[12:11:50] [PASSED] Kernel buffer object
[12:11:50] [PASSED] Shared buffer object
[12:11:50] ============ [PASSED] ttm_bo_validate_multihop =============
[12:11:50] ========== ttm_bo_validate_no_placement_signaled ==========
[12:11:50] [PASSED] Buffer object in system domain, no page vector
[12:11:50] [PASSED] Buffer object in system domain with an existing page vector
[12:11:50] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[12:11:50] ======== ttm_bo_validate_no_placement_not_signaled ========
[12:11:50] [PASSED] Buffer object for userspace
[12:11:50] [PASSED] Kernel buffer object
[12:11:50] [PASSED] Shared buffer object
[12:11:50] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[12:11:50] [PASSED] ttm_bo_validate_move_fence_signaled
[12:11:50] ========= ttm_bo_validate_move_fence_not_signaled =========
[12:11:50] [PASSED] Waits for GPU
[12:11:50] [PASSED] Tries to lock straight away
[12:11:50] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[12:11:50] [PASSED] ttm_bo_validate_swapout
[12:11:50] [PASSED] ttm_bo_validate_happy_evict
[12:11:50] [PASSED] ttm_bo_validate_all_pinned_evict
[12:11:50] [PASSED] ttm_bo_validate_allowed_only_evict
[12:11:50] [PASSED] ttm_bo_validate_deleted_evict
[12:11:50] [PASSED] ttm_bo_validate_busy_domain_evict
[12:11:50] [PASSED] ttm_bo_validate_evict_gutting
[12:11:50] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[12:11:50] ================= [PASSED] ttm_bo_validate =================
[12:11:50] ============================================================
[12:11:50] Testing complete. Ran 102 tests: passed: 102
[12:11:50] Elapsed time: 11.325s total, 1.645s configuring, 9.464s building, 0.188s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.BAT: success for Introduce Xe Correctable Error Handling (rev5)
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
` (4 preceding siblings ...)
2026-04-07 12:11 ` ✓ CI.KUnit: success " Patchwork
@ 2026-04-07 12:50 ` Patchwork
2026-04-07 14:29 ` ✓ Xe.CI.FULL: " Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-04-07 12:50 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2332 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev5)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25_BAT -> xe-pw-160184v5_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (14 -> 14)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-160184v5_BAT that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1:
- bat-adlp-7: [PASS][1] -> [DMESG-WARN][2] ([Intel XE#7483])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@d-edp1.html
#### Possible fixes ####
* igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1:
- bat-adlp-7: [DMESG-WARN][3] ([Intel XE#7483]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/bat-adlp-7/igt@kms_flip@basic-flip-vs-wf_vblank@c-edp1.html
* igt@xe_waitfence@abstime:
- bat-dg2-oem2: [TIMEOUT][5] ([Intel XE#6506]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/bat-dg2-oem2/igt@xe_waitfence@abstime.html
[Intel XE#6506]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6506
[Intel XE#7483]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7483
Build changes
-------------
* Linux: xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25 -> xe-pw-160184v5
IGT_8850: 8850
xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25: 3acaeaba9868604b32e13fa82f666f27677a9c25
xe-pw-160184v5: 160184v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/index.html
[-- Attachment #2: Type: text/html, Size: 3029 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* ✓ Xe.CI.FULL: success for Introduce Xe Correctable Error Handling (rev5)
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
` (5 preceding siblings ...)
2026-04-07 12:50 ` ✓ Xe.CI.BAT: " Patchwork
@ 2026-04-07 14:29 ` Patchwork
6 siblings, 0 replies; 14+ messages in thread
From: Patchwork @ 2026-04-07 14:29 UTC (permalink / raw)
To: Raag Jadav; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 15868 bytes --]
== Series Details ==
Series: Introduce Xe Correctable Error Handling (rev5)
URL : https://patchwork.freedesktop.org/series/160184/
State : success
== Summary ==
CI Bug Log - changes from xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25_FULL -> xe-pw-160184v5_FULL
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (2 -> 2)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-160184v5_FULL that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@kms_big_fb@4-tiled-32bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][1] ([Intel XE#2327])
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-bmg: NOTRUN -> [SKIP][2] ([Intel XE#1124]) +1 other test skip
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_bw@linear-tiling-2-displays-2560x1440p:
- shard-bmg: NOTRUN -> [SKIP][3] ([Intel XE#367] / [Intel XE#7354])
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_bw@linear-tiling-2-displays-2560x1440p.html
* igt@kms_chamelium_hpd@dp-hpd-after-hibernate:
- shard-bmg: NOTRUN -> [SKIP][4] ([Intel XE#2252])
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_chamelium_hpd@dp-hpd-after-hibernate.html
* igt@kms_cursor_crc@cursor-sliding-256x256:
- shard-bmg: [PASS][5] -> [FAIL][6] ([Intel XE#6747]) +2 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-5/igt@kms_cursor_crc@cursor-sliding-256x256.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-2/igt@kms_cursor_crc@cursor-sliding-256x256.html
* igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size:
- shard-bmg: [PASS][7] -> [DMESG-WARN][8] ([Intel XE#5354])
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-7/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-8/igt@kms_cursor_legacy@cursora-vs-flipb-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-lnl: [PASS][9] -> [FAIL][10] ([Intel XE#301])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2:
- shard-bmg: [PASS][11] -> [FAIL][12] ([Intel XE#7545]) +1 other test fail
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-dp2.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1:
- shard-lnl: [PASS][13] -> [FAIL][14] ([Intel XE#301] / [Intel XE#3149])
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
- shard-bmg: NOTRUN -> [SKIP][15] ([Intel XE#7178] / [Intel XE#7351])
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt:
- shard-bmg: NOTRUN -> [SKIP][16] ([Intel XE#4141]) +2 other tests skip
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff:
- shard-bmg: NOTRUN -> [SKIP][17] ([Intel XE#2311]) +3 other tests skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2313]) +1 other test skip
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_hdr@invalid-hdr:
- shard-bmg: [PASS][19] -> [SKIP][20] ([Intel XE#1503])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-8/igt@kms_hdr@invalid-hdr.html
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-6/igt@kms_hdr@invalid-hdr.html
* igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner:
- shard-bmg: NOTRUN -> [SKIP][21] ([Intel XE#4090] / [Intel XE#7443])
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_joiner@switch-modeset-ultra-joiner-big-joiner.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d:
- shard-bmg: NOTRUN -> [SKIP][22] ([Intel XE#2763] / [Intel XE#6886]) +2 other tests skip
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-75@pipe-d.html
* igt@kms_pm_rpm@modeset-lpsp:
- shard-bmg: NOTRUN -> [SKIP][23] ([Intel XE#1439] / [Intel XE#3141] / [Intel XE#7383] / [Intel XE#836])
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_pm_rpm@modeset-lpsp.html
* igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area:
- shard-bmg: NOTRUN -> [SKIP][24] ([Intel XE#1489]) +1 other test skip
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_psr2_sf@pr-primary-plane-update-sf-dmg-area.html
* igt@kms_psr@psr-sprite-render:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#2234] / [Intel XE#2850]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_psr@psr-sprite-render.html
* igt@kms_vrr@flip-basic:
- shard-bmg: NOTRUN -> [SKIP][26] ([Intel XE#1499])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@kms_vrr@flip-basic.html
* igt@xe_create@multigpu-create-massive-size:
- shard-bmg: NOTRUN -> [SKIP][27] ([Intel XE#2504] / [Intel XE#7319] / [Intel XE#7350])
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_create@multigpu-create-massive-size.html
* igt@xe_eudebug_online@breakpoint-many-sessions-tiles:
- shard-bmg: NOTRUN -> [SKIP][28] ([Intel XE#7636])
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_eudebug_online@breakpoint-many-sessions-tiles.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race:
- shard-bmg: NOTRUN -> [SKIP][29] ([Intel XE#2322] / [Intel XE#7372])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race-imm:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#7136])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_exec_fault_mode@twice-multi-queue-userptr-invalidate-race-imm.html
* igt@xe_exec_multi_queue@virtual:
- shard-bmg: NOTRUN -> [SKIP][31] ([Intel XE#6874])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_exec_multi_queue@virtual.html
* igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma:
- shard-lnl: [PASS][32] -> [FAIL][33] ([Intel XE#5625])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-lnl-1/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-lnl-8/igt@xe_exec_system_allocator@pat-index-madvise-pat-idx-uc-single-vma.html
* igt@xe_exec_threads@threads-multi-queue-fd-basic:
- shard-bmg: NOTRUN -> [SKIP][34] ([Intel XE#7138])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-10/igt@xe_exec_threads@threads-multi-queue-fd-basic.html
#### Possible fixes ####
* igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size:
- shard-bmg: [DMESG-WARN][35] ([Intel XE#5354]) -> [PASS][36]
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-3/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-6/igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions-varying-size.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][37] ([Intel XE#301]) -> [PASS][38]
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-bmg: [INCOMPLETE][39] ([Intel XE#6321]) -> [PASS][40]
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-4/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-5/igt@xe_evict@evict-beng-mixed-many-threads-small.html
#### Warnings ####
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-lnl: [FAIL][41] ([Intel XE#301]) -> [FAIL][42] ([Intel XE#301] / [Intel XE#3149])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-lnl-2/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [FAIL][43] ([Intel XE#1729] / [Intel XE#7424]) -> [SKIP][44] ([Intel XE#2426] / [Intel XE#5848])
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-6/igt@kms_tiled_display@basic-test-pattern.html
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-3/igt@kms_tiled_display@basic-test-pattern.html
* igt@kms_tiled_display@basic-test-pattern-with-chamelium:
- shard-bmg: [SKIP][45] ([Intel XE#2509] / [Intel XE#7437]) -> [SKIP][46] ([Intel XE#2426] / [Intel XE#5848])
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25/shard-bmg-4/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/shard-bmg-5/igt@kms_tiled_display@basic-test-pattern-with-chamelium.html
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1439]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1439
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2504
[Intel XE#2509]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2509
[Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#3141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3141
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#4090]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4090
[Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
[Intel XE#5354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5354
[Intel XE#5625]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5625
[Intel XE#5848]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5848
[Intel XE#6321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6321
[Intel XE#6747]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6747
[Intel XE#6874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6874
[Intel XE#6886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/6886
[Intel XE#7136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7136
[Intel XE#7138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7138
[Intel XE#7178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7178
[Intel XE#7319]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7319
[Intel XE#7350]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7350
[Intel XE#7351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7351
[Intel XE#7354]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7354
[Intel XE#7372]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7372
[Intel XE#7383]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7383
[Intel XE#7424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7424
[Intel XE#7437]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7437
[Intel XE#7443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7443
[Intel XE#7545]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7545
[Intel XE#7636]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/7636
[Intel XE#836]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/836
Build changes
-------------
* Linux: xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25 -> xe-pw-160184v5
IGT_8850: 8850
xe-4856-3acaeaba9868604b32e13fa82f666f27677a9c25: 3acaeaba9868604b32e13fa82f666f27677a9c25
xe-pw-160184v5: 160184v5
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-160184v5/index.html
[-- Attachment #2: Type: text/html, Size: 17627 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling
2026-04-07 11:06 ` [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling Raag Jadav
@ 2026-04-08 12:25 ` Mallesh, Koujalagi
2026-04-09 7:59 ` Raag Jadav
2026-04-09 10:14 ` Tauro, Riana
1 sibling, 1 reply; 14+ messages in thread
From: Mallesh, Koujalagi @ 2026-04-08 12:25 UTC (permalink / raw)
To: Raag Jadav
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, intel-xe
[-- Attachment #1: Type: text/plain, Size: 8506 bytes --]
On 07-04-2026 04:36 pm, Raag Jadav wrote:
> Add initial support for correctable error handling which is serviced
> using system controller event. Currently we only log the errors in
> dmesg but this serves as a foundation for RAS infrastructure and will
> be further extended to facilitate other RAS features.
>
> Signed-off-by: Raag Jadav<raag.jadav@intel.com>
> ---
> v4: Fix Severity/Component logging (Mallesh)
> s/xe_ras_error/xe_ras_error_class (Riana)
> v5: Handle unexpected counter threshold crossed (Mallesh)
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_ras.c | 96 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 14 ++++
> drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> 5 files changed, 186 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index c0e820eeea30..f66561977a45 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> xe_pxp_submit.o \
> xe_query.o \
> xe_range_fence.o \
> + xe_ras.o \
> xe_reg_sr.o \
> xe_reg_whitelist.o \
> xe_ring_ops.o \
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> new file mode 100644
> index 000000000000..6f84ade02057
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> +#include "xe_ras_types.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +
> +/* Severity of detected errors */
> +enum xe_ras_severity {
> + XE_RAS_SEV_NOT_SUPPORTED = 0,
> + XE_RAS_SEV_CORRECTABLE,
> + XE_RAS_SEV_UNCORRECTABLE,
> + XE_RAS_SEV_INFORMATIONAL,
> + XE_RAS_SEV_MAX
> +};
> +
> +/* Major IP blocks/components where errors can originate */
> +enum xe_ras_component {
> + XE_RAS_COMP_NOT_SUPPORTED = 0,
> + XE_RAS_COMP_DEVICE_MEMORY,
> + XE_RAS_COMP_CORE_COMPUTE,
> + XE_RAS_COMP_RESERVED,
> + XE_RAS_COMP_PCIE,
> + XE_RAS_COMP_FABRIC,
> + XE_RAS_COMP_SOC_INTERNAL,
> + XE_RAS_COMP_MAX
> +};
> +
> +static const char *const xe_ras_severities[] = {
> + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> +
> +static const char *const xe_ras_components[] = {
> + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> + [XE_RAS_COMP_RESERVED] = "Reserved",
> + [XE_RAS_COMP_PCIE] = "PCIe",
> + [XE_RAS_COMP_FABRIC] = "Fabric",
> + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> +
> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> +{
Unused xe parameter, remove it
> + if (sev >= XE_RAS_SEV_MAX)
> + sev = XE_RAS_SEV_NOT_SUPPORTED;
> +
> + return xe_ras_severities[sev];
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
ditto
> + if (comp >= XE_RAS_COMP_MAX)
> + comp = XE_RAS_COMP_NOT_SUPPORTED;
> +
> + return xe_ras_components[comp];
> +}
> +
> +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
> +{
> + struct xe_ras_threshold_crossed_data *pending = (void *)&response->data;
> + struct xe_ras_error_class *errors = pending->counters;
> + struct xe_device *xe = sc_to_xe(sc);
> + u32 ncounters = pending->ncounters;
> + u32 cid, sev, comp, inst, cause;
> + u8 tile;
> +
> + if (!ncounters || ncounters >= XE_RAS_NUM_COUNTERS) {
if ncounters are 16, then it's logged in error, however for (cid = 0;
cid < ncounters; cid++)
safely accesses up to ncounters - 1. So check should be
if (!ncounters || ncounters > XE_RAS_NUM_COUNTERS) right?
> + xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters);
Use "[RAS]: ", since code is RAS owned.
Thanks,
-/Mallesh
> + return;
> + }
> +
> + BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending));
> + xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters);
> +
> + for (cid = 0; cid < ncounters; cid++) {
> + sev = errors[cid].common.severity;
> + comp = errors[cid].common.component;
> +
> + tile = errors[cid].product.unit.tile;
> + inst = errors[cid].product.unit.instance;
> + cause = errors[cid].product.cause.cause;
> +
> + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> + tile, inst, comp_to_str(xe, comp), sev_to_str(xe, sev), cause);
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> new file mode 100644
> index 000000000000..92ee93d4e877
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_H_
> +#define _XE_RAS_H_
> +
> +struct xe_sysctrl;
> +struct xe_sysctrl_event_response;
> +
> +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..0e3ba9e81538
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_COUNTERS 16
> +
> +/**
> + * struct xe_ras_error_common - Error fields that are common across all products
> + */
> +struct xe_ras_error_common {
> + /** @severity: Error severity */
> + u8 severity;
> + /** @component: IP block where error originated */
> + u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> + /** @tile: Tile identifier */
> + u8 tile;
> + /** @instance: Instance identifier specific to IP */
> + u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> + /** @cause: Cause/checker */
> + u32 cause;
> + /** @reserved: For future use */
> + u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> + /** @unit: Unit within IP block */
> + struct xe_ras_error_unit unit;
> + /** @cause: Cause/checker */
> + struct xe_ras_error_cause cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_class - Combines common and product-specific parts
> + */
> +struct xe_ras_error_class {
> + /** @common: Common error type and component */
> + struct xe_ras_error_common common;
> + /** @product: Product-specific unit and cause */
> + struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_threshold_crossed_data - Data for threshold crossed event
> + */
> +struct xe_ras_threshold_crossed_data {
> + /** @ncounters: Number of error counters that crossed thresholds */
> + u32 ncounters;
> + /** @counters: Array of error counters that crossed threshold */
> + struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> index 8a2e44f4f5e0..139ecd4aafcd 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -6,6 +6,7 @@
> #include "xe_device.h"
> #include "xe_irq.h"
> #include "xe_printk.h"
> +#include "xe_ras.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_event_types.h"
> #include "xe_sysctrl_mailbox.h" @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct
> xe_sysctrl *sc, } if (response.event ==
> XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) { - xe_warn(xe, "[RAS]: counter threshold crossed\n");
> + xe_ras_threshold_crossed(sc, &response);
> } else {
> xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> return;
[-- Attachment #2: Type: text/html, Size: 9711 bytes --]
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler
2026-04-07 11:06 ` [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
@ 2026-04-09 5:04 ` Tauro, Riana
2026-04-09 6:47 ` Raag Jadav
0 siblings, 1 reply; 14+ messages in thread
From: Tauro, Riana @ 2026-04-09 5:04 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: matthew.brost, rodrigo.vivi, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, mallesh.koujalagi, soham.purkait,
anoop.c.vijay, aravind.iddamsetty
On 4/7/2026 4:36 PM, Raag Jadav wrote:
> Add system controller interrupt handler which is denoted by 11th bit in
> GFX master interrupt register. While at it, add worker for scheduling
> system controller work.
>
> Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
> v4: Handle IRQ before sysctrl initialization (Mallesh)
> ---
> drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> drivers/gpu/drm/xe/xe_irq.c | 2 ++
> drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> 5 files changed, 44 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> index 9d74f454d3ff..1d6b976c4de0 100644
> --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> @@ -22,6 +22,7 @@
> #define DISPLAY_IRQ REG_BIT(16)
> #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> #define I2C_IRQ REG_BIT(12)
> +#define SYSCTRL_IRQ REG_BIT(11)
> #define GT_DW_IRQ(x) REG_BIT(x)
>
> /*
> diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> index 9a775c6588dc..e9f0b3cad06d 100644
> --- a/drivers/gpu/drm/xe/xe_irq.c
> +++ b/drivers/gpu/drm/xe/xe_irq.c
> @@ -24,6 +24,7 @@
> #include "xe_mmio.h"
> #include "xe_pxp.h"
> #include "xe_sriov.h"
> +#include "xe_sysctrl.h"
> #include "xe_tile.h"
>
> /*
> @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> xe_heci_csc_irq_handler(xe, master_ctl);
> xe_display_irq_handler(xe, master_ctl);
> xe_i2c_irq_handler(xe, master_ctl);
> + xe_sysctrl_irq_handler(xe, master_ctl);
> xe_mert_irq_handler(xe, master_ctl);
> gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> }
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index 2bcef304eb9a..afa9654668a2 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -8,6 +8,7 @@
>
> #include <drm/drm_managed.h>
>
> +#include "regs/xe_irq_regs.h"
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_device.h"
> #include "xe_mmio.h"
> @@ -30,10 +31,16 @@
> static void sysctrl_fini(void *arg)
> {
> struct xe_device *xe = arg;
> + struct xe_sysctrl *sc = &xe->sc;
>
> + cancel_work_sync(&sc->work);
> xe->soc_remapper.set_sysctrl_region(xe, 0);
> }
>
> +static void xe_sysctrl_work(struct work_struct *work)
> +{
> +}
> +
> /**
> * xe_sysctrl_init() - Initialize System Controller subsystem
> * @xe: xe device instance
> @@ -55,11 +62,7 @@ int xe_sysctrl_init(struct xe_device *xe)
> if (!xe->info.has_sysctrl)
> return 0;
>
> - xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> -
> - ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> - if (ret)
> - return ret;
> + xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
>
> sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> if (!sc->mmio)
> @@ -73,9 +76,33 @@ int xe_sysctrl_init(struct xe_device *xe)
> if (ret)
> return ret;
>
> + ret = devm_mutex_init(xe->drm.dev, &sc->work_lock);
Nit: Mutex can be added in the same patch where it is used.
Reviewed-by: Riana Tauro <riana.tauro@intel.com>
> + if (ret)
> + return ret;
> +
> + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> xe_sysctrl_mailbox_init(sc);
> + INIT_WORK(&sc->work, xe_sysctrl_work);
>
> - return 0;
> + return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> +}
> +
> +/**
> + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> + * @xe: xe device instance
> + * @master_ctl: interrupt register
> + *
> + * Handle interrupts generated by System Controller.
> + */
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> +{
> + struct xe_sysctrl *sc = &xe->sc;
> +
> + if (!xe->info.has_sysctrl || !sc->work.func)
> + return;
> +
> + if (master_ctl & SYSCTRL_IRQ)
> + schedule_work(&sc->work);
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index f3b0f3716b2f..f7469bfc9324 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -17,6 +17,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> }
>
> int xe_sysctrl_init(struct xe_device *xe);
> +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> void xe_sysctrl_pm_resume(struct xe_device *xe);
>
> #endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> index 8217f6befe70..13fbf2990280 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> @@ -8,6 +8,7 @@
>
> #include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/workqueue_types.h>
>
> struct xe_mmio;
>
> @@ -27,6 +28,12 @@ struct xe_sysctrl {
>
> /** @phase_bit: Message boundary phase toggle bit (0 or 1) */
> bool phase_bit;
> +
> + /** @work: Pending events work */
> + struct work_struct work;
> +
> + /** @work_lock: Mutex protecting pending events */
> + struct mutex work_lock;
> };
>
> #endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler
2026-04-09 5:04 ` Tauro, Riana
@ 2026-04-09 6:47 ` Raag Jadav
0 siblings, 0 replies; 14+ messages in thread
From: Raag Jadav @ 2026-04-09 6:47 UTC (permalink / raw)
To: Tauro, Riana
Cc: intel-xe, matthew.brost, rodrigo.vivi, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, mallesh.koujalagi,
soham.purkait, anoop.c.vijay, aravind.iddamsetty
On Thu, Apr 09, 2026 at 10:34:09AM +0530, Tauro, Riana wrote:
> On 4/7/2026 4:36 PM, Raag Jadav wrote:
> > Add system controller interrupt handler which is denoted by 11th bit in
> > GFX master interrupt register. While at it, add worker for scheduling
> > system controller work.
> >
> > Co-developed-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Soham Purkait <soham.purkait@intel.com>
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> > ---
> > v2: Use system_percpu_wq instead of dedicated (Matthew Brost)
> > v4: Handle IRQ before sysctrl initialization (Mallesh)
> > ---
> > drivers/gpu/drm/xe/regs/xe_irq_regs.h | 1 +
> > drivers/gpu/drm/xe/xe_irq.c | 2 ++
> > drivers/gpu/drm/xe/xe_sysctrl.c | 39 ++++++++++++++++++++++-----
> > drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> > drivers/gpu/drm/xe/xe_sysctrl_types.h | 7 +++++
> > 5 files changed, 44 insertions(+), 6 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/xe/regs/xe_irq_regs.h b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > index 9d74f454d3ff..1d6b976c4de0 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_irq_regs.h
> > @@ -22,6 +22,7 @@
> > #define DISPLAY_IRQ REG_BIT(16)
> > #define SOC_H2DMEMINT_IRQ REG_BIT(13)
> > #define I2C_IRQ REG_BIT(12)
> > +#define SYSCTRL_IRQ REG_BIT(11)
> > #define GT_DW_IRQ(x) REG_BIT(x)
> > /*
> > diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
> > index 9a775c6588dc..e9f0b3cad06d 100644
> > --- a/drivers/gpu/drm/xe/xe_irq.c
> > +++ b/drivers/gpu/drm/xe/xe_irq.c
> > @@ -24,6 +24,7 @@
> > #include "xe_mmio.h"
> > #include "xe_pxp.h"
> > #include "xe_sriov.h"
> > +#include "xe_sysctrl.h"
> > #include "xe_tile.h"
> > /*
> > @@ -525,6 +526,7 @@ static irqreturn_t dg1_irq_handler(int irq, void *arg)
> > xe_heci_csc_irq_handler(xe, master_ctl);
> > xe_display_irq_handler(xe, master_ctl);
> > xe_i2c_irq_handler(xe, master_ctl);
> > + xe_sysctrl_irq_handler(xe, master_ctl);
> > xe_mert_irq_handler(xe, master_ctl);
> > gu_misc_iir = gu_misc_irq_ack(xe, master_ctl);
> > }
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> > index 2bcef304eb9a..afa9654668a2 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> > @@ -8,6 +8,7 @@
> > #include <drm/drm_managed.h>
> > +#include "regs/xe_irq_regs.h"
> > #include "regs/xe_sysctrl_regs.h"
> > #include "xe_device.h"
> > #include "xe_mmio.h"
> > @@ -30,10 +31,16 @@
> > static void sysctrl_fini(void *arg)
> > {
> > struct xe_device *xe = arg;
> > + struct xe_sysctrl *sc = &xe->sc;
> > + cancel_work_sync(&sc->work);
> > xe->soc_remapper.set_sysctrl_region(xe, 0);
> > }
> > +static void xe_sysctrl_work(struct work_struct *work)
> > +{
> > +}
> > +
> > /**
> > * xe_sysctrl_init() - Initialize System Controller subsystem
> > * @xe: xe device instance
> > @@ -55,11 +62,7 @@ int xe_sysctrl_init(struct xe_device *xe)
> > if (!xe->info.has_sysctrl)
> > return 0;
> > - xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > -
> > - ret = devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> > - if (ret)
> > - return ret;
> > + xe_assert(xe, xe->soc_remapper.set_sysctrl_region);
> > sc->mmio = devm_kzalloc(xe->drm.dev, sizeof(*sc->mmio), GFP_KERNEL);
> > if (!sc->mmio)
> > @@ -73,9 +76,33 @@ int xe_sysctrl_init(struct xe_device *xe)
> > if (ret)
> > return ret;
> > + ret = devm_mutex_init(xe->drm.dev, &sc->work_lock);
> Nit: Mutex can be added in the same patch where it is used.
Just trying to avoid random churns.
> Reviewed-by: Riana Tauro <riana.tauro@intel.com>
Thank you.
Raag
> > + if (ret)
> > + return ret;
> > +
> > + xe->soc_remapper.set_sysctrl_region(xe, SYSCTRL_MAILBOX_INDEX);
> > xe_sysctrl_mailbox_init(sc);
> > + INIT_WORK(&sc->work, xe_sysctrl_work);
> > - return 0;
> > + return devm_add_action_or_reset(xe->drm.dev, sysctrl_fini, xe);
> > +}
> > +
> > +/**
> > + * xe_sysctrl_irq_handler() - Handler for System Controller interrupts
> > + * @xe: xe device instance
> > + * @master_ctl: interrupt register
> > + *
> > + * Handle interrupts generated by System Controller.
> > + */
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl)
> > +{
> > + struct xe_sysctrl *sc = &xe->sc;
> > +
> > + if (!xe->info.has_sysctrl || !sc->work.func)
> > + return;
> > +
> > + if (master_ctl & SYSCTRL_IRQ)
> > + schedule_work(&sc->work);
> > }
> > /**
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> > index f3b0f3716b2f..f7469bfc9324 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> > @@ -17,6 +17,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> > }
> > int xe_sysctrl_init(struct xe_device *xe);
> > +void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> > void xe_sysctrl_pm_resume(struct xe_device *xe);
> > #endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_types.h b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > index 8217f6befe70..13fbf2990280 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_types.h
> > @@ -8,6 +8,7 @@
> > #include <linux/mutex.h>
> > #include <linux/types.h>
> > +#include <linux/workqueue_types.h>
> > struct xe_mmio;
> > @@ -27,6 +28,12 @@ struct xe_sysctrl {
> > /** @phase_bit: Message boundary phase toggle bit (0 or 1) */
> > bool phase_bit;
> > +
> > + /** @work: Pending events work */
> > + struct work_struct work;
> > +
> > + /** @work_lock: Mutex protecting pending events */
> > + struct mutex work_lock;
> > };
> > #endif
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling
2026-04-08 12:25 ` Mallesh, Koujalagi
@ 2026-04-09 7:59 ` Raag Jadav
0 siblings, 0 replies; 14+ messages in thread
From: Raag Jadav @ 2026-04-09 7:59 UTC (permalink / raw)
To: Mallesh, Koujalagi
Cc: matthew.brost, rodrigo.vivi, riana.tauro, michal.wajdeczko,
matthew.d.roper, umesh.nerlige.ramappa, soham.purkait,
anoop.c.vijay, aravind.iddamsetty, intel-xe
On Wed, Apr 08, 2026 at 05:55:17PM +0530, Mallesh, Koujalagi wrote:
> On 07-04-2026 04:36 pm, Raag Jadav wrote:
> > Add initial support for correctable error handling which is serviced
> > using system controller event. Currently we only log the errors in
> > dmesg but this serves as a foundation for RAS infrastructure and will
> > be further extended to facilitate other RAS features.
> >
> > Signed-off-by: Raag Jadav<raag.jadav@intel.com>
> > ---
> > v4: Fix Severity/Component logging (Mallesh)
> > s/xe_ras_error/xe_ras_error_class (Riana)
> > v5: Handle unexpected counter threshold crossed (Mallesh)
> > ---
> > drivers/gpu/drm/xe/Makefile | 1 +
> > drivers/gpu/drm/xe/xe_ras.c | 96 +++++++++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_ras.h | 14 ++++
> > drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++
> > drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> > 5 files changed, 186 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> > create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> > create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
> >
> > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> > index c0e820eeea30..f66561977a45 100644
> > --- a/drivers/gpu/drm/xe/Makefile
> > +++ b/drivers/gpu/drm/xe/Makefile
> > @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> > xe_pxp_submit.o \
> > xe_query.o \
> > xe_range_fence.o \
> > + xe_ras.o \
> > xe_reg_sr.o \
> > xe_reg_whitelist.o \
> > xe_ring_ops.o \
> > diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> > new file mode 100644
> > index 000000000000..6f84ade02057
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.c
> > @@ -0,0 +1,96 @@
> > +// SPDX-License-Identifier: MIT
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#include "xe_printk.h"
> > +#include "xe_ras.h"
> > +#include "xe_ras_types.h"
> > +#include "xe_sysctrl.h"
> > +#include "xe_sysctrl_event_types.h"
> > +
> > +/* Severity of detected errors */
> > +enum xe_ras_severity {
> > + XE_RAS_SEV_NOT_SUPPORTED = 0,
> > + XE_RAS_SEV_CORRECTABLE,
> > + XE_RAS_SEV_UNCORRECTABLE,
> > + XE_RAS_SEV_INFORMATIONAL,
> > + XE_RAS_SEV_MAX
> > +};
> > +
> > +/* Major IP blocks/components where errors can originate */
> > +enum xe_ras_component {
> > + XE_RAS_COMP_NOT_SUPPORTED = 0,
> > + XE_RAS_COMP_DEVICE_MEMORY,
> > + XE_RAS_COMP_CORE_COMPUTE,
> > + XE_RAS_COMP_RESERVED,
> > + XE_RAS_COMP_PCIE,
> > + XE_RAS_COMP_FABRIC,
> > + XE_RAS_COMP_SOC_INTERNAL,
> > + XE_RAS_COMP_MAX
> > +};
> > +
> > +static const char *const xe_ras_severities[] = {
> > + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> > + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> > + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> > +
> > +static const char *const xe_ras_components[] = {
> > + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> > + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> > + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> > + [XE_RAS_COMP_RESERVED] = "Reserved",
> > + [XE_RAS_COMP_PCIE] = "PCIe",
> > + [XE_RAS_COMP_FABRIC] = "Fabric",
> > + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> > +};
> > +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> > +
> > +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> > +{
> Unused xe parameter, remove it
Sure.
> > + if (sev >= XE_RAS_SEV_MAX)
> > + sev = XE_RAS_SEV_NOT_SUPPORTED;
> > +
> > + return xe_ras_severities[sev];
> > +}
> > +
> > +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> > +{
> ditto
> > + if (comp >= XE_RAS_COMP_MAX)
> > + comp = XE_RAS_COMP_NOT_SUPPORTED;
> > +
> > + return xe_ras_components[comp];
> > +}
> > +
> > +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
> > +{
> > + struct xe_ras_threshold_crossed_data *pending = (void *)&response->data;
> > + struct xe_ras_error_class *errors = pending->counters;
> > + struct xe_device *xe = sc_to_xe(sc);
> > + u32 ncounters = pending->ncounters;
> > + u32 cid, sev, comp, inst, cause;
> > + u8 tile;
> > +
> > + if (!ncounters || ncounters >= XE_RAS_NUM_COUNTERS) {
>
> if ncounters are 16, then it's logged in error, however for (cid = 0; cid <
> ncounters; cid++)
>
> safely accesses up to ncounters - 1. So check should be
>
> if (!ncounters || ncounters > XE_RAS_NUM_COUNTERS) right?
Good catch.
> > + xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters);
>
> Use "[RAS]: ", since code is RAS owned.
Agree, but this'll be misleading because it gives the impression of RAS
error, which it is not.
Raag
> > + return;
> > + }
> > +
> > + BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending));
> > + xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters);
> > +
> > + for (cid = 0; cid < ncounters; cid++) {
> > + sev = errors[cid].common.severity;
> > + comp = errors[cid].common.component;
> > +
> > + tile = errors[cid].product.unit.tile;
> > + inst = errors[cid].product.unit.instance;
> > + cause = errors[cid].product.cause.cause;
> > +
> > + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> > + tile, inst, comp_to_str(xe, comp), sev_to_str(xe, sev), cause);
> > + }
> > +}
> > diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> > new file mode 100644
> > index 000000000000..92ee93d4e877
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras.h
> > @@ -0,0 +1,14 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_H_
> > +#define _XE_RAS_H_
> > +
> > +struct xe_sysctrl;
> > +struct xe_sysctrl_event_response;
> > +
> > +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> > new file mode 100644
> > index 000000000000..0e3ba9e81538
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> > @@ -0,0 +1,73 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2026 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_RAS_TYPES_H_
> > +#define _XE_RAS_TYPES_H_
> > +
> > +#include <linux/types.h>
> > +
> > +#define XE_RAS_NUM_COUNTERS 16
> > +
> > +/**
> > + * struct xe_ras_error_common - Error fields that are common across all products
> > + */
> > +struct xe_ras_error_common {
> > + /** @severity: Error severity */
> > + u8 severity;
> > + /** @component: IP block where error originated */
> > + u8 component;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_unit - Error unit information
> > + */
> > +struct xe_ras_error_unit {
> > + /** @tile: Tile identifier */
> > + u8 tile;
> > + /** @instance: Instance identifier specific to IP */
> > + u32 instance;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_cause - Error cause information
> > + */
> > +struct xe_ras_error_cause {
> > + /** @cause: Cause/checker */
> > + u32 cause;
> > + /** @reserved: For future use */
> > + u8 reserved;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_product - Error fields that are specific to the product
> > + */
> > +struct xe_ras_error_product {
> > + /** @unit: Unit within IP block */
> > + struct xe_ras_error_unit unit;
> > + /** @cause: Cause/checker */
> > + struct xe_ras_error_cause cause;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_error_class - Combines common and product-specific parts
> > + */
> > +struct xe_ras_error_class {
> > + /** @common: Common error type and component */
> > + struct xe_ras_error_common common;
> > + /** @product: Product-specific unit and cause */
> > + struct xe_ras_error_product product;
> > +} __packed;
> > +
> > +/**
> > + * struct xe_ras_threshold_crossed_data - Data for threshold crossed event
> > + */
> > +struct xe_ras_threshold_crossed_data {
> > + /** @ncounters: Number of error counters that crossed thresholds */
> > + u32 ncounters;
> > + /** @counters: Array of error counters that crossed threshold */
> > + struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> > +} __packed;
> > +
> > +#endif
> > diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > index 8a2e44f4f5e0..139ecd4aafcd 100644
> > --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> > @@ -6,6 +6,7 @@
> > #include "xe_device.h"
> > #include "xe_irq.h"
> > #include "xe_printk.h"
> > +#include "xe_ras.h"
> > #include "xe_sysctrl.h"
> > #include "xe_sysctrl_event_types.h"
> > #include "xe_sysctrl_mailbox.h" @@ -38,7 +39,7 @@ static void
> > xe_sysctrl_get_pending_event(struct xe_sysctrl *sc, } if (response.event
> > == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) { - xe_warn(xe, "[RAS]: counter
> > threshold crossed\n");
> > + xe_ras_threshold_crossed(sc, &response);
> > } else {
> > xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> > return;
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support
2026-04-07 11:06 ` [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support Raag Jadav
@ 2026-04-09 9:57 ` Tauro, Riana
0 siblings, 0 replies; 14+ messages in thread
From: Tauro, Riana @ 2026-04-09 9:57 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: matthew.brost, rodrigo.vivi, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, mallesh.koujalagi, soham.purkait,
anoop.c.vijay, aravind.iddamsetty
On 4/7/2026 4:36 PM, Raag Jadav wrote:
> System controller reports different types of events to GFX endpoint for
> different usecases, add initial support for them. This will be further
> extended to service those usecases.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> Reviewed-by: Mallesh Koujalagi <mallesh.koujalagi@intel.com>
> ---
> v2: Handle unexpected response length (Mallesh)
> v3: Handle event flood (Mallesh)
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_sysctrl.c | 7 ++
> drivers/gpu/drm/xe/xe_sysctrl.h | 1 +
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 88 +++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event_types.h | 52 ++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_mailbox.h | 10 +++
> 6 files changed, 159 insertions(+)
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event.c
> create mode 100644 drivers/gpu/drm/xe/xe_sysctrl_event_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index ab1e0b3b332d..c0e820eeea30 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -125,6 +125,7 @@ xe-y += xe_bb.o \
> xe_survivability_mode.o \
> xe_sync.o \
> xe_sysctrl.o \
> + xe_sysctrl_event.o \
> xe_sysctrl_mailbox.o \
> xe_tile.o \
> xe_tile_sysfs.o \
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.c b/drivers/gpu/drm/xe/xe_sysctrl.c
> index afa9654668a2..7003b1da6e46 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.c
> @@ -12,6 +12,7 @@
> #include "regs/xe_sysctrl_regs.h"
> #include "xe_device.h"
> #include "xe_mmio.h"
> +#include "xe_pm.h"
> #include "xe_soc_remapper.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_mailbox.h"
> @@ -39,6 +40,12 @@ static void sysctrl_fini(void *arg)
>
> static void xe_sysctrl_work(struct work_struct *work)
> {
> + struct xe_sysctrl *sc = container_of(work, struct xe_sysctrl, work);
> + struct xe_device *xe = sc_to_xe(sc);
> +
> + guard(xe_pm_runtime)(xe);
> + guard(mutex)(&sc->work_lock);
> + xe_sysctrl_event(sc);
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl.h b/drivers/gpu/drm/xe/xe_sysctrl.h
> index f7469bfc9324..090dffb6d55f 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl.h
> @@ -16,6 +16,7 @@ static inline struct xe_device *sc_to_xe(struct xe_sysctrl *sc)
> return container_of(sc, struct xe_device, sc);
> }
>
> +void xe_sysctrl_event(struct xe_sysctrl *sc);
> int xe_sysctrl_init(struct xe_device *xe);
> void xe_sysctrl_irq_handler(struct xe_device *xe, u32 master_ctl);
> void xe_sysctrl_pm_resume(struct xe_device *xe);
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> new file mode 100644
> index 000000000000..8a2e44f4f5e0
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -0,0 +1,88 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_device.h"
> +#include "xe_irq.h"
> +#include "xe_printk.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +#include "xe_sysctrl_mailbox.h"
> +#include "xe_sysctrl_mailbox_types.h"
> +
> +static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> + struct xe_sysctrl_mailbox_command *command)
static functions don't need a xe prefix
> +{
> + struct xe_sysctrl_event_response response;
> + struct xe_device *xe = sc_to_xe(sc);
> + u32 count = 0;
> + size_t len;
> + int ret;
> +
> + command->data_out = &response;
> + command->data_out_len = sizeof(response);
Can be part of prepare command
> +
> + do {
> + memset(&response, 0, sizeof(response));
> +
> + ret = xe_sysctrl_send_command(sc, command, &len);
> + if (ret) {
> + xe_err(xe, "sysctrl: failed to get pending event %d\n", ret);
> + return;
> + }
> +
> + if (len != sizeof(response)) {
> + xe_err(xe, "sysctrl: unexpected pending event response length %zu\n", len);
> + return;
> + }
> +
> + if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> + xe_warn(xe, "[RAS]: counter threshold crossed\n");
> + } else {
> + xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> + return;
Should we return here if the event is not threshold_crossed.
The events left might still be valid.
If more event types are added, this might be an issue. Can't we just log
the unknown event and go ahead?
> + }
> +
> + if (++count > XE_SYSCTRL_EVENT_FLOOD) {
Can't the first response count be used as a reference for comparison?
Looks like the response count keeps decrementing for each command sent.
Also add a comment for the response.count behavior in the structure
> + xe_err(xe, "sysctrl: event flooding\n");
> + return;
> + }
> +
> + xe_dbg(xe, "sysctrl: %u events pending\n", response.count);
> + } while (response.count);
> +}
> +
> +static void xe_sysctrl_event_request_prep(struct xe_device *xe,
> + struct xe_sysctrl_app_msg_hdr *header,
> + struct xe_sysctrl_event_request *request)
static functions don't need a xe_ prefix
> +{
> + struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
> +
> + header->data = REG_FIELD_PREP(APP_HDR_GROUP_ID_MASK, XE_SYSCTRL_GROUP_GFSP) |
> + REG_FIELD_PREP(APP_HDR_COMMAND_MASK, XE_SYSCTRL_CMD_GET_PENDING_EVENT);
> +
> + request->vector = xe_device_has_msix(xe) ? XE_IRQ_DEFAULT_MSIX : 0;
> + request->fn = PCI_FUNC(pdev->devfn);
> +}
> +
> +/**
> + * xe_sysctrl_event() - Handler for System Controller events
> + * @sc: System Controller instance
> + *
> + * Handle events generated by System Controller.
> + */
> +void xe_sysctrl_event(struct xe_sysctrl *sc)
> +{
> + struct xe_sysctrl_mailbox_command command = {};
> + struct xe_sysctrl_event_request request = {};
> + struct xe_sysctrl_app_msg_hdr header = {};
> +
> + xe_sysctrl_event_request_prep(sc_to_xe(sc), &header, &request);
> +
> + command.header = header;
> + command.data_in = &request;
> + command.data_in_len = sizeof(request);
> +
> + xe_sysctrl_get_pending_event(sc, &command);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event_types.h b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> new file mode 100644
> index 000000000000..9a26ad758a0b
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event_types.h
> @@ -0,0 +1,52 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_SYSCTRL_EVENT_TYPES_H_
> +#define _XE_SYSCTRL_EVENT_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_SYSCTRL_EVENT_DATA_LEN 59
> +
> +/* Modify as needed */
> +#define XE_SYSCTRL_EVENT_FLOOD 16
> +
> +enum xe_sysctrl_event {
> + XE_SYSCTRL_EVENT_THRESHOLD_CROSSED = 1,
Nit: 0x01
Add a one line comment
> +};
> +
> +/**
> + * struct xe_sysctrl_event_request - Request structure for pending event
> + */
> +struct xe_sysctrl_event_request {
> + /** @vector: MSI-X vector that was triggered */
> + u32 vector;
> + /** @fn: Function index (0-7) of PCIe device */
> + u32 fn:8;
> + /** @reserved: Reserved for future use */
> + u32 reserved:24;
> + /** @reserved2: Reserved for future use */
> + u32 reserved2[2];
> +} __packed;
> +
> +/**
> + * struct xe_sysctrl_event_response - Response structure for pending event
> + */
> +struct xe_sysctrl_event_response {
> + /** @count: Number of pending events */
> + u32 count;
> + /** @event: Pending event */
> + enum xe_sysctrl_event event;
> + /** @timestamp: Timestamp of most recent event */
> + u64 timestamp;
> + /** @extended: Event has extended payload */
> + u32 extended:1;
> + /** @reserved: Reserved for future use */
> + u32 reserved:31;
> + /** @data: Generic event data */
> + u32 data[XE_SYSCTRL_EVENT_DATA_LEN];
> +} __packed;
> +
> +#endif /* _XE_SYSCTRL_EVENT_TYPES_H_ */
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> index 91460be9e22c..d59a825597d3 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_mailbox.h
> @@ -23,6 +23,16 @@ struct xe_sysctrl_mailbox_command;
> #define XE_SYSCTRL_APP_HDR_VERSION(hdr) \
> FIELD_GET(APP_HDR_VERSION_MASK, le32_to_cpu((hdr)->data))
>
> +/* Command groups */
> +enum xe_sysctrl_group {
> + XE_SYSCTRL_GROUP_GFSP = 0x01,
> +};
> +
> +/* Commands supported by GFSP group */
> +enum xe_sysctrl_gfsp_cmd {
> + XE_SYSCTRL_CMD_GET_PENDING_EVENT = 0x07,
> +};
Move the enums to types.h along with structures.
Also had a one-line documentation for each
Thanks
Riana
> +
> void xe_sysctrl_mailbox_init(struct xe_sysctrl *sc);
> int xe_sysctrl_send_command(struct xe_sysctrl *sc,
> struct xe_sysctrl_mailbox_command *cmd,
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling
2026-04-07 11:06 ` [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling Raag Jadav
2026-04-08 12:25 ` Mallesh, Koujalagi
@ 2026-04-09 10:14 ` Tauro, Riana
1 sibling, 0 replies; 14+ messages in thread
From: Tauro, Riana @ 2026-04-09 10:14 UTC (permalink / raw)
To: Raag Jadav, intel-xe
Cc: matthew.brost, rodrigo.vivi, michal.wajdeczko, matthew.d.roper,
umesh.nerlige.ramappa, mallesh.koujalagi, soham.purkait,
anoop.c.vijay, aravind.iddamsetty
On 4/7/2026 4:36 PM, Raag Jadav wrote:
> Add initial support for correctable error handling which is serviced
> using system controller event. Currently we only log the errors in
> dmesg but this serves as a foundation for RAS infrastructure and will
> be further extended to facilitate other RAS features.
>
> Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> ---
> v4: Fix Severity/Component logging (Mallesh)
> s/xe_ras_error/xe_ras_error_class (Riana)
> v5: Handle unexpected counter threshold crossed (Mallesh)
> ---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/xe_ras.c | 96 +++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_ras.h | 14 ++++
> drivers/gpu/drm/xe/xe_ras_types.h | 73 ++++++++++++++++++++
> drivers/gpu/drm/xe/xe_sysctrl_event.c | 3 +-
> 5 files changed, 186 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/xe/xe_ras.c
> create mode 100644 drivers/gpu/drm/xe/xe_ras.h
> create mode 100644 drivers/gpu/drm/xe/xe_ras_types.h
>
> diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
> index c0e820eeea30..f66561977a45 100644
> --- a/drivers/gpu/drm/xe/Makefile
> +++ b/drivers/gpu/drm/xe/Makefile
> @@ -113,6 +113,7 @@ xe-y += xe_bb.o \
> xe_pxp_submit.o \
> xe_query.o \
> xe_range_fence.o \
> + xe_ras.o \
> xe_reg_sr.o \
> xe_reg_whitelist.o \
> xe_ring_ops.o \
> diff --git a/drivers/gpu/drm/xe/xe_ras.c b/drivers/gpu/drm/xe/xe_ras.c
> new file mode 100644
> index 000000000000..6f84ade02057
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.c
> @@ -0,0 +1,96 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#include "xe_printk.h"
> +#include "xe_ras.h"
> +#include "xe_ras_types.h"
> +#include "xe_sysctrl.h"
> +#include "xe_sysctrl_event_types.h"
> +
> +/* Severity of detected errors */
> +enum xe_ras_severity {
> + XE_RAS_SEV_NOT_SUPPORTED = 0,
> + XE_RAS_SEV_CORRECTABLE,
> + XE_RAS_SEV_UNCORRECTABLE,
> + XE_RAS_SEV_INFORMATIONAL,
> + XE_RAS_SEV_MAX
> +};
> +
> +/* Major IP blocks/components where errors can originate */
> +enum xe_ras_component {
> + XE_RAS_COMP_NOT_SUPPORTED = 0,
> + XE_RAS_COMP_DEVICE_MEMORY,
> + XE_RAS_COMP_CORE_COMPUTE,
> + XE_RAS_COMP_RESERVED,
> + XE_RAS_COMP_PCIE,
> + XE_RAS_COMP_FABRIC,
> + XE_RAS_COMP_SOC_INTERNAL,
> + XE_RAS_COMP_MAX
> +};
> +
> +static const char *const xe_ras_severities[] = {
> + [XE_RAS_SEV_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_SEV_CORRECTABLE] = "Correctable",
> + [XE_RAS_SEV_UNCORRECTABLE] = "Uncorrectable",
> + [XE_RAS_SEV_INFORMATIONAL] = "Informational",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_severities) == XE_RAS_SEV_MAX);
> +
> +static const char *const xe_ras_components[] = {
> + [XE_RAS_COMP_NOT_SUPPORTED] = "Not Supported",
> + [XE_RAS_COMP_DEVICE_MEMORY] = "Device Memory",
> + [XE_RAS_COMP_CORE_COMPUTE] = "Core Compute",
> + [XE_RAS_COMP_RESERVED] = "Reserved",
> + [XE_RAS_COMP_PCIE] = "PCIe",
> + [XE_RAS_COMP_FABRIC] = "Fabric",
> + [XE_RAS_COMP_SOC_INTERNAL] = "SoC Internal",
> +};
> +static_assert(ARRAY_SIZE(xe_ras_components) == XE_RAS_COMP_MAX);
> +
> +static inline const char *sev_to_str(struct xe_device *xe, u32 sev)
> +{
> + if (sev >= XE_RAS_SEV_MAX)
> + sev = XE_RAS_SEV_NOT_SUPPORTED;
> +
> + return xe_ras_severities[sev];
> +}
> +
> +static inline const char *comp_to_str(struct xe_device *xe, u32 comp)
> +{
> + if (comp >= XE_RAS_COMP_MAX)
> + comp = XE_RAS_COMP_NOT_SUPPORTED;
> +
> + return xe_ras_components[comp];
> +}
> +
> +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response)
Let the parameter be xe_device for xe_ras file. I don't see sc used in
this function.
I think the second parameter should be void. But upto you.
> +{
> + struct xe_ras_threshold_crossed_data *pending = (void *)&response->data;
> + struct xe_ras_error_class *errors = pending->counters;
> + struct xe_device *xe = sc_to_xe(sc);
> + u32 ncounters = pending->ncounters;
> + u32 cid, sev, comp, inst, cause;
complete names are better than trimming or acronyms
> + u8 tile;
> +
> + if (!ncounters || ncounters >= XE_RAS_NUM_COUNTERS) {
> + xe_err(xe, "sysctrl: unexpected counter threshold crossed %u\n", ncounters);
> + return;
> + }
> +
> + BUILD_BUG_ON(sizeof(response->data) < sizeof(*pending));
> + xe_warn(xe, "[RAS]: counter threshold crossed, %u new errors\n", ncounters);
> +
> + for (cid = 0; cid < ncounters; cid++) {
> + sev = errors[cid].common.severity;
> + comp = errors[cid].common.component;
> +
> + tile = errors[cid].product.unit.tile;
> + inst = errors[cid].product.unit.instance;
> + cause = errors[cid].product.cause.cause;
> +
> + xe_warn(xe, "[RAS]: Tile:%u Instance:%u Component:%s Error:%s Cause:%#x\n",
> + tile, inst, comp_to_str(xe, comp), sev_to_str(xe, sev), cause);
As mentioned in previous revisions, let's keep minimal logging with
severity and component.
Logging should be consistent across all patches so let's keep minimal
for now and add detailed logging
as part of a different series.
> + }
> +}
> diff --git a/drivers/gpu/drm/xe/xe_ras.h b/drivers/gpu/drm/xe/xe_ras.h
> new file mode 100644
> index 000000000000..92ee93d4e877
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_H_
> +#define _XE_RAS_H_
> +
> +struct xe_sysctrl;
> +struct xe_sysctrl_event_response;
> +
> +void xe_ras_threshold_crossed(struct xe_sysctrl *sc, struct xe_sysctrl_event_response *response);
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_ras_types.h b/drivers/gpu/drm/xe/xe_ras_types.h
> new file mode 100644
> index 000000000000..0e3ba9e81538
> --- /dev/null
> +++ b/drivers/gpu/drm/xe/xe_ras_types.h
> @@ -0,0 +1,73 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2026 Intel Corporation
> + */
> +
> +#ifndef _XE_RAS_TYPES_H_
> +#define _XE_RAS_TYPES_H_
> +
> +#include <linux/types.h>
> +
> +#define XE_RAS_NUM_COUNTERS 16
> +
> +/**
> + * struct xe_ras_error_common - Error fields that are common across all products
> + */
> +struct xe_ras_error_common {
> + /** @severity: Error severity */
> + u8 severity;
> + /** @component: IP block where error originated */
> + u8 component;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_unit - Error unit information
> + */
> +struct xe_ras_error_unit {
> + /** @tile: Tile identifier */
> + u8 tile;
> + /** @instance: Instance identifier specific to IP */
> + u32 instance;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_cause - Error cause information
> + */
> +struct xe_ras_error_cause {
> + /** @cause: Cause/checker */
> + u32 cause;
> + /** @reserved: For future use */
> + u8 reserved;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_product - Error fields that are specific to the product
> + */
> +struct xe_ras_error_product {
> + /** @unit: Unit within IP block */
> + struct xe_ras_error_unit unit;
> + /** @cause: Cause/checker */
> + struct xe_ras_error_cause cause;
> +} __packed;
> +
> +/**
> + * struct xe_ras_error_class - Combines common and product-specific parts
> + */
> +struct xe_ras_error_class {
> + /** @common: Common error type and component */
> + struct xe_ras_error_common common;
> + /** @product: Product-specific unit and cause */
> + struct xe_ras_error_product product;
> +} __packed;
> +
> +/**
> + * struct xe_ras_threshold_crossed_data - Data for threshold crossed event
> + */
> +struct xe_ras_threshold_crossed_data {
Why data? Can be xe_ras_threshold_crossed Thanks Riana
> + /** @ncounters: Number of error counters that crossed thresholds */
> + u32 ncounters;
> + /** @counters: Array of error counters that crossed threshold */
> + struct xe_ras_error_class counters[XE_RAS_NUM_COUNTERS];
> +} __packed;
> +
> +#endif
> diff --git a/drivers/gpu/drm/xe/xe_sysctrl_event.c b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> index 8a2e44f4f5e0..139ecd4aafcd 100644
> --- a/drivers/gpu/drm/xe/xe_sysctrl_event.c
> +++ b/drivers/gpu/drm/xe/xe_sysctrl_event.c
> @@ -6,6 +6,7 @@
> #include "xe_device.h"
> #include "xe_irq.h"
> #include "xe_printk.h"
> +#include "xe_ras.h"
> #include "xe_sysctrl.h"
> #include "xe_sysctrl_event_types.h"
> #include "xe_sysctrl_mailbox.h"
> @@ -38,7 +39,7 @@ static void xe_sysctrl_get_pending_event(struct xe_sysctrl *sc,
> }
>
> if (response.event == XE_SYSCTRL_EVENT_THRESHOLD_CROSSED) {
> - xe_warn(xe, "[RAS]: counter threshold crossed\n");
> + xe_ras_threshold_crossed(sc, &response);
> } else {
> xe_err(xe, "sysctrl: unexpected event %#x\n", response.event);
> return;
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2026-04-09 10:15 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2026-04-07 11:06 [PATCH v5 0/3] Introduce Xe Correctable Error Handling Raag Jadav
2026-04-07 11:06 ` [PATCH v5 1/3] drm/xe/sysctrl: Add system controller interrupt handler Raag Jadav
2026-04-09 5:04 ` Tauro, Riana
2026-04-09 6:47 ` Raag Jadav
2026-04-07 11:06 ` [PATCH v5 2/3] drm/xe/sysctrl: Add system controller event support Raag Jadav
2026-04-09 9:57 ` Tauro, Riana
2026-04-07 11:06 ` [PATCH v5 3/3] drm/xe/ras: Introduce correctable error handling Raag Jadav
2026-04-08 12:25 ` Mallesh, Koujalagi
2026-04-09 7:59 ` Raag Jadav
2026-04-09 10:14 ` Tauro, Riana
2026-04-07 12:10 ` ✗ CI.checkpatch: warning for Introduce Xe Correctable Error Handling (rev5) Patchwork
2026-04-07 12:11 ` ✓ CI.KUnit: success " Patchwork
2026-04-07 12:50 ` ✓ Xe.CI.BAT: " Patchwork
2026-04-07 14:29 ` ✓ Xe.CI.FULL: " Patchwork
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox