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mx.microsoft.com 1; spf=pass smtp.mailfrom=intel.com; dmarc=pass action=none header.from=intel.com; dkim=pass header.d=intel.com; arc=none Authentication-Results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=intel.com; Received: from DM4PR11MB5341.namprd11.prod.outlook.com (2603:10b6:5:390::22) by PH7PR11MB5820.namprd11.prod.outlook.com (2603:10b6:510:133::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8722.31; Fri, 30 May 2025 06:22:54 +0000 Received: from DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839]) by DM4PR11MB5341.namprd11.prod.outlook.com ([fe80::397:7566:d626:e839%3]) with mapi id 15.20.8769.025; Fri, 30 May 2025 06:22:54 +0000 Message-ID: <987a8237-6d76-46e7-826a-d4751eab9d86@intel.com> Date: Fri, 30 May 2025 11:52:47 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 03/17] drm/i915/display: Add pipe dmc registers and bits for DC Balance To: Mitul Golani , , CC: References: <20250513051700.507389-1-mitulkumar.ajitkumar.golani@intel.com> <20250513051700.507389-4-mitulkumar.ajitkumar.golani@intel.com> Content-Language: en-US From: "Nautiyal, Ankit K" In-Reply-To: <20250513051700.507389-4-mitulkumar.ajitkumar.golani@intel.com> Content-Type: text/plain; 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(Ankit) > - Use MMIO pipe macros instead of transcoder ones. (Ankit) > - Remove dev_priv use. (Jani, Nikula) > > --v3: > - Add all register address, from capital alphabet to small. (Ankit) > - Add EVT CTL registers. > - Add co-author tag. > - Add event flag for Triggering DC Balance. > > Co-authored-by: Mitul Golani > Signed-off-by: Ville Syrjälä > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_dmc_regs.h | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dmc_regs.h b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > index e16ea3f16ed8..137816cb9e9d 100644 > --- a/drivers/gpu/drm/i915/display/intel_dmc_regs.h > +++ b/drivers/gpu/drm/i915/display/intel_dmc_regs.h > @@ -75,6 +75,7 @@ > #define DMC_EVT_CTL_EVENT_ID_MASK REG_GENMASK(15, 8) > #define DMC_EVT_CTL_EVENT_ID_FALSE 0x01 > #define DMC_EVT_CTL_EVENT_ID_VBLANK_A 0x32 /* main DMC */ > +#define DMC_EVT_CTL_EVENT_ID_ADAPTIVE_DC_BALANCE_TRIGGER 0x3D > /* An event handler scheduled to run at a 1 kHz frequency. */ > #define DMC_EVT_CTL_EVENT_ID_CLK_MSEC 0xbf > > @@ -117,4 +118,55 @@ > #define DMC_WAKELOCK_CTL_REQ REG_BIT(31) > #define DMC_WAKELOCK_CTL_ACK REG_BIT(15) > > +#define _PIPEDMC_DCB_CTL_A 0x5f1a0 > +#define _PIPEDMC_DCB_CTL_B 0x5f5a0 > +#define PIPEDMC_DCB_CTL(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_CTL_A,\ > + _PIPEDMC_DCB_CTL_B) > +#define PIPEDMC_ADAPTIVE_DCB_ENABLE REG_BIT(31) > + > +#define _PIPEDMC_DCB_VBLANK_A 0x5f1bc > +#define _PIPEDMC_DCB_VBLANK_B 0x5f5bc > +#define PIPEDMC_DCB_VBLANK(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VBLANK_A,\ > + _PIPEDMC_DCB_VBLANK_B) > + > +#define _PIPEDMC_DCB_SLOPE_A 0x5f1b8 > +#define _PIPEDMC_DCB_SLOPE_B 0x5f5b8 > +#define PIPEDMC_DCB_SLOPE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_SLOPE_A,\ > + _PIPEDMC_DCB_SLOPE_B) > + > +#define _PIPEDMC_DCB_GUARDBAND_A 0x5f1b4 > +#define _PIPEDMC_DCB_GUARDBAND_B 0x5f5b4 > +#define PIPEDMC_DCB_GUARDBAND(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_GUARDBAND_A,\ > + _PIPEDMC_DCB_GUARDBAND_B) > + > +#define _PIPEDMC_DCB_MAX_INCREASE_A 0x5f1ac > +#define _PIPEDMC_DCB_MAX_INCREASE_B 0x5f5ac > +#define PIPEDMC_DCB_MAX_INCREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_INCREASE_A,\ > + _PIPEDMC_DCB_MAX_INCREASE_B) > + > +#define _PIPEDMC_DCB_MAX_DECREASE_A 0x5f1b0 > +#define _PIPEDMC_DCB_MAX_DECREASE_B 0x5f5b0 > +#define PIPEDMC_DCB_MAX_DECREASE(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_MAX_DECREASE_A,\ > + _PIPEDMC_DCB_MAX_DECREASE_B) > + > +#define _PIPEDMC_DCB_VMIN_A 0x5f1a4 > +#define _PIPEDMC_DCB_VMIN_B 0x5f5a4 > +#define PIPEDMC_DCB_VMIN(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMIN_A,\ > + _PIPEDMC_DCB_VMIN_B) > + > +#define _PIPEDMC_DCB_VMAX_A 0x5f1a8 > +#define _PIPEDMC_DCB_VMAX_B 0x5f5a8 > +#define PIPEDMC_DCB_VMAX(pipe) _MMIO_PIPE((pipe), _PIPEDMC_DCB_VMAX_A,\ > + _PIPEDMC_DCB_VMAX_B) > + > +#define _PIPEDMC_DCB_DEBUG_A 0x5f1c0 > +#define _PIPEDMC_DCB_DEBUG_B 0x5f5c0 > +#define PIPEDMC_DCB_DEBUG(pipe) _MMIO_PIPE(pipe, _PIPEDMC_DCB_DEBUG_A,\ > + _PIPEDMC_DCB_DEBUG_B) > + > +#define _PIPEDMC_EVT_CTL_3_A 0x5f040 > +#define _PIPEDMC_EVT_CTL_3_B 0x5f440 > +#define PIPEDMC_EVT_CTL_3(pipe) _MMIO_PIPE(pipe, _PIPEDMC_EVT_CTL_3_A,\ > + _PIPEDMC_EVT_CTL_3_B) > + > #endif /* __INTEL_DMC_REGS_H__ */