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Fri, 8 Dec 2023 04:22:29 +0000 Received: from MW4PR11MB7056.namprd11.prod.outlook.com ([fe80::8844:2d91:a510:af3c]) by MW4PR11MB7056.namprd11.prod.outlook.com ([fe80::8844:2d91:a510:af3c%4]) with mapi id 15.20.7025.022; Fri, 8 Dec 2023 04:22:29 +0000 Message-ID: <988eb0a4-0808-4e3b-812f-9ebd4b413258@intel.com> Date: Fri, 8 Dec 2023 09:52:24 +0530 User-Agent: Mozilla Thunderbird Subject: Re: [Intel-xe] [PATCH v4 5/9] drm/xe/xe2: Update chunk size for each iteration of ccs copy Content-Language: en-US To: Matt Roper References: <20231206043126.984049-1-himal.prasad.ghimiray@intel.com> <20231206043126.984049-6-himal.prasad.ghimiray@intel.com> <20231207000146.GT1327160@mdroper-desk1.amr.corp.intel.com> From: "Ghimiray, Himal Prasad" In-Reply-To: <20231207000146.GT1327160@mdroper-desk1.amr.corp.intel.com> Content-Type: text/plain; charset="UTF-8"; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: PN2PR01CA0234.INDPRD01.PROD.OUTLOOK.COM (2603:1096:c01:eb::6) To MW4PR11MB7056.namprd11.prod.outlook.com (2603:10b6:303:21a::12) MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MW4PR11MB7056:EE_|DS7PR11MB7952:EE_ X-MS-Office365-Filtering-Correlation-Id: 7c405166-fddd-4974-74ee-08dbf7a54a74 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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>> u64 ccs_ofs, ccs_size; >> u32 ccs_pt; >> + >> bool usm = xe->info.supports_usm; >> + u32 avail_pts = NUM_PT_PER_BLIT; >> >> src_L0 = xe_migrate_res_sizes(&src_it); >> dst_L0 = xe_migrate_res_sizes(&dst_it); >> >> + /* In IGFX the XY_CTRL_SURF_COPY_BLT can handle max of 1024 >> + * pages. Hence limit the processing size to SZ_4M per >> + * iteration. >> + */ >> + if (!IS_DGFX(xe) && GRAPHICS_VER(xe) >= 20) { > Where is the igpu limitation coming from? The change to expressing copy > size in terms of pages seems to be a general Xe2 IP change that we'd > expect all future platforms, both igpu and dgpu to follow. I added the limitation considering dgfx can have 64 K pages. And then limiting size should be decided by xe_migrate_res_sizes. Will try to make this change more generic in next version. > > >> + src_L0 = min_t(u64, src_L0, SZ_4M); >> + dst_L0 = min_t(u64, dst_L0, SZ_4M); >> + >> + avail_pts = SZ_4M / SZ_2M; > What does the SZ_2M here represent? It's not super obvious. > > Also, even though you have a comment above, it still might be nicer to > "show the work" for SZ_4M instead of using a magic number. E.g., > > XE_PAGE_SIZE * (FIELD_MAX(XE2_CCS_SIZE_MASK) + 1) / ... > > > Matt > >> + } >> + >> drm_dbg(&xe->drm, "Pass %u, sizes: %llu & %llu\n", >> pass++, src_L0, dst_L0); >> >> @@ -684,18 +697,18 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, >> >> batch_size += pte_update_size(m, src_is_vram, src, &src_it, &src_L0, >> &src_L0_ofs, &src_L0_pt, 0, 0, >> - NUM_PT_PER_BLIT); >> + avail_pts); >> >> batch_size += pte_update_size(m, dst_is_vram, dst, &dst_it, &src_L0, >> &dst_L0_ofs, &dst_L0_pt, 0, >> - NUM_PT_PER_BLIT, NUM_PT_PER_BLIT); >> + avail_pts, avail_pts); >> >> if (copy_system_ccs) { >> ccs_size = xe_device_ccs_bytes(xe, src_L0); >> batch_size += pte_update_size(m, false, NULL, &ccs_it, &ccs_size, >> &ccs_ofs, &ccs_pt, 0, >> - 2 * NUM_PT_PER_BLIT, >> - NUM_PT_PER_BLIT); >> + 2 * avail_pts, >> + avail_pts); >> } >> >> /* Add copy commands size here */ >> @@ -923,8 +936,19 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m, >> struct xe_bb *bb; >> u32 batch_size, update_idx; >> bool usm = xe->info.supports_usm; >> + u32 avail_pts = NUM_PT_PER_BLIT; >> >> clear_L0 = xe_migrate_res_sizes(&src_it); >> + >> + /* In IGFX the XY_CTRL_SURF_COPY_BLT can handle max of 1024 >> + * pages. Hence limit the processing size to SZ_4M per >> + * iteration. >> + */ >> + if (!IS_DGFX(xe) && GRAPHICS_VER(xe) >= 20) { >> + clear_L0 = min_t(u64, clear_L0, SZ_4M); >> + avail_pts = SZ_4M / SZ_2M; >> + } >> + >> drm_dbg(&xe->drm, "Pass %u, size: %llu\n", pass++, clear_L0); >> >> /* Calculate final sizes and batch size.. */ >> @@ -932,7 +956,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m, >> pte_update_size(m, clear_vram, src, &src_it, >> &clear_L0, &clear_L0_ofs, &clear_L0_pt, >> emit_clear_cmd_len(gt), 0, >> - NUM_PT_PER_BLIT); >> + avail_pts); >> if (xe_device_has_flat_ccs(xe) && clear_vram) >> batch_size += EMIT_COPY_CCS_DW; >> >> -- >> 2.25.1 >>