Re: [PATCH] drm/xe/xe2: Add workaround 14021402888

["Ghimiray, Himal Prasad" <himal.prasad.ghimiray@intel.com>]

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On 17-04-2024 07:48, Bommu Krishnaiah wrote:
> Sampler Cache Returning Incorrect Data Due to Mismatched Tagging of
> Associated Partial Cache Lines and disabling sampler clear power
> optimization gives better overall performance.

Inconsistent capitalization in commit message.

>
> Signed-off-by: Bommu Krishnaiah<krishnaiah.bommu@intel.com>
> Cc: Tejas Upadhyay<tejas.upadhyay@intel.com>
> Cc: Matt Roper<matthew.d.roper@intel.com>
> ---
>   drivers/gpu/drm/xe/regs/xe_gt_regs.h | 2 ++
>   drivers/gpu/drm/xe/xe_wa.c           | 8 ++++++++
>   2 files changed, 10 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 94445810ccc9..d4ec82189ca2 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -344,12 +344,14 @@
>   
>   #define SAMPLER_MODE				XE_REG_MCR(0xe18c, XE_REG_OPTION_MASKED)
>   #define   ENABLE_SMALLPL			REG_BIT(15)
> +#define   SMP_FORCE_128B_OVERFETCH		REG_BIT(10)
>   #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>   #define   SAMPLER_ENABLE_HEADLESS_MSG		REG_BIT(5)
>   #define   INDIRECT_STATE_BASE_ADDR_OVERRIDE	REG_BIT(0)
>   
>   #define HALF_SLICE_CHICKEN7				XE_REG_MCR(0xe194, XE_REG_OPTION_MASKED)
>   #define   DG2_DISABLE_ROUND_ENABLE_ALLOW_FOR_SSLA	REG_BIT(15)
> +#define   CLEAR_OPTIMIZATION_DISABLE			REG_BIT(6)
>   
>   #define CACHE_MODE_SS				XE_REG_MCR(0xe420, XE_REG_OPTION_MASKED)
>   #define   DISABLE_ECC				REG_BIT(5)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index 632bd9066f8d..91c9834c3e21 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -534,6 +534,14 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>   		       FUNC(xe_rtp_match_first_render_or_compute)),
>   	  XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0, WR_REQ_CHAINING_DIS))
>   	},
> +	{ XE_RTP_NAME("14021402888"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(SAMPLER_MODE, SMP_FORCE_128B_OVERFETCH))
This is not required.   Below implementation (Setting 
CLEAR_OPTIMIZATION_DISABLE REG_BIT(6) of HALF_SLICE_CHICKEN7) should be 
enough.
> +	},
> +	{ XE_RTP_NAME("14021402888"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2001), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(SET(HALF_SLICE_CHICKEN7, CLEAR_OPTIMIZATION_DISABLE))
> +	},
>   
>   	/* Xe2_HPM */
>   

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