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From: Jani Nikula <jani.nikula@intel.com>
To: "Shankar, Uma" <uma.shankar@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: RE: [PATCH] drm/i915: move GEN7_ERR_INT snapshot to display irq code
Date: Fri, 23 Jan 2026 11:44:13 +0200	[thread overview]
Message-ID: <9c2bee04bf61874849aa53af3baae3f878dcbf19@intel.com> (raw)
In-Reply-To: <CY5PR11MB6344156110390114E8974C33F494A@CY5PR11MB6344.namprd11.prod.outlook.com>

On Fri, 23 Jan 2026, "Shankar, Uma" <uma.shankar@intel.com> wrote:
>> -----Original Message-----
>> From: Nikula, Jani <jani.nikula@intel.com>
>> Sent: Thursday, January 22, 2026 6:08 PM
>> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
>> Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
>> <uma.shankar@intel.com>
>> Subject: [PATCH] drm/i915: move GEN7_ERR_INT snapshot to display irq code
>> 
>> The error interrupt register GEN7_ERR_INT is a display irq register. Move its
>> GPU error capture to display irq snapshot.
>
> Looks Good to me.
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>

Thanks, pushed to din.

BR,
Jani.

>
>> Cc: Uma Shankar <uma.shankar@intel.com>
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_display_irq.c | 5 +++++
>>  drivers/gpu/drm/i915/i915_gpu_error.c            | 6 ------
>>  drivers/gpu/drm/i915/i915_gpu_error.h            | 1 -
>>  3 files changed, 5 insertions(+), 7 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c
>> b/drivers/gpu/drm/i915/display/intel_display_irq.c
>> index 9adeebb376b1..0a71840041de 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
>> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
>> @@ -2472,6 +2472,7 @@ void intel_display_irq_init(struct intel_display *display)
>> 
>>  struct intel_display_irq_snapshot {
>>  	u32 derrmr;
>> +	u32 err_int;
>>  };
>> 
>>  struct intel_display_irq_snapshot *
>> @@ -2486,6 +2487,9 @@ intel_display_irq_snapshot_capture(struct intel_display
>> *display)
>>  	if (DISPLAY_VER(display) >= 6 && DISPLAY_VER(display) < 20 &&
>> !HAS_GMCH(display))
>>  		snapshot->derrmr = intel_de_read(display, DERRMR);
>> 
>> +	if (DISPLAY_VER(display) == 7)
>> +		snapshot->err_int = intel_de_read(display, GEN7_ERR_INT);
>> +
>>  	return snapshot;
>>  }
>> 
>> @@ -2496,4 +2500,5 @@ void intel_display_irq_snapshot_print(const struct
>> intel_display_irq_snapshot *s
>>  		return;
>> 
>>  	drm_printf(p, "DERRMR: 0x%08x\n", snapshot->derrmr);
>> +	drm_printf(p, "ERR_INT: 0x%08x\n", snapshot->err_int);
>>  }
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c
>> b/drivers/gpu/drm/i915/i915_gpu_error.c
>> index 303d8d9b7775..31c5341fb9cf 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.c
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.c
>> @@ -824,9 +824,6 @@ static void err_print_gt_global(struct
>> drm_i915_error_state_buf *m,
>>  		err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
>>  			   gt->fault_data1, gt->fault_data0);
>> 
>> -	if (GRAPHICS_VER(m->i915) == 7)
>> -		err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
>> -
>>  	if (IS_GRAPHICS_VER(m->i915, 8, 11))
>>  		err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
>> 
>> @@ -1929,9 +1926,6 @@ static void gt_record_global_regs(struct
>> intel_gt_coredump *gt)
>>  	if (IS_VALLEYVIEW(i915))
>>  		gt->forcewake = intel_uncore_read_fw(uncore,
>> FORCEWAKE_VLV);
>> 
>> -	if (GRAPHICS_VER(i915) == 7)
>> -		gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
>> -
>>  	if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 55)) {
>>  		gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
>> 
>> 	XEHP_FAULT_TLB_DATA0);
>> diff --git a/drivers/gpu/drm/i915/i915_gpu_error.h
>> b/drivers/gpu/drm/i915/i915_gpu_error.h
>> index 91b3df621a49..26970c5e291e 100644
>> --- a/drivers/gpu/drm/i915/i915_gpu_error.h
>> +++ b/drivers/gpu/drm/i915/i915_gpu_error.h
>> @@ -149,7 +149,6 @@ struct intel_gt_coredump {
>>  	u32 gtier[6], ngtier;
>>  	u32 forcewake;
>>  	u32 error; /* gen6+ */
>> -	u32 err_int; /* gen7 */
>>  	u32 fault_data0; /* gen8, gen9 */
>>  	u32 fault_data1; /* gen8, gen9 */
>>  	u32 done_reg;
>> --
>> 2.47.3
>

-- 
Jani Nikula, Intel

      reply	other threads:[~2026-01-23  9:45 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-01-22 12:37 [PATCH] drm/i915: move GEN7_ERR_INT snapshot to display irq code Jani Nikula
2026-01-22 13:37 ` ✓ CI.KUnit: success for " Patchwork
2026-01-22 14:40 ` ✓ Xe.CI.BAT: " Patchwork
2026-01-23  4:24 ` ✗ Xe.CI.Full: failure " Patchwork
2026-01-23  6:18 ` [PATCH] " Shankar, Uma
2026-01-23  9:44   ` Jani Nikula [this message]

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