[PATCH 0/4] drm/i915/vbt: cleanups and new fields

[PATCH 0/4] drm/i915/vbt: cleanups and new fields

[Jani Nikula]

Jani Nikula (4):
  drm/i915/vbt: split up DSI VBT defs to a separate file
  drm/i915/vbt: add anonymous structs to group DSI VBT defs
  drm/i915/vbt: flip bta_enabled to bta_disable
  drm/i915/vbt: add missing DSI VBT defs

 drivers/gpu/drm/i915/display/intel_bios.h     | 174 ----------------
 .../drm/i915/display/intel_display_types.h    |   1 +
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c  |   2 +-
 .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 197 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
 5 files changed, 200 insertions(+), 176 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h

-- 
2.47.2

[PATCH 1/4] drm/i915/vbt: split up DSI VBT defs to a separate file

[Jani Nikula]

The DSI VBT definitions have ended up in intel_bios.h, because
intel_vbt_defs.h is supposed to be internal to intel_bios.c, but the DSI
VBT definitions are needed in more places.

Split out the DSI VBT definitions to intel_dsi_vbt_defs.h. This will
also help keep the definitions in sync with IGT.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bios.h     | 174 -----------------
 .../drm/i915/display/intel_display_types.h    |   1 +
 .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 183 ++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
 4 files changed, 185 insertions(+), 175 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h

diff --git a/drivers/gpu/drm/i915/display/intel_bios.h b/drivers/gpu/drm/i915/display/intel_bios.h
index 6cd7a011b8c4..8fdde85f7939 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.h
+++ b/drivers/gpu/drm/i915/display/intel_bios.h
@@ -50,180 +50,6 @@ enum intel_backlight_type {
 	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
 };
 
-/*
- * MIPI Sequence Block definitions
- *
- * Note the VBT spec has AssertReset / DeassertReset swapped from their
- * usual naming, we use the proper names here to avoid confusion when
- * reading the code.
- */
-enum mipi_seq {
-	MIPI_SEQ_END = 0,
-	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
-	MIPI_SEQ_INIT_OTP,
-	MIPI_SEQ_DISPLAY_ON,
-	MIPI_SEQ_DISPLAY_OFF,
-	MIPI_SEQ_ASSERT_RESET,		/* Spec says MipiDeassertResetPin */
-	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
-	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
-	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
-	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
-	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
-	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
-	MIPI_SEQ_MAX
-};
-
-enum mipi_seq_element {
-	MIPI_SEQ_ELEM_END = 0,
-	MIPI_SEQ_ELEM_SEND_PKT,
-	MIPI_SEQ_ELEM_DELAY,
-	MIPI_SEQ_ELEM_GPIO,
-	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
-	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
-	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
-	MIPI_SEQ_ELEM_MAX
-};
-
-#define MIPI_DSI_UNDEFINED_PANEL_ID	0
-#define MIPI_DSI_GENERIC_PANEL_ID	1
-
-struct mipi_config {
-	u16 panel_id;
-
-	/* General Params */
-	u32 enable_dithering:1;
-	u32 rsvd1:1;
-	u32 is_bridge:1;
-
-	u32 panel_arch_type:2;
-	u32 is_cmd_mode:1;
-
-#define NON_BURST_SYNC_PULSE	0x1
-#define NON_BURST_SYNC_EVENTS	0x2
-#define BURST_MODE		0x3
-	u32 video_transfer_mode:2;
-
-	u32 cabc_supported:1;
-#define PPS_BLC_PMIC   0
-#define PPS_BLC_SOC    1
-	u32 pwm_blc:1;
-
-	/* Bit 13:10 */
-#define PIXEL_FORMAT_RGB565			0x1
-#define PIXEL_FORMAT_RGB666			0x2
-#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
-#define PIXEL_FORMAT_RGB888			0x4
-	u32 videomode_color_format:4;
-
-	/* Bit 15:14 */
-#define ENABLE_ROTATION_0	0x0
-#define ENABLE_ROTATION_90	0x1
-#define ENABLE_ROTATION_180	0x2
-#define ENABLE_ROTATION_270	0x3
-	u32 rotation:2;
-	u32 bta_enabled:1;
-	u32 rsvd2:15;
-
-	/* 2 byte Port Description */
-#define DUAL_LINK_NOT_SUPPORTED	0
-#define DUAL_LINK_FRONT_BACK	1
-#define DUAL_LINK_PIXEL_ALT	2
-	u16 dual_link:2;
-	u16 lane_cnt:2;
-	u16 pixel_overlap:3;
-	u16 rgb_flip:1;
-#define DL_DCS_PORT_A			0x00
-#define DL_DCS_PORT_C			0x01
-#define DL_DCS_PORT_A_AND_C		0x02
-	u16 dl_dcs_cabc_ports:2;
-	u16 dl_dcs_backlight_ports:2;
-	u16 rsvd3:4;
-
-	u16 rsvd4;
-
-	u8 rsvd5;
-	u32 target_burst_mode_freq;
-	u32 dsi_ddr_clk;
-	u32 bridge_ref_clk;
-
-#define  BYTE_CLK_SEL_20MHZ		0
-#define  BYTE_CLK_SEL_10MHZ		1
-#define  BYTE_CLK_SEL_5MHZ		2
-	u8 byte_clk_sel:2;
-
-	u8 rsvd6:6;
-
-	/* DPHY Flags */
-	u16 dphy_param_valid:1;
-	u16 eot_pkt_disabled:1;
-	u16 enable_clk_stop:1;
-	u16 rsvd7:13;
-
-	u32 hs_tx_timeout;
-	u32 lp_rx_timeout;
-	u32 turn_around_timeout;
-	u32 device_reset_timer;
-	u32 master_init_timer;
-	u32 dbi_bw_timer;
-	u32 lp_byte_clk_val;
-
-	/*  4 byte Dphy Params */
-	u32 prepare_cnt:6;
-	u32 rsvd8:2;
-	u32 clk_zero_cnt:8;
-	u32 trail_cnt:5;
-	u32 rsvd9:3;
-	u32 exit_zero_cnt:6;
-	u32 rsvd10:2;
-
-	u32 clk_lane_switch_cnt;
-	u32 hl_switch_cnt;
-
-	u32 rsvd11[6];
-
-	/* timings based on dphy spec */
-	u8 tclk_miss;
-	u8 tclk_post;
-	u8 rsvd12;
-	u8 tclk_pre;
-	u8 tclk_prepare;
-	u8 tclk_settle;
-	u8 tclk_term_enable;
-	u8 tclk_trail;
-	u16 tclk_prepare_clkzero;
-	u8 rsvd13;
-	u8 td_term_enable;
-	u8 teot;
-	u8 ths_exit;
-	u8 ths_prepare;
-	u16 ths_prepare_hszero;
-	u8 rsvd14;
-	u8 ths_settle;
-	u8 ths_skip;
-	u8 ths_trail;
-	u8 tinit;
-	u8 tlpx;
-	u8 rsvd15[3];
-
-	/* GPIOs */
-	u8 panel_enable;
-	u8 bl_enable;
-	u8 pwm_enable;
-	u8 reset_r_n;
-	u8 pwr_down_r;
-	u8 stdby_r_n;
-
-} __packed;
-
-/* all delays have a unit of 100us */
-struct mipi_pps_data {
-	u16 panel_on_delay;
-	u16 bl_enable_delay;
-	u16 bl_disable_delay;
-	u16 panel_off_delay;
-	u16 panel_power_cycle_delay;
-} __packed;
-
 void intel_bios_init(struct intel_display *display);
 void intel_bios_init_panel_early(struct intel_display *display,
 				 struct intel_panel *panel,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 35596f3921e8..0d945d1fedd6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -50,6 +50,7 @@
 #include "intel_display_limits.h"
 #include "intel_display_power.h"
 #include "intel_dpll_mgr.h"
+#include "intel_dsi_vbt_defs.h"
 #include "intel_wm_types.h"
 
 struct cec_notifier;
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
new file mode 100644
index 000000000000..f83d42ed0c5a
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: MIT */
+/* Copyright © 2025 Intel Corporation */
+
+#ifndef __INTEL_DSI_VBT_DEFS_H__
+#define __INTEL_DSI_VBT_DEFS_H__
+
+#include <linux/types.h>
+
+/*
+ * MIPI Sequence Block definitions
+ *
+ * Note the VBT spec has AssertReset / DeassertReset swapped from their
+ * usual naming, we use the proper names here to avoid confusion when
+ * reading the code.
+ */
+enum mipi_seq {
+	MIPI_SEQ_END = 0,
+	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
+	MIPI_SEQ_INIT_OTP,
+	MIPI_SEQ_DISPLAY_ON,
+	MIPI_SEQ_DISPLAY_OFF,
+	MIPI_SEQ_ASSERT_RESET,		/* Spec says MipiDeassertResetPin */
+	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
+	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
+	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
+	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
+	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
+	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
+	MIPI_SEQ_MAX
+};
+
+enum mipi_seq_element {
+	MIPI_SEQ_ELEM_END = 0,
+	MIPI_SEQ_ELEM_SEND_PKT,
+	MIPI_SEQ_ELEM_DELAY,
+	MIPI_SEQ_ELEM_GPIO,
+	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
+	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
+	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
+	MIPI_SEQ_ELEM_MAX
+};
+
+#define MIPI_DSI_UNDEFINED_PANEL_ID	0
+#define MIPI_DSI_GENERIC_PANEL_ID	1
+
+struct mipi_config {
+	u16 panel_id;
+
+	/* General Params */
+	u32 enable_dithering:1;
+	u32 rsvd1:1;
+	u32 is_bridge:1;
+
+	u32 panel_arch_type:2;
+	u32 is_cmd_mode:1;
+
+#define NON_BURST_SYNC_PULSE	0x1
+#define NON_BURST_SYNC_EVENTS	0x2
+#define BURST_MODE		0x3
+	u32 video_transfer_mode:2;
+
+	u32 cabc_supported:1;
+#define PPS_BLC_PMIC   0
+#define PPS_BLC_SOC    1
+	u32 pwm_blc:1;
+
+	/* Bit 13:10 */
+#define PIXEL_FORMAT_RGB565			0x1
+#define PIXEL_FORMAT_RGB666			0x2
+#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
+#define PIXEL_FORMAT_RGB888			0x4
+	u32 videomode_color_format:4;
+
+	/* Bit 15:14 */
+#define ENABLE_ROTATION_0	0x0
+#define ENABLE_ROTATION_90	0x1
+#define ENABLE_ROTATION_180	0x2
+#define ENABLE_ROTATION_270	0x3
+	u32 rotation:2;
+	u32 bta_enabled:1;
+	u32 rsvd2:15;
+
+	/* 2 byte Port Description */
+#define DUAL_LINK_NOT_SUPPORTED	0
+#define DUAL_LINK_FRONT_BACK	1
+#define DUAL_LINK_PIXEL_ALT	2
+	u16 dual_link:2;
+	u16 lane_cnt:2;
+	u16 pixel_overlap:3;
+	u16 rgb_flip:1;
+#define DL_DCS_PORT_A			0x00
+#define DL_DCS_PORT_C			0x01
+#define DL_DCS_PORT_A_AND_C		0x02
+	u16 dl_dcs_cabc_ports:2;
+	u16 dl_dcs_backlight_ports:2;
+	u16 rsvd3:4;
+
+	u16 rsvd4;
+
+	u8 rsvd5;
+	u32 target_burst_mode_freq;
+	u32 dsi_ddr_clk;
+	u32 bridge_ref_clk;
+
+#define  BYTE_CLK_SEL_20MHZ		0
+#define  BYTE_CLK_SEL_10MHZ		1
+#define  BYTE_CLK_SEL_5MHZ		2
+	u8 byte_clk_sel:2;
+
+	u8 rsvd6:6;
+
+	/* DPHY Flags */
+	u16 dphy_param_valid:1;
+	u16 eot_pkt_disabled:1;
+	u16 enable_clk_stop:1;
+	u16 rsvd7:13;
+
+	u32 hs_tx_timeout;
+	u32 lp_rx_timeout;
+	u32 turn_around_timeout;
+	u32 device_reset_timer;
+	u32 master_init_timer;
+	u32 dbi_bw_timer;
+	u32 lp_byte_clk_val;
+
+	/*  4 byte Dphy Params */
+	u32 prepare_cnt:6;
+	u32 rsvd8:2;
+	u32 clk_zero_cnt:8;
+	u32 trail_cnt:5;
+	u32 rsvd9:3;
+	u32 exit_zero_cnt:6;
+	u32 rsvd10:2;
+
+	u32 clk_lane_switch_cnt;
+	u32 hl_switch_cnt;
+
+	u32 rsvd11[6];
+
+	/* timings based on dphy spec */
+	u8 tclk_miss;
+	u8 tclk_post;
+	u8 rsvd12;
+	u8 tclk_pre;
+	u8 tclk_prepare;
+	u8 tclk_settle;
+	u8 tclk_term_enable;
+	u8 tclk_trail;
+	u16 tclk_prepare_clkzero;
+	u8 rsvd13;
+	u8 td_term_enable;
+	u8 teot;
+	u8 ths_exit;
+	u8 ths_prepare;
+	u16 ths_prepare_hszero;
+	u8 rsvd14;
+	u8 ths_settle;
+	u8 ths_skip;
+	u8 ths_trail;
+	u8 tinit;
+	u8 tlpx;
+	u8 rsvd15[3];
+
+	/* GPIOs */
+	u8 panel_enable;
+	u8 bl_enable;
+	u8 pwm_enable;
+	u8 reset_r_n;
+	u8 pwr_down_r;
+	u8 stdby_r_n;
+
+} __packed;
+
+/* all delays have a unit of 100us */
+struct mipi_pps_data {
+	u16 panel_on_delay;
+	u16 bl_enable_delay;
+	u16 bl_disable_delay;
+	u16 panel_off_delay;
+	u16 panel_power_cycle_delay;
+} __packed;
+
+#endif /* __INTEL_DSI_VBT_DEFS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
index 92c04811aa28..6612d3a4ec49 100644
--- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
@@ -37,7 +37,7 @@
 #ifndef _INTEL_VBT_DEFS_H_
 #define _INTEL_VBT_DEFS_H_
 
-#include "intel_bios.h"
+#include "intel_dsi_vbt_defs.h"
 
 /* EDID derived structures */
 struct bdb_edid_pnp_id {
-- 
2.47.2

[PATCH 2/4] drm/i915/vbt: add anonymous structs to group DSI VBT defs

[Jani Nikula]

The grouping of DSI VBT definitions is hard to follow and match against
the spec. Use anonymous structs and add comments with the spec
description.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 87 ++++++++++---------
 1 file changed, 47 insertions(+), 40 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
index f83d42ed0c5a..7ac872dbba8d 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
@@ -47,53 +47,55 @@ struct mipi_config {
 	u16 panel_id;
 
 	/* General Params */
-	u32 enable_dithering:1;
-	u32 rsvd1:1;
-	u32 is_bridge:1;
+	struct {
+		u32 enable_dithering:1;
+		u32 rsvd1:1;
+		u32 is_bridge:1;
 
-	u32 panel_arch_type:2;
-	u32 is_cmd_mode:1;
+		u32 panel_arch_type:2;
+		u32 is_cmd_mode:1;
 
 #define NON_BURST_SYNC_PULSE	0x1
 #define NON_BURST_SYNC_EVENTS	0x2
 #define BURST_MODE		0x3
-	u32 video_transfer_mode:2;
+		u32 video_transfer_mode:2;
 
-	u32 cabc_supported:1;
+		u32 cabc_supported:1;
 #define PPS_BLC_PMIC   0
 #define PPS_BLC_SOC    1
-	u32 pwm_blc:1;
+		u32 pwm_blc:1;
 
-	/* Bit 13:10 */
 #define PIXEL_FORMAT_RGB565			0x1
 #define PIXEL_FORMAT_RGB666			0x2
 #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
 #define PIXEL_FORMAT_RGB888			0x4
-	u32 videomode_color_format:4;
+		u32 videomode_color_format:4;
 
-	/* Bit 15:14 */
 #define ENABLE_ROTATION_0	0x0
 #define ENABLE_ROTATION_90	0x1
 #define ENABLE_ROTATION_180	0x2
 #define ENABLE_ROTATION_270	0x3
-	u32 rotation:2;
-	u32 bta_enabled:1;
-	u32 rsvd2:15;
+		u32 rotation:2;
+		u32 bta_enabled:1;
+		u32 rsvd2:15;
+	} __packed;
 
-	/* 2 byte Port Description */
+	/* Port Desc */
+	struct {
 #define DUAL_LINK_NOT_SUPPORTED	0
 #define DUAL_LINK_FRONT_BACK	1
 #define DUAL_LINK_PIXEL_ALT	2
-	u16 dual_link:2;
-	u16 lane_cnt:2;
-	u16 pixel_overlap:3;
-	u16 rgb_flip:1;
+		u16 dual_link:2;
+		u16 lane_cnt:2;
+		u16 pixel_overlap:3;
+		u16 rgb_flip:1;
 #define DL_DCS_PORT_A			0x00
 #define DL_DCS_PORT_C			0x01
 #define DL_DCS_PORT_A_AND_C		0x02
-	u16 dl_dcs_cabc_ports:2;
-	u16 dl_dcs_backlight_ports:2;
-	u16 rsvd3:4;
+		u16 dl_dcs_cabc_ports:2;
+		u16 dl_dcs_backlight_ports:2;
+		u16 rsvd3:4;
+	} __packed;
 
 	u16 rsvd4;
 
@@ -102,18 +104,22 @@ struct mipi_config {
 	u32 dsi_ddr_clk;
 	u32 bridge_ref_clk;
 
+	/* LP Byte Clock */
+	struct {
 #define  BYTE_CLK_SEL_20MHZ		0
 #define  BYTE_CLK_SEL_10MHZ		1
 #define  BYTE_CLK_SEL_5MHZ		2
-	u8 byte_clk_sel:2;
-
-	u8 rsvd6:6;
-
-	/* DPHY Flags */
-	u16 dphy_param_valid:1;
-	u16 eot_pkt_disabled:1;
-	u16 enable_clk_stop:1;
-	u16 rsvd7:13;
+		u8 byte_clk_sel:2;
+		u8 rsvd6:6;
+	} __packed;
+
+	/* DPhy Flags */
+	struct {
+		u16 dphy_param_valid:1;
+		u16 eot_pkt_disabled:1;
+		u16 enable_clk_stop:1;
+		u16 rsvd7:13;
+	} __packed;
 
 	u32 hs_tx_timeout;
 	u32 lp_rx_timeout;
@@ -123,14 +129,16 @@ struct mipi_config {
 	u32 dbi_bw_timer;
 	u32 lp_byte_clk_val;
 
-	/*  4 byte Dphy Params */
-	u32 prepare_cnt:6;
-	u32 rsvd8:2;
-	u32 clk_zero_cnt:8;
-	u32 trail_cnt:5;
-	u32 rsvd9:3;
-	u32 exit_zero_cnt:6;
-	u32 rsvd10:2;
+	/*  DPhy Params */
+	struct {
+		u32 prepare_cnt:6;
+		u32 rsvd8:2;
+		u32 clk_zero_cnt:8;
+		u32 trail_cnt:5;
+		u32 rsvd9:3;
+		u32 exit_zero_cnt:6;
+		u32 rsvd10:2;
+	} __packed;
 
 	u32 clk_lane_switch_cnt;
 	u32 hl_switch_cnt;
@@ -168,7 +176,6 @@ struct mipi_config {
 	u8 reset_r_n;
 	u8 pwr_down_r;
 	u8 stdby_r_n;
-
 } __packed;
 
 /* all delays have a unit of 100us */
-- 
2.47.2

[PATCH 3/4] drm/i915/vbt: flip bta_enabled to bta_disable

[Jani Nikula]

The meaning is disable, so flip the member name.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt.c      | 2 +-
 drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index e6a851d276f8..23402408e172 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -777,7 +777,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16 panel_id)
 	intel_dsi->init_count = mipi_config->master_init_timer;
 	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
 	intel_dsi->video_frmt_cfg_bits =
-		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
+		mipi_config->bta_disable ? DISABLE_VIDEO_BTA : 0;
 	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
 
 	/* Starting point, adjusted depending on dual link and burst mode */
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
index 7ac872dbba8d..3f9b9ed6592c 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
@@ -76,7 +76,7 @@ struct mipi_config {
 #define ENABLE_ROTATION_180	0x2
 #define ENABLE_ROTATION_270	0x3
 		u32 rotation:2;
-		u32 bta_enabled:1;
+		u32 bta_disable:1;
 		u32 rsvd2:15;
 	} __packed;
 
-- 
2.47.2

[PATCH 4/4] drm/i915/vbt: add missing DSI VBT defs

[Jani Nikula]

Add some missing DSI VBT definitions.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
index 3f9b9ed6592c..edc7331dcca2 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
@@ -94,10 +94,15 @@ struct mipi_config {
 #define DL_DCS_PORT_A_AND_C		0x02
 		u16 dl_dcs_cabc_ports:2;
 		u16 dl_dcs_backlight_ports:2;
-		u16 rsvd3:4;
+		u16 port_sync:1;				/* 219-230 */
+		u16 rsvd3:3;
 	} __packed;
 
-	u16 rsvd4;
+	/* DSI Controller Parameters */
+	struct {
+		u16 dsi_usage:1;
+		u16 rsvd4:15;
+	} __packed;
 
 	u8 rsvd5;
 	u32 target_burst_mode_freq;
@@ -118,7 +123,9 @@ struct mipi_config {
 		u16 dphy_param_valid:1;
 		u16 eot_pkt_disabled:1;
 		u16 enable_clk_stop:1;
-		u16 rsvd7:13;
+		u16 blanking_packets_during_bllp:1;		/* 219+ */
+		u16 lp_clock_during_lpm:1;			/* 219+ */
+		u16 rsvd7:11;
 	} __packed;
 
 	u32 hs_tx_timeout;
-- 
2.47.2

✗ CI.checkpatch: warning for drm/i915/vbt: cleanups and new fields

[Patchwork]

== Series Details ==

Series: drm/i915/vbt: cleanups and new fields
URL   : https://patchwork.freedesktop.org/series/152780/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
6f9293a391ff3c575bc021f454be5d0a0c076f57
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 3173c44fa8965c0ec2100fda5587607ff8a4dfb1
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Mon Aug 11 18:25:50 2025 +0300

    drm/i915/vbt: add missing DSI VBT defs
    
    Add some missing DSI VBT definitions.
    
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 008ca7d455ca7f73eeca04881640f7c43a994370 drm-intel
f43f9981953b drm/i915/vbt: split up DSI VBT defs to a separate file
-:213: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#213: 
new file mode 100644

total: 0 errors, 1 warnings, 0 checks, 378 lines checked
f00ef34d7674 drm/i915/vbt: add anonymous structs to group DSI VBT defs
d0ac8799ca36 drm/i915/vbt: flip bta_enabled to bta_disable
3173c44fa896 drm/i915/vbt: add missing DSI VBT defs

✓ CI.KUnit: success for drm/i915/vbt: cleanups and new fields

[Patchwork]

== Series Details ==

Series: drm/i915/vbt: cleanups and new fields
URL   : https://patchwork.freedesktop.org/series/152780/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[16:48:53] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:48:58] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:49:42] Starting KUnit Kernel (1/1)...
[16:49:42] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:49:42] ================== guc_buf (11 subtests) ===================
[16:49:42] [PASSED] test_smallest
[16:49:42] [PASSED] test_largest
[16:49:42] [PASSED] test_granular
[16:49:42] [PASSED] test_unique
[16:49:42] [PASSED] test_overlap
[16:49:42] [PASSED] test_reusable
[16:49:42] [PASSED] test_too_big
[16:49:42] [PASSED] test_flush
[16:49:42] [PASSED] test_lookup
[16:49:42] [PASSED] test_data
[16:49:42] [PASSED] test_class
[16:49:42] ===================== [PASSED] guc_buf =====================
[16:49:42] =================== guc_dbm (7 subtests) ===================
[16:49:42] [PASSED] test_empty
[16:49:42] [PASSED] test_default
[16:49:42] ======================== test_size  ========================
[16:49:42] [PASSED] 4
[16:49:42] [PASSED] 8
[16:49:42] [PASSED] 32
[16:49:42] [PASSED] 256
[16:49:42] ==================== [PASSED] test_size ====================
[16:49:42] ======================= test_reuse  ========================
[16:49:42] [PASSED] 4
[16:49:42] [PASSED] 8
[16:49:42] [PASSED] 32
[16:49:42] [PASSED] 256
[16:49:42] =================== [PASSED] test_reuse ====================
[16:49:42] =================== test_range_overlap  ====================
[16:49:42] [PASSED] 4
[16:49:42] [PASSED] 8
[16:49:42] [PASSED] 32
[16:49:42] [PASSED] 256
[16:49:42] =============== [PASSED] test_range_overlap ================
[16:49:42] =================== test_range_compact  ====================
[16:49:42] [PASSED] 4
[16:49:42] [PASSED] 8
[16:49:42] [PASSED] 32
[16:49:42] [PASSED] 256
[16:49:42] =============== [PASSED] test_range_compact ================
[16:49:42] ==================== test_range_spare  =====================
[16:49:42] [PASSED] 4
[16:49:42] [PASSED] 8
[16:49:42] [PASSED] 32
[16:49:42] [PASSED] 256
[16:49:42] ================ [PASSED] test_range_spare =================
[16:49:42] ===================== [PASSED] guc_dbm =====================
[16:49:42] =================== guc_idm (6 subtests) ===================
[16:49:42] [PASSED] bad_init
[16:49:42] [PASSED] no_init
[16:49:42] [PASSED] init_fini
[16:49:42] [PASSED] check_used
[16:49:42] [PASSED] check_quota
[16:49:42] [PASSED] check_all
[16:49:42] ===================== [PASSED] guc_idm =====================
[16:49:42] ================== no_relay (3 subtests) ===================
[16:49:42] [PASSED] xe_drops_guc2pf_if_not_ready
[16:49:42] [PASSED] xe_drops_guc2vf_if_not_ready
[16:49:42] [PASSED] xe_rejects_send_if_not_ready
[16:49:42] ==================== [PASSED] no_relay =====================
[16:49:42] ================== pf_relay (14 subtests) ==================
[16:49:42] [PASSED] pf_rejects_guc2pf_too_short
[16:49:42] [PASSED] pf_rejects_guc2pf_too_long
[16:49:42] [PASSED] pf_rejects_guc2pf_no_payload
[16:49:42] [PASSED] pf_fails_no_payload
[16:49:42] [PASSED] pf_fails_bad_origin
[16:49:42] [PASSED] pf_fails_bad_type
[16:49:42] [PASSED] pf_txn_reports_error
[16:49:42] [PASSED] pf_txn_sends_pf2guc
[16:49:42] [PASSED] pf_sends_pf2guc
[16:49:42] [SKIPPED] pf_loopback_nop
[16:49:42] [SKIPPED] pf_loopback_echo
[16:49:42] [SKIPPED] pf_loopback_fail
[16:49:42] [SKIPPED] pf_loopback_busy
[16:49:42] [SKIPPED] pf_loopback_retry
[16:49:42] ==================== [PASSED] pf_relay =====================
[16:49:42] ================== vf_relay (3 subtests) ===================
[16:49:42] [PASSED] vf_rejects_guc2vf_too_short
[16:49:42] [PASSED] vf_rejects_guc2vf_too_long
[16:49:42] [PASSED] vf_rejects_guc2vf_no_payload
[16:49:42] ==================== [PASSED] vf_relay =====================
[16:49:42] ===================== lmtt (1 subtest) =====================
[16:49:42] ======================== test_ops  =========================
[16:49:42] [PASSED] 2-level
[16:49:42] [PASSED] multi-level
[16:49:42] ==================== [PASSED] test_ops =====================
[16:49:42] ====================== [PASSED] lmtt =======================
[16:49:42] ================= pf_service (11 subtests) =================
[16:49:42] [PASSED] pf_negotiate_any
[16:49:42] [PASSED] pf_negotiate_base_match
[16:49:42] [PASSED] pf_negotiate_base_newer
[16:49:42] [PASSED] pf_negotiate_base_next
[16:49:42] [SKIPPED] pf_negotiate_base_older
[16:49:42] [PASSED] pf_negotiate_base_prev
[16:49:42] [PASSED] pf_negotiate_latest_match
[16:49:42] [PASSED] pf_negotiate_latest_newer
[16:49:42] [PASSED] pf_negotiate_latest_next
[16:49:42] [SKIPPED] pf_negotiate_latest_older
[16:49:42] [SKIPPED] pf_negotiate_latest_prev
[16:49:42] =================== [PASSED] pf_service ====================
[16:49:42] =================== xe_mocs (2 subtests) ===================
[16:49:42] ================ xe_live_mocs_kernel_kunit  ================
[16:49:42] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[16:49:42] ================ xe_live_mocs_reset_kunit  =================
[16:49:42] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[16:49:42] ==================== [SKIPPED] xe_mocs =====================
[16:49:42] ================= xe_migrate (2 subtests) ==================
[16:49:42] ================= xe_migrate_sanity_kunit  =================
[16:49:42] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[16:49:42] ================== xe_validate_ccs_kunit  ==================
[16:49:42] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[16:49:42] =================== [SKIPPED] xe_migrate ===================
[16:49:42] ================== xe_dma_buf (1 subtest) ==================
[16:49:42] ==================== xe_dma_buf_kunit  =====================
[16:49:42] ================ [SKIPPED] xe_dma_buf_kunit ================
[16:49:42] =================== [SKIPPED] xe_dma_buf ===================
[16:49:42] ================= xe_bo_shrink (1 subtest) =================
[16:49:42] =================== xe_bo_shrink_kunit  ====================
[16:49:42] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[16:49:42] ================== [SKIPPED] xe_bo_shrink ==================
[16:49:42] ==================== xe_bo (2 subtests) ====================
[16:49:42] ================== xe_ccs_migrate_kunit  ===================
[16:49:42] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[16:49:42] ==================== xe_bo_evict_kunit  ====================
[16:49:42] =============== [SKIPPED] xe_bo_evict_kunit ================
[16:49:42] ===================== [SKIPPED] xe_bo ======================
[16:49:42] ==================== args (11 subtests) ====================
[16:49:42] [PASSED] count_args_test
[16:49:42] [PASSED] call_args_example
[16:49:42] [PASSED] call_args_test
[16:49:42] [PASSED] drop_first_arg_example
[16:49:42] [PASSED] drop_first_arg_test
[16:49:42] [PASSED] first_arg_example
[16:49:42] [PASSED] first_arg_test
[16:49:42] [PASSED] last_arg_example
[16:49:42] [PASSED] last_arg_test
[16:49:42] [PASSED] pick_arg_example
[16:49:42] [PASSED] sep_comma_example
[16:49:42] ====================== [PASSED] args =======================
[16:49:42] =================== xe_pci (3 subtests) ====================
[16:49:42] ==================== check_graphics_ip  ====================
[16:49:42] [PASSED] 12.70 Xe_LPG
[16:49:42] [PASSED] 12.71 Xe_LPG
[16:49:42] [PASSED] 12.74 Xe_LPG+
[16:49:42] [PASSED] 20.01 Xe2_HPG
[16:49:42] [PASSED] 20.02 Xe2_HPG
[16:49:42] [PASSED] 20.04 Xe2_LPG
[16:49:42] [PASSED] 30.00 Xe3_LPG
[16:49:42] [PASSED] 30.01 Xe3_LPG
[16:49:42] [PASSED] 30.03 Xe3_LPG
[16:49:42] ================ [PASSED] check_graphics_ip ================
[16:49:42] ===================== check_media_ip  ======================
[16:49:42] [PASSED] 13.00 Xe_LPM+
[16:49:42] [PASSED] 13.01 Xe2_HPM
[16:49:42] [PASSED] 20.00 Xe2_LPM
[16:49:42] [PASSED] 30.00 Xe3_LPM
[16:49:42] [PASSED] 30.02 Xe3_LPM
[16:49:42] ================= [PASSED] check_media_ip ==================
[16:49:42] ================= check_platform_gt_count  =================
[16:49:42] [PASSED] 0x9A60 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A68 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A70 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A40 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A49 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A59 (TIGERLAKE)
[16:49:42] [PASSED] 0x9A78 (TIGERLAKE)
[16:49:42] [PASSED] 0x9AC0 (TIGERLAKE)
[16:49:42] [PASSED] 0x9AC9 (TIGERLAKE)
[16:49:42] [PASSED] 0x9AD9 (TIGERLAKE)
[16:49:42] [PASSED] 0x9AF8 (TIGERLAKE)
[16:49:42] [PASSED] 0x4C80 (ROCKETLAKE)
[16:49:42] [PASSED] 0x4C8A (ROCKETLAKE)
[16:49:42] [PASSED] 0x4C8B (ROCKETLAKE)
[16:49:42] [PASSED] 0x4C8C (ROCKETLAKE)
[16:49:42] [PASSED] 0x4C90 (ROCKETLAKE)
[16:49:42] [PASSED] 0x4C9A (ROCKETLAKE)
[16:49:42] [PASSED] 0x4680 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4682 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4688 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x468A (ALDERLAKE_S)
[16:49:42] [PASSED] 0x468B (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4690 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4692 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4693 (ALDERLAKE_S)
[16:49:42] [PASSED] 0x46A0 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46A1 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46A2 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46A3 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46A6 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46A8 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46AA (ALDERLAKE_P)
[16:49:42] [PASSED] 0x462A (ALDERLAKE_P)
[16:49:42] [PASSED] 0x4626 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x4628 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46B0 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46B1 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46B2 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46B3 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46C0 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46C1 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46C2 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46C3 (ALDERLAKE_P)
[16:49:42] [PASSED] 0x46D0 (ALDERLAKE_N)
[16:49:42] [PASSED] 0x46D1 (ALDERLAKE_N)
[16:49:42] [PASSED] 0x46D2 (ALDERLAKE_N)
[16:49:42] [PASSED] 0x46D3 (ALDERLAKE_N)
[16:49:42] [PASSED] 0x46D4 (ALDERLAKE_N)
[16:49:42] [PASSED] 0xA721 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7A1 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7A9 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7AC (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7AD (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA720 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7A0 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7A8 (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7AA (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA7AB (ALDERLAKE_P)
[16:49:42] [PASSED] 0xA780 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA781 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA782 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA783 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA788 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA789 (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA78A (ALDERLAKE_S)
[16:49:42] [PASSED] 0xA78B (ALDERLAKE_S)
[16:49:42] [PASSED] 0x4905 (DG1)
[16:49:42] [PASSED] 0x4906 (DG1)
[16:49:42] [PASSED] 0x4907 (DG1)
[16:49:42] [PASSED] 0x4908 (DG1)
[16:49:42] [PASSED] 0x4909 (DG1)
[16:49:42] [PASSED] 0x56C0 (DG2)
[16:49:42] [PASSED] 0x56C2 (DG2)
[16:49:42] [PASSED] 0x56C1 (DG2)
[16:49:42] [PASSED] 0x7D51 (METEORLAKE)
[16:49:42] [PASSED] 0x7DD1 (METEORLAKE)
[16:49:42] [PASSED] 0x7D41 (METEORLAKE)
[16:49:42] [PASSED] 0x7D67 (METEORLAKE)
[16:49:42] [PASSED] 0xB640 (METEORLAKE)
[16:49:42] [PASSED] 0x56A0 (DG2)
[16:49:42] [PASSED] 0x56A1 (DG2)
[16:49:42] [PASSED] 0x56A2 (DG2)
[16:49:42] [PASSED] 0x56BE (DG2)
[16:49:42] [PASSED] 0x56BF (DG2)
[16:49:42] [PASSED] 0x5690 (DG2)
[16:49:42] [PASSED] 0x5691 (DG2)
[16:49:42] [PASSED] 0x5692 (DG2)
[16:49:42] [PASSED] 0x56A5 (DG2)
[16:49:42] [PASSED] 0x56A6 (DG2)
[16:49:42] [PASSED] 0x56B0 (DG2)
[16:49:42] [PASSED] 0x56B1 (DG2)
[16:49:42] [PASSED] 0x56BA (DG2)
[16:49:42] [PASSED] 0x56BB (DG2)
[16:49:42] [PASSED] 0x56BC (DG2)
[16:49:42] [PASSED] 0x56BD (DG2)
[16:49:42] [PASSED] 0x5693 (DG2)
[16:49:42] [PASSED] 0x5694 (DG2)
[16:49:42] [PASSED] 0x5695 (DG2)
[16:49:42] [PASSED] 0x56A3 (DG2)
[16:49:42] [PASSED] 0x56A4 (DG2)
[16:49:42] [PASSED] 0x56B2 (DG2)
[16:49:42] [PASSED] 0x56B3 (DG2)
[16:49:42] [PASSED] 0x5696 (DG2)
[16:49:42] [PASSED] 0x5697 (DG2)
[16:49:42] [PASSED] 0xB69 (PVC)
[16:49:42] [PASSED] 0xB6E (PVC)
[16:49:42] [PASSED] 0xBD4 (PVC)
[16:49:42] [PASSED] 0xBD5 (PVC)
[16:49:42] [PASSED] 0xBD6 (PVC)
[16:49:42] [PASSED] 0xBD7 (PVC)
[16:49:42] [PASSED] 0xBD8 (PVC)
[16:49:42] [PASSED] 0xBD9 (PVC)
[16:49:42] [PASSED] 0xBDA (PVC)
[16:49:42] [PASSED] 0xBDB (PVC)
[16:49:42] [PASSED] 0xBE0 (PVC)
[16:49:42] [PASSED] 0xBE1 (PVC)
[16:49:42] [PASSED] 0xBE5 (PVC)
[16:49:42] [PASSED] 0x7D40 (METEORLAKE)
[16:49:42] [PASSED] 0x7D45 (METEORLAKE)
[16:49:42] [PASSED] 0x7D55 (METEORLAKE)
[16:49:42] [PASSED] 0x7D60 (METEORLAKE)
[16:49:42] [PASSED] 0x7DD5 (METEORLAKE)
[16:49:42] [PASSED] 0x6420 (LUNARLAKE)
[16:49:42] [PASSED] 0x64A0 (LUNARLAKE)
[16:49:42] [PASSED] 0x64B0 (LUNARLAKE)
[16:49:42] [PASSED] 0xE202 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE209 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE20B (BATTLEMAGE)
[16:49:42] [PASSED] 0xE20C (BATTLEMAGE)
[16:49:42] [PASSED] 0xE20D (BATTLEMAGE)
[16:49:42] [PASSED] 0xE210 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE211 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE212 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE216 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE220 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE221 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE222 (BATTLEMAGE)
[16:49:42] [PASSED] 0xE223 (BATTLEMAGE)
[16:49:42] [PASSED] 0xB080 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB081 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB082 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB083 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB084 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB085 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB086 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB087 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB08F (PANTHERLAKE)
[16:49:42] [PASSED] 0xB090 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB0A0 (PANTHERLAKE)
[16:49:42] [PASSED] 0xB0B0 (PANTHERLAKE)
[16:49:42] [PASSED] 0xFD80 (PANTHERLAKE)
[16:49:42] [PASSED] 0xFD81 (PANTHERLAKE)
[16:49:42] ============= [PASSED] check_platform_gt_count =============
[16:49:42] ===================== [PASSED] xe_pci ======================
[16:49:42] =================== xe_rtp (2 subtests) ====================
[16:49:42] =============== xe_rtp_process_to_sr_tests  ================
[16:49:42] [PASSED] coalesce-same-reg
[16:49:42] [PASSED] no-match-no-add
[16:49:42] [PASSED] match-or
[16:49:42] [PASSED] match-or-xfail
[16:49:42] [PASSED] no-match-no-add-multiple-rules
[16:49:42] [PASSED] two-regs-two-entries
[16:49:42] [PASSED] clr-one-set-other
[16:49:42] [PASSED] set-field
[16:49:42] [PASSED] conflict-duplicate
[16:49:42] [PASSED] conflict-not-disjoint
[16:49:42] [PASSED] conflict-reg-type
[16:49:42] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[16:49:42] ================== xe_rtp_process_tests  ===================
[16:49:42] [PASSED] active1
[16:49:42] [PASSED] active2
[16:49:42] [PASSED] active-inactive
[16:49:42] [PASSED] inactive-active
[16:49:42] [PASSED] inactive-1st_or_active-inactive
[16:49:42] [PASSED] inactive-2nd_or_active-inactive
[16:49:42] [PASSED] inactive-last_or_active-inactive
[16:49:42] [PASSED] inactive-no_or_active-inactive
[16:49:42] ============== [PASSED] xe_rtp_process_tests ===============
[16:49:42] ===================== [PASSED] xe_rtp ======================
[16:49:42] ==================== xe_wa (1 subtest) =====================
[16:49:42] ======================== xe_wa_gt  =========================
[16:49:42] [PASSED] TIGERLAKE (B0)
[16:49:42] [PASSED] DG1 (A0)
[16:49:42] [PASSED] DG1 (B0)
[16:49:42] [PASSED] ALDERLAKE_S (A0)
[16:49:42] [PASSED] ALDERLAKE_S (B0)
[16:49:42] [PASSED] ALDERLAKE_S (C0)
[16:49:42] [PASSED] ALDERLAKE_S (D0)
[16:49:42] [PASSED] ALDERLAKE_P (A0)
[16:49:42] [PASSED] ALDERLAKE_P (B0)
[16:49:42] [PASSED] ALDERLAKE_P (C0)
[16:49:42] [PASSED] ALDERLAKE_S_RPLS (D0)
[16:49:42] [PASSED] ALDERLAKE_P_RPLU (E0)
[16:49:42] [PASSED] DG2_G10 (C0)
[16:49:42] [PASSED] DG2_G11 (B1)
[16:49:42] [PASSED] DG2_G12 (A1)
[16:49:42] [PASSED] METEORLAKE (g:A0, m:A0)
[16:49:42] [PASSED] METEORLAKE (g:A0, m:A0)
[16:49:42] [PASSED] METEORLAKE (g:A0, m:A0)
[16:49:42] [PASSED] LUNARLAKE (g:A0, m:A0)
[16:49:42] [PASSED] LUNARLAKE (g:B0, m:A0)
stty: 'standard input': Inappropriate ioctl for device
[16:49:42] [PASSED] BATTLEMAGE (g:A0, m:A1)
[16:49:42] ==================== [PASSED] xe_wa_gt =====================
[16:49:42] ====================== [PASSED] xe_wa ======================
[16:49:42] ============================================================
[16:49:42] Testing complete. Ran 297 tests: passed: 281, skipped: 16
[16:49:42] Elapsed time: 49.463s total, 5.148s configuring, 43.898s building, 0.373s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[16:49:42] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:49:44] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:50:18] Starting KUnit Kernel (1/1)...
[16:50:18] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:50:18] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[16:50:18] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[16:50:18] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[16:50:18] =========== drm_validate_clone_mode (2 subtests) ===========
[16:50:18] ============== drm_test_check_in_clone_mode  ===============
[16:50:18] [PASSED] in_clone_mode
[16:50:18] [PASSED] not_in_clone_mode
[16:50:18] ========== [PASSED] drm_test_check_in_clone_mode ===========
[16:50:18] =============== drm_test_check_valid_clones  ===============
[16:50:18] [PASSED] not_in_clone_mode
[16:50:18] [PASSED] valid_clone
[16:50:18] [PASSED] invalid_clone
[16:50:18] =========== [PASSED] drm_test_check_valid_clones ===========
[16:50:18] ============= [PASSED] drm_validate_clone_mode =============
[16:50:18] ============= drm_validate_modeset (1 subtest) =============
[16:50:18] [PASSED] drm_test_check_connector_changed_modeset
[16:50:18] ============== [PASSED] drm_validate_modeset ===============
[16:50:18] ====== drm_test_bridge_get_current_state (2 subtests) ======
[16:50:18] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[16:50:18] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[16:50:18] ======== [PASSED] drm_test_bridge_get_current_state ========
[16:50:18] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[16:50:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[16:50:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[16:50:18] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[16:50:18] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[16:50:18] ============== drm_bridge_alloc (2 subtests) ===============
[16:50:18] [PASSED] drm_test_drm_bridge_alloc_basic
[16:50:18] [PASSED] drm_test_drm_bridge_alloc_get_put
[16:50:18] ================ [PASSED] drm_bridge_alloc =================
[16:50:18] ================== drm_buddy (7 subtests) ==================
[16:50:18] [PASSED] drm_test_buddy_alloc_limit
[16:50:18] [PASSED] drm_test_buddy_alloc_optimistic
[16:50:18] [PASSED] drm_test_buddy_alloc_pessimistic
[16:50:18] [PASSED] drm_test_buddy_alloc_pathological
[16:50:18] [PASSED] drm_test_buddy_alloc_contiguous
[16:50:18] [PASSED] drm_test_buddy_alloc_clear
[16:50:18] [PASSED] drm_test_buddy_alloc_range_bias
[16:50:18] ==================== [PASSED] drm_buddy ====================
[16:50:18] ============= drm_cmdline_parser (40 subtests) =============
[16:50:18] [PASSED] drm_test_cmdline_force_d_only
[16:50:18] [PASSED] drm_test_cmdline_force_D_only_dvi
[16:50:18] [PASSED] drm_test_cmdline_force_D_only_hdmi
[16:50:18] [PASSED] drm_test_cmdline_force_D_only_not_digital
[16:50:18] [PASSED] drm_test_cmdline_force_e_only
[16:50:18] [PASSED] drm_test_cmdline_res
[16:50:18] [PASSED] drm_test_cmdline_res_vesa
[16:50:18] [PASSED] drm_test_cmdline_res_vesa_rblank
[16:50:18] [PASSED] drm_test_cmdline_res_rblank
[16:50:18] [PASSED] drm_test_cmdline_res_bpp
[16:50:18] [PASSED] drm_test_cmdline_res_refresh
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[16:50:18] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[16:50:18] [PASSED] drm_test_cmdline_res_margins_force_on
[16:50:18] [PASSED] drm_test_cmdline_res_vesa_margins
[16:50:18] [PASSED] drm_test_cmdline_name
[16:50:18] [PASSED] drm_test_cmdline_name_bpp
[16:50:18] [PASSED] drm_test_cmdline_name_option
[16:50:18] [PASSED] drm_test_cmdline_name_bpp_option
[16:50:18] [PASSED] drm_test_cmdline_rotate_0
[16:50:18] [PASSED] drm_test_cmdline_rotate_90
[16:50:18] [PASSED] drm_test_cmdline_rotate_180
[16:50:18] [PASSED] drm_test_cmdline_rotate_270
[16:50:18] [PASSED] drm_test_cmdline_hmirror
[16:50:18] [PASSED] drm_test_cmdline_vmirror
[16:50:18] [PASSED] drm_test_cmdline_margin_options
[16:50:18] [PASSED] drm_test_cmdline_multiple_options
[16:50:18] [PASSED] drm_test_cmdline_bpp_extra_and_option
[16:50:18] [PASSED] drm_test_cmdline_extra_and_option
[16:50:18] [PASSED] drm_test_cmdline_freestanding_options
[16:50:18] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[16:50:18] [PASSED] drm_test_cmdline_panel_orientation
[16:50:18] ================ drm_test_cmdline_invalid  =================
[16:50:18] [PASSED] margin_only
[16:50:18] [PASSED] interlace_only
[16:50:18] [PASSED] res_missing_x
[16:50:18] [PASSED] res_missing_y
[16:50:18] [PASSED] res_bad_y
[16:50:18] [PASSED] res_missing_y_bpp
[16:50:18] [PASSED] res_bad_bpp
[16:50:18] [PASSED] res_bad_refresh
[16:50:18] [PASSED] res_bpp_refresh_force_on_off
[16:50:18] [PASSED] res_invalid_mode
[16:50:18] [PASSED] res_bpp_wrong_place_mode
[16:50:18] [PASSED] name_bpp_refresh
[16:50:18] [PASSED] name_refresh
[16:50:18] [PASSED] name_refresh_wrong_mode
[16:50:18] [PASSED] name_refresh_invalid_mode
[16:50:18] [PASSED] rotate_multiple
[16:50:18] [PASSED] rotate_invalid_val
[16:50:18] [PASSED] rotate_truncated
[16:50:18] [PASSED] invalid_option
[16:50:18] [PASSED] invalid_tv_option
[16:50:18] [PASSED] truncated_tv_option
[16:50:18] ============ [PASSED] drm_test_cmdline_invalid =============
[16:50:18] =============== drm_test_cmdline_tv_options  ===============
[16:50:18] [PASSED] NTSC
[16:50:18] [PASSED] NTSC_443
[16:50:18] [PASSED] NTSC_J
[16:50:18] [PASSED] PAL
[16:50:18] [PASSED] PAL_M
[16:50:18] [PASSED] PAL_N
[16:50:18] [PASSED] SECAM
[16:50:18] [PASSED] MONO_525
[16:50:18] [PASSED] MONO_625
[16:50:18] =========== [PASSED] drm_test_cmdline_tv_options ===========
[16:50:18] =============== [PASSED] drm_cmdline_parser ================
[16:50:18] ========== drmm_connector_hdmi_init (20 subtests) ==========
[16:50:18] [PASSED] drm_test_connector_hdmi_init_valid
[16:50:18] [PASSED] drm_test_connector_hdmi_init_bpc_8
[16:50:18] [PASSED] drm_test_connector_hdmi_init_bpc_10
[16:50:18] [PASSED] drm_test_connector_hdmi_init_bpc_12
[16:50:18] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[16:50:18] [PASSED] drm_test_connector_hdmi_init_bpc_null
[16:50:18] [PASSED] drm_test_connector_hdmi_init_formats_empty
[16:50:18] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[16:50:18] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[16:50:18] [PASSED] supported_formats=0x9 yuv420_allowed=1
[16:50:18] [PASSED] supported_formats=0x9 yuv420_allowed=0
[16:50:18] [PASSED] supported_formats=0x3 yuv420_allowed=1
[16:50:18] [PASSED] supported_formats=0x3 yuv420_allowed=0
[16:50:18] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[16:50:18] [PASSED] drm_test_connector_hdmi_init_null_ddc
[16:50:18] [PASSED] drm_test_connector_hdmi_init_null_product
[16:50:18] [PASSED] drm_test_connector_hdmi_init_null_vendor
[16:50:18] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[16:50:18] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[16:50:18] [PASSED] drm_test_connector_hdmi_init_product_valid
[16:50:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[16:50:18] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[16:50:18] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[16:50:18] ========= drm_test_connector_hdmi_init_type_valid  =========
[16:50:18] [PASSED] HDMI-A
[16:50:18] [PASSED] HDMI-B
[16:50:18] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[16:50:18] ======== drm_test_connector_hdmi_init_type_invalid  ========
[16:50:18] [PASSED] Unknown
[16:50:18] [PASSED] VGA
[16:50:18] [PASSED] DVI-I
[16:50:18] [PASSED] DVI-D
[16:50:18] [PASSED] DVI-A
[16:50:18] [PASSED] Composite
[16:50:18] [PASSED] SVIDEO
[16:50:18] [PASSED] LVDS
[16:50:18] [PASSED] Component
[16:50:18] [PASSED] DIN
[16:50:18] [PASSED] DP
[16:50:18] [PASSED] TV
[16:50:18] [PASSED] eDP
[16:50:18] [PASSED] Virtual
[16:50:18] [PASSED] DSI
[16:50:18] [PASSED] DPI
[16:50:18] [PASSED] Writeback
[16:50:18] [PASSED] SPI
[16:50:18] [PASSED] USB
[16:50:18] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[16:50:18] ============ [PASSED] drmm_connector_hdmi_init =============
[16:50:18] ============= drmm_connector_init (3 subtests) =============
[16:50:18] [PASSED] drm_test_drmm_connector_init
[16:50:18] [PASSED] drm_test_drmm_connector_init_null_ddc
[16:50:18] ========= drm_test_drmm_connector_init_type_valid  =========
[16:50:18] [PASSED] Unknown
[16:50:18] [PASSED] VGA
[16:50:18] [PASSED] DVI-I
[16:50:18] [PASSED] DVI-D
[16:50:18] [PASSED] DVI-A
[16:50:18] [PASSED] Composite
[16:50:18] [PASSED] SVIDEO
[16:50:18] [PASSED] LVDS
[16:50:18] [PASSED] Component
[16:50:18] [PASSED] DIN
[16:50:18] [PASSED] DP
[16:50:18] [PASSED] HDMI-A
[16:50:18] [PASSED] HDMI-B
[16:50:18] [PASSED] TV
[16:50:18] [PASSED] eDP
[16:50:18] [PASSED] Virtual
[16:50:18] [PASSED] DSI
[16:50:18] [PASSED] DPI
[16:50:18] [PASSED] Writeback
[16:50:18] [PASSED] SPI
[16:50:18] [PASSED] USB
[16:50:18] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[16:50:18] =============== [PASSED] drmm_connector_init ===============
[16:50:18] ========= drm_connector_dynamic_init (6 subtests) ==========
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_init
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_init_properties
[16:50:18] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[16:50:18] [PASSED] Unknown
[16:50:18] [PASSED] VGA
[16:50:18] [PASSED] DVI-I
[16:50:18] [PASSED] DVI-D
[16:50:18] [PASSED] DVI-A
[16:50:18] [PASSED] Composite
[16:50:18] [PASSED] SVIDEO
[16:50:18] [PASSED] LVDS
[16:50:18] [PASSED] Component
[16:50:18] [PASSED] DIN
[16:50:18] [PASSED] DP
[16:50:18] [PASSED] HDMI-A
[16:50:18] [PASSED] HDMI-B
[16:50:18] [PASSED] TV
[16:50:18] [PASSED] eDP
[16:50:18] [PASSED] Virtual
[16:50:18] [PASSED] DSI
[16:50:18] [PASSED] DPI
[16:50:18] [PASSED] Writeback
[16:50:18] [PASSED] SPI
[16:50:18] [PASSED] USB
[16:50:18] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[16:50:18] ======== drm_test_drm_connector_dynamic_init_name  =========
[16:50:18] [PASSED] Unknown
[16:50:18] [PASSED] VGA
[16:50:18] [PASSED] DVI-I
[16:50:18] [PASSED] DVI-D
[16:50:18] [PASSED] DVI-A
[16:50:18] [PASSED] Composite
[16:50:18] [PASSED] SVIDEO
[16:50:18] [PASSED] LVDS
[16:50:18] [PASSED] Component
[16:50:18] [PASSED] DIN
[16:50:18] [PASSED] DP
[16:50:18] [PASSED] HDMI-A
[16:50:18] [PASSED] HDMI-B
[16:50:18] [PASSED] TV
[16:50:18] [PASSED] eDP
[16:50:18] [PASSED] Virtual
[16:50:18] [PASSED] DSI
[16:50:18] [PASSED] DPI
[16:50:18] [PASSED] Writeback
[16:50:18] [PASSED] SPI
[16:50:18] [PASSED] USB
[16:50:18] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[16:50:18] =========== [PASSED] drm_connector_dynamic_init ============
[16:50:18] ==== drm_connector_dynamic_register_early (4 subtests) =====
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[16:50:18] ====== [PASSED] drm_connector_dynamic_register_early =======
[16:50:18] ======= drm_connector_dynamic_register (7 subtests) ========
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[16:50:18] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[16:50:18] ========= [PASSED] drm_connector_dynamic_register ==========
[16:50:18] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[16:50:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[16:50:18] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[16:50:18] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[16:50:18] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[16:50:18] ========== drm_test_get_tv_mode_from_name_valid  ===========
[16:50:18] [PASSED] NTSC
[16:50:18] [PASSED] NTSC-443
[16:50:18] [PASSED] NTSC-J
[16:50:18] [PASSED] PAL
[16:50:18] [PASSED] PAL-M
[16:50:18] [PASSED] PAL-N
[16:50:18] [PASSED] SECAM
[16:50:18] [PASSED] Mono
[16:50:18] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[16:50:18] [PASSED] drm_test_get_tv_mode_from_name_truncated
[16:50:18] ============ [PASSED] drm_get_tv_mode_from_name ============
[16:50:18] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[16:50:18] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[16:50:18] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[16:50:18] [PASSED] VIC 96
[16:50:18] [PASSED] VIC 97
[16:50:18] [PASSED] VIC 101
[16:50:18] [PASSED] VIC 102
[16:50:18] [PASSED] VIC 106
[16:50:18] [PASSED] VIC 107
[16:50:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[16:50:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[16:50:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[16:50:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[16:50:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[16:50:18] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[16:50:18] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[16:50:18] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[16:50:18] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[16:50:18] [PASSED] Automatic
[16:50:18] [PASSED] Full
[16:50:18] [PASSED] Limited 16:235
[16:50:18] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[16:50:18] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[16:50:18] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[16:50:18] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[16:50:18] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[16:50:18] [PASSED] RGB
[16:50:18] [PASSED] YUV 4:2:0
[16:50:18] [PASSED] YUV 4:2:2
[16:50:18] [PASSED] YUV 4:4:4
[16:50:18] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[16:50:18] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[16:50:18] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[16:50:18] ============= drm_damage_helper (21 subtests) ==============
[16:50:18] [PASSED] drm_test_damage_iter_no_damage
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_src_moved
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_not_visible
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[16:50:18] [PASSED] drm_test_damage_iter_no_damage_no_fb
[16:50:18] [PASSED] drm_test_damage_iter_simple_damage
[16:50:18] [PASSED] drm_test_damage_iter_single_damage
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_outside_src
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_src_moved
[16:50:18] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[16:50:18] [PASSED] drm_test_damage_iter_damage
[16:50:18] [PASSED] drm_test_damage_iter_damage_one_intersect
[16:50:18] [PASSED] drm_test_damage_iter_damage_one_outside
[16:50:18] [PASSED] drm_test_damage_iter_damage_src_moved
[16:50:18] [PASSED] drm_test_damage_iter_damage_not_visible
[16:50:18] ================ [PASSED] drm_damage_helper ================
[16:50:18] ============== drm_dp_mst_helper (3 subtests) ==============
[16:50:18] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[16:50:18] [PASSED] Clock 154000 BPP 30 DSC disabled
[16:50:18] [PASSED] Clock 234000 BPP 30 DSC disabled
[16:50:18] [PASSED] Clock 297000 BPP 24 DSC disabled
[16:50:18] [PASSED] Clock 332880 BPP 24 DSC enabled
[16:50:18] [PASSED] Clock 324540 BPP 24 DSC enabled
[16:50:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[16:50:18] ============== drm_test_dp_mst_calc_pbn_div  ===============
[16:50:18] [PASSED] Link rate 2000000 lane count 4
[16:50:18] [PASSED] Link rate 2000000 lane count 2
[16:50:18] [PASSED] Link rate 2000000 lane count 1
[16:50:18] [PASSED] Link rate 1350000 lane count 4
[16:50:18] [PASSED] Link rate 1350000 lane count 2
[16:50:18] [PASSED] Link rate 1350000 lane count 1
[16:50:18] [PASSED] Link rate 1000000 lane count 4
[16:50:18] [PASSED] Link rate 1000000 lane count 2
[16:50:18] [PASSED] Link rate 1000000 lane count 1
[16:50:18] [PASSED] Link rate 810000 lane count 4
[16:50:18] [PASSED] Link rate 810000 lane count 2
[16:50:18] [PASSED] Link rate 810000 lane count 1
[16:50:18] [PASSED] Link rate 540000 lane count 4
[16:50:18] [PASSED] Link rate 540000 lane count 2
[16:50:18] [PASSED] Link rate 540000 lane count 1
[16:50:18] [PASSED] Link rate 270000 lane count 4
[16:50:18] [PASSED] Link rate 270000 lane count 2
[16:50:18] [PASSED] Link rate 270000 lane count 1
[16:50:18] [PASSED] Link rate 162000 lane count 4
[16:50:18] [PASSED] Link rate 162000 lane count 2
[16:50:18] [PASSED] Link rate 162000 lane count 1
[16:50:18] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[16:50:18] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[16:50:18] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[16:50:18] [PASSED] DP_POWER_UP_PHY with port number
[16:50:18] [PASSED] DP_POWER_DOWN_PHY with port number
[16:50:18] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[16:50:18] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[16:50:18] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[16:50:18] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[16:50:18] [PASSED] DP_QUERY_PAYLOAD with port number
[16:50:18] [PASSED] DP_QUERY_PAYLOAD with VCPI
[16:50:18] [PASSED] DP_REMOTE_DPCD_READ with port number
[16:50:18] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[16:50:18] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[16:50:18] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[16:50:18] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[16:50:18] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[16:50:18] [PASSED] DP_REMOTE_I2C_READ with port number
[16:50:18] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[16:50:18] [PASSED] DP_REMOTE_I2C_READ with transactions array
[16:50:18] [PASSED] DP_REMOTE_I2C_WRITE with port number
[16:50:18] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[16:50:18] [PASSED] DP_REMOTE_I2C_WRITE with data array
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[16:50:18] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[16:50:18] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[16:50:18] ================ [PASSED] drm_dp_mst_helper ================
[16:50:18] ================== drm_exec (7 subtests) ===================
[16:50:18] [PASSED] sanitycheck
[16:50:18] [PASSED] test_lock
[16:50:18] [PASSED] test_lock_unlock
[16:50:18] [PASSED] test_duplicates
[16:50:18] [PASSED] test_prepare
[16:50:18] [PASSED] test_prepare_array
[16:50:18] [PASSED] test_multiple_loops
[16:50:18] ==================== [PASSED] drm_exec =====================
[16:50:18] =========== drm_format_helper_test (17 subtests) ===========
[16:50:18] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[16:50:18] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[16:50:18] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[16:50:18] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[16:50:18] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[16:50:18] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[16:50:18] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[16:50:18] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[16:50:18] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[16:50:18] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[16:50:18] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[16:50:18] ============== drm_test_fb_xrgb8888_to_mono  ===============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[16:50:18] ==================== drm_test_fb_swab  =====================
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ================ [PASSED] drm_test_fb_swab =================
[16:50:18] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[16:50:18] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[16:50:18] [PASSED] single_pixel_source_buffer
[16:50:18] [PASSED] single_pixel_clip_rectangle
[16:50:18] [PASSED] well_known_colors
[16:50:18] [PASSED] destination_pitch
[16:50:18] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[16:50:18] ================= drm_test_fb_clip_offset  =================
[16:50:18] [PASSED] pass through
[16:50:18] [PASSED] horizontal offset
[16:50:18] [PASSED] vertical offset
[16:50:18] [PASSED] horizontal and vertical offset
[16:50:18] [PASSED] horizontal offset (custom pitch)
[16:50:18] [PASSED] vertical offset (custom pitch)
[16:50:18] [PASSED] horizontal and vertical offset (custom pitch)
[16:50:18] ============= [PASSED] drm_test_fb_clip_offset =============
[16:50:18] =================== drm_test_fb_memcpy  ====================
[16:50:18] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[16:50:18] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[16:50:18] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[16:50:18] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[16:50:18] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[16:50:18] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[16:50:18] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[16:50:18] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[16:50:18] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[16:50:18] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[16:50:18] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[16:50:18] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[16:50:18] =============== [PASSED] drm_test_fb_memcpy ================
[16:50:18] ============= [PASSED] drm_format_helper_test ==============
[16:50:18] ================= drm_format (18 subtests) =================
[16:50:18] [PASSED] drm_test_format_block_width_invalid
[16:50:18] [PASSED] drm_test_format_block_width_one_plane
[16:50:18] [PASSED] drm_test_format_block_width_two_plane
[16:50:18] [PASSED] drm_test_format_block_width_three_plane
[16:50:18] [PASSED] drm_test_format_block_width_tiled
[16:50:18] [PASSED] drm_test_format_block_height_invalid
[16:50:18] [PASSED] drm_test_format_block_height_one_plane
[16:50:18] [PASSED] drm_test_format_block_height_two_plane
[16:50:18] [PASSED] drm_test_format_block_height_three_plane
[16:50:18] [PASSED] drm_test_format_block_height_tiled
[16:50:18] [PASSED] drm_test_format_min_pitch_invalid
[16:50:18] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[16:50:18] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[16:50:18] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[16:50:18] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[16:50:18] [PASSED] drm_test_format_min_pitch_two_plane
[16:50:18] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[16:50:18] [PASSED] drm_test_format_min_pitch_tiled
[16:50:18] =================== [PASSED] drm_format ====================
[16:50:18] ============== drm_framebuffer (10 subtests) ===============
[16:50:18] ========== drm_test_framebuffer_check_src_coords  ==========
[16:50:18] [PASSED] Success: source fits into fb
[16:50:18] [PASSED] Fail: overflowing fb with x-axis coordinate
[16:50:18] [PASSED] Fail: overflowing fb with y-axis coordinate
[16:50:18] [PASSED] Fail: overflowing fb with source width
[16:50:18] [PASSED] Fail: overflowing fb with source height
[16:50:18] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[16:50:18] [PASSED] drm_test_framebuffer_cleanup
[16:50:18] =============== drm_test_framebuffer_create  ===============
[16:50:18] [PASSED] ABGR8888 normal sizes
[16:50:18] [PASSED] ABGR8888 max sizes
[16:50:18] [PASSED] ABGR8888 pitch greater than min required
[16:50:18] [PASSED] ABGR8888 pitch less than min required
[16:50:18] [PASSED] ABGR8888 Invalid width
[16:50:18] [PASSED] ABGR8888 Invalid buffer handle
[16:50:18] [PASSED] No pixel format
[16:50:18] [PASSED] ABGR8888 Width 0
[16:50:18] [PASSED] ABGR8888 Height 0
[16:50:18] [PASSED] ABGR8888 Out of bound height * pitch combination
[16:50:18] [PASSED] ABGR8888 Large buffer offset
[16:50:18] [PASSED] ABGR8888 Buffer offset for inexistent plane
[16:50:18] [PASSED] ABGR8888 Invalid flag
[16:50:18] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[16:50:18] [PASSED] ABGR8888 Valid buffer modifier
[16:50:18] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[16:50:18] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] NV12 Normal sizes
[16:50:18] [PASSED] NV12 Max sizes
[16:50:18] [PASSED] NV12 Invalid pitch
[16:50:18] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[16:50:18] [PASSED] NV12 different  modifier per-plane
[16:50:18] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[16:50:18] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] NV12 Modifier for inexistent plane
[16:50:18] [PASSED] NV12 Handle for inexistent plane
[16:50:18] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[16:50:18] [PASSED] YVU420 Normal sizes
[16:50:18] [PASSED] YVU420 Max sizes
[16:50:18] [PASSED] YVU420 Invalid pitch
[16:50:18] [PASSED] YVU420 Different pitches
[16:50:18] [PASSED] YVU420 Different buffer offsets/pitches
[16:50:18] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[16:50:18] [PASSED] YVU420 Valid modifier
[16:50:18] [PASSED] YVU420 Different modifiers per plane
[16:50:18] [PASSED] YVU420 Modifier for inexistent plane
[16:50:18] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[16:50:18] [PASSED] X0L2 Normal sizes
[16:50:18] [PASSED] X0L2 Max sizes
[16:50:18] [PASSED] X0L2 Invalid pitch
[16:50:18] [PASSED] X0L2 Pitch greater than minimum required
[16:50:18] [PASSED] X0L2 Handle for inexistent plane
[16:50:18] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[16:50:18] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[16:50:18] [PASSED] X0L2 Valid modifier
[16:50:18] [PASSED] X0L2 Modifier for inexistent plane
[16:50:18] =========== [PASSED] drm_test_framebuffer_create ===========
[16:50:18] [PASSED] drm_test_framebuffer_free
[16:50:18] [PASSED] drm_test_framebuffer_init
[16:50:18] [PASSED] drm_test_framebuffer_init_bad_format
[16:50:18] [PASSED] drm_test_framebuffer_init_dev_mismatch
[16:50:18] [PASSED] drm_test_framebuffer_lookup
[16:50:18] [PASSED] drm_test_framebuffer_lookup_inexistent
[16:50:18] [PASSED] drm_test_framebuffer_modifiers_not_supported
[16:50:18] ================= [PASSED] drm_framebuffer =================
[16:50:18] ================ drm_gem_shmem (8 subtests) ================
[16:50:18] [PASSED] drm_gem_shmem_test_obj_create
[16:50:18] [PASSED] drm_gem_shmem_test_obj_create_private
[16:50:18] [PASSED] drm_gem_shmem_test_pin_pages
[16:50:18] [PASSED] drm_gem_shmem_test_vmap
[16:50:18] [PASSED] drm_gem_shmem_test_get_pages_sgt
[16:50:18] [PASSED] drm_gem_shmem_test_get_sg_table
[16:50:18] [PASSED] drm_gem_shmem_test_madvise
[16:50:18] [PASSED] drm_gem_shmem_test_purge
[16:50:18] ================== [PASSED] drm_gem_shmem ==================
[16:50:18] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[16:50:18] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[16:50:18] [PASSED] Automatic
[16:50:18] [PASSED] Full
[16:50:18] [PASSED] Limited 16:235
[16:50:18] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[16:50:18] [PASSED] drm_test_check_disable_connector
[16:50:18] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[16:50:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[16:50:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[16:50:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[16:50:18] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[16:50:18] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[16:50:18] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[16:50:18] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[16:50:18] [PASSED] drm_test_check_output_bpc_dvi
[16:50:18] [PASSED] drm_test_check_output_bpc_format_vic_1
[16:50:18] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[16:50:18] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[16:50:18] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[16:50:18] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[16:50:18] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[16:50:18] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[16:50:18] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[16:50:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[16:50:18] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[16:50:18] [PASSED] drm_test_check_broadcast_rgb_value
[16:50:18] [PASSED] drm_test_check_bpc_8_value
[16:50:18] [PASSED] drm_test_check_bpc_10_value
[16:50:18] [PASSED] drm_test_check_bpc_12_value
[16:50:18] [PASSED] drm_test_check_format_value
[16:50:18] [PASSED] drm_test_check_tmds_char_value
[16:50:18] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[16:50:18] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[16:50:18] [PASSED] drm_test_check_mode_valid
[16:50:18] [PASSED] drm_test_check_mode_valid_reject
[16:50:18] [PASSED] drm_test_check_mode_valid_reject_rate
[16:50:18] [PASSED] drm_test_check_mode_valid_reject_max_clock
[16:50:18] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[16:50:18] ================= drm_managed (2 subtests) =================
[16:50:18] [PASSED] drm_test_managed_release_action
[16:50:18] [PASSED] drm_test_managed_run_action
[16:50:18] =================== [PASSED] drm_managed ===================
[16:50:18] =================== drm_mm (6 subtests) ====================
[16:50:18] [PASSED] drm_test_mm_init
[16:50:18] [PASSED] drm_test_mm_debug
[16:50:18] [PASSED] drm_test_mm_align32
[16:50:18] [PASSED] drm_test_mm_align64
[16:50:18] [PASSED] drm_test_mm_lowest
[16:50:18] [PASSED] drm_test_mm_highest
[16:50:18] ===================== [PASSED] drm_mm ======================
[16:50:18] ============= drm_modes_analog_tv (5 subtests) =============
[16:50:18] [PASSED] drm_test_modes_analog_tv_mono_576i
[16:50:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[16:50:18] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[16:50:18] [PASSED] drm_test_modes_analog_tv_pal_576i
[16:50:18] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[16:50:18] =============== [PASSED] drm_modes_analog_tv ===============
[16:50:18] ============== drm_plane_helper (2 subtests) ===============
[16:50:18] =============== drm_test_check_plane_state  ================
[16:50:18] [PASSED] clipping_simple
[16:50:18] [PASSED] clipping_rotate_reflect
[16:50:18] [PASSED] positioning_simple
[16:50:18] [PASSED] upscaling
[16:50:18] [PASSED] downscaling
[16:50:18] [PASSED] rounding1
[16:50:18] [PASSED] rounding2
[16:50:18] [PASSED] rounding3
[16:50:18] [PASSED] rounding4
[16:50:18] =========== [PASSED] drm_test_check_plane_state ============
[16:50:18] =========== drm_test_check_invalid_plane_state  ============
[16:50:18] [PASSED] positioning_invalid
[16:50:18] [PASSED] upscaling_invalid
[16:50:18] [PASSED] downscaling_invalid
[16:50:18] ======= [PASSED] drm_test_check_invalid_plane_state ========
[16:50:18] ================ [PASSED] drm_plane_helper =================
[16:50:18] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[16:50:18] ====== drm_test_connector_helper_tv_get_modes_check  =======
[16:50:18] [PASSED] None
[16:50:18] [PASSED] PAL
[16:50:18] [PASSED] NTSC
[16:50:18] [PASSED] Both, NTSC Default
[16:50:18] [PASSED] Both, PAL Default
[16:50:18] [PASSED] Both, NTSC Default, with PAL on command-line
[16:50:18] [PASSED] Both, PAL Default, with NTSC on command-line
[16:50:18] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[16:50:18] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[16:50:18] ================== drm_rect (9 subtests) ===================
[16:50:18] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[16:50:18] [PASSED] drm_test_rect_clip_scaled_not_clipped
[16:50:18] [PASSED] drm_test_rect_clip_scaled_clipped
[16:50:18] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[16:50:18] ================= drm_test_rect_intersect  =================
[16:50:18] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[16:50:18] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[16:50:18] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[16:50:18] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[16:50:18] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[16:50:18] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[16:50:18] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[16:50:18] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[16:50:18] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[16:50:18] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[16:50:18] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[16:50:18] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[16:50:18] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[16:50:18] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[16:50:18] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[16:50:18] ============= [PASSED] drm_test_rect_intersect =============
[16:50:18] ================ drm_test_rect_calc_hscale  ================
[16:50:18] [PASSED] normal use
[16:50:18] [PASSED] out of max range
[16:50:18] [PASSED] out of min range
[16:50:18] [PASSED] zero dst
[16:50:18] [PASSED] negative src
[16:50:18] [PASSED] negative dst
[16:50:18] ============ [PASSED] drm_test_rect_calc_hscale ============
[16:50:18] ================ drm_test_rect_calc_vscale  ================
[16:50:18] [PASSED] normal use
[16:50:18] [PASSED] out of max range
[16:50:18] [PASSED] out of min range
[16:50:18] [PASSED] zero dst
[16:50:18] [PASSED] negative src
[16:50:18] [PASSED] negative dst
[16:50:18] ============ [PASSED] drm_test_rect_calc_vscale ============
[16:50:18] ================== drm_test_rect_rotate  ===================
[16:50:18] [PASSED] reflect-x
[16:50:18] [PASSED] reflect-y
[16:50:18] [PASSED] rotate-0
[16:50:18] [PASSED] rotate-90
[16:50:18] [PASSED] rotate-180
[16:50:18] [PASSED] rotate-270
stty: 'standard input': Inappropriate ioctl for device
[16:50:18] ============== [PASSED] drm_test_rect_rotate ===============
[16:50:18] ================ drm_test_rect_rotate_inv  =================
[16:50:18] [PASSED] reflect-x
[16:50:18] [PASSED] reflect-y
[16:50:18] [PASSED] rotate-0
[16:50:18] [PASSED] rotate-90
[16:50:18] [PASSED] rotate-180
[16:50:18] [PASSED] rotate-270
[16:50:18] ============ [PASSED] drm_test_rect_rotate_inv =============
[16:50:18] ==================== [PASSED] drm_rect =====================
[16:50:18] ============ drm_sysfb_modeset_test (1 subtest) ============
[16:50:18] ============ drm_test_sysfb_build_fourcc_list  =============
[16:50:18] [PASSED] no native formats
[16:50:18] [PASSED] XRGB8888 as native format
[16:50:18] [PASSED] remove duplicates
[16:50:18] [PASSED] convert alpha formats
[16:50:18] [PASSED] random formats
[16:50:18] ======== [PASSED] drm_test_sysfb_build_fourcc_list =========
[16:50:18] ============= [PASSED] drm_sysfb_modeset_test ==============
[16:50:18] ============================================================
[16:50:18] Testing complete. Ran 616 tests: passed: 616
[16:50:18] Elapsed time: 36.075s total, 1.983s configuring, 33.871s building, 0.170s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[16:50:18] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[16:50:20] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[16:50:30] Starting KUnit Kernel (1/1)...
[16:50:30] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[16:50:30] ================= ttm_device (5 subtests) ==================
[16:50:30] [PASSED] ttm_device_init_basic
[16:50:30] [PASSED] ttm_device_init_multiple
[16:50:30] [PASSED] ttm_device_fini_basic
[16:50:30] [PASSED] ttm_device_init_no_vma_man
[16:50:30] ================== ttm_device_init_pools  ==================
[16:50:30] [PASSED] No DMA allocations, no DMA32 required
[16:50:30] [PASSED] DMA allocations, DMA32 required
[16:50:30] [PASSED] No DMA allocations, DMA32 required
[16:50:30] [PASSED] DMA allocations, no DMA32 required
[16:50:30] ============== [PASSED] ttm_device_init_pools ==============
[16:50:30] =================== [PASSED] ttm_device ====================
[16:50:30] ================== ttm_pool (8 subtests) ===================
[16:50:30] ================== ttm_pool_alloc_basic  ===================
[16:50:30] [PASSED] One page
[16:50:30] [PASSED] More than one page
[16:50:30] [PASSED] Above the allocation limit
[16:50:30] [PASSED] One page, with coherent DMA mappings enabled
[16:50:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:50:30] ============== [PASSED] ttm_pool_alloc_basic ===============
[16:50:30] ============== ttm_pool_alloc_basic_dma_addr  ==============
[16:50:30] [PASSED] One page
[16:50:30] [PASSED] More than one page
[16:50:30] [PASSED] Above the allocation limit
[16:50:30] [PASSED] One page, with coherent DMA mappings enabled
[16:50:30] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[16:50:30] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[16:50:30] [PASSED] ttm_pool_alloc_order_caching_match
[16:50:30] [PASSED] ttm_pool_alloc_caching_mismatch
[16:50:30] [PASSED] ttm_pool_alloc_order_mismatch
[16:50:30] [PASSED] ttm_pool_free_dma_alloc
[16:50:30] [PASSED] ttm_pool_free_no_dma_alloc
[16:50:30] [PASSED] ttm_pool_fini_basic
[16:50:30] ==================== [PASSED] ttm_pool =====================
[16:50:30] ================ ttm_resource (8 subtests) =================
[16:50:30] ================= ttm_resource_init_basic  =================
[16:50:30] [PASSED] Init resource in TTM_PL_SYSTEM
[16:50:30] [PASSED] Init resource in TTM_PL_VRAM
[16:50:30] [PASSED] Init resource in a private placement
[16:50:30] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[16:50:30] ============= [PASSED] ttm_resource_init_basic =============
[16:50:30] [PASSED] ttm_resource_init_pinned
[16:50:30] [PASSED] ttm_resource_fini_basic
[16:50:30] [PASSED] ttm_resource_manager_init_basic
[16:50:30] [PASSED] ttm_resource_manager_usage_basic
[16:50:30] [PASSED] ttm_resource_manager_set_used_basic
[16:50:30] [PASSED] ttm_sys_man_alloc_basic
[16:50:30] [PASSED] ttm_sys_man_free_basic
[16:50:30] ================== [PASSED] ttm_resource ===================
[16:50:30] =================== ttm_tt (15 subtests) ===================
[16:50:30] ==================== ttm_tt_init_basic  ====================
[16:50:30] [PASSED] Page-aligned size
[16:50:30] [PASSED] Extra pages requested
[16:50:30] ================ [PASSED] ttm_tt_init_basic ================
[16:50:30] [PASSED] ttm_tt_init_misaligned
[16:50:30] [PASSED] ttm_tt_fini_basic
[16:50:30] [PASSED] ttm_tt_fini_sg
[16:50:30] [PASSED] ttm_tt_fini_shmem
[16:50:30] [PASSED] ttm_tt_create_basic
[16:50:30] [PASSED] ttm_tt_create_invalid_bo_type
[16:50:30] [PASSED] ttm_tt_create_ttm_exists
[16:50:30] [PASSED] ttm_tt_create_failed
[16:50:30] [PASSED] ttm_tt_destroy_basic
[16:50:30] [PASSED] ttm_tt_populate_null_ttm
[16:50:30] [PASSED] ttm_tt_populate_populated_ttm
[16:50:30] [PASSED] ttm_tt_unpopulate_basic
[16:50:30] [PASSED] ttm_tt_unpopulate_empty_ttm
[16:50:30] [PASSED] ttm_tt_swapin_basic
[16:50:30] ===================== [PASSED] ttm_tt ======================
[16:50:30] =================== ttm_bo (14 subtests) ===================
[16:50:30] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[16:50:30] [PASSED] Cannot be interrupted and sleeps
[16:50:30] [PASSED] Cannot be interrupted, locks straight away
[16:50:30] [PASSED] Can be interrupted, sleeps
[16:50:30] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[16:50:30] [PASSED] ttm_bo_reserve_locked_no_sleep
[16:50:30] [PASSED] ttm_bo_reserve_no_wait_ticket
[16:50:30] [PASSED] ttm_bo_reserve_double_resv
[16:50:30] [PASSED] ttm_bo_reserve_interrupted
[16:50:30] [PASSED] ttm_bo_reserve_deadlock
[16:50:30] [PASSED] ttm_bo_unreserve_basic
[16:50:30] [PASSED] ttm_bo_unreserve_pinned
[16:50:30] [PASSED] ttm_bo_unreserve_bulk
[16:50:30] [PASSED] ttm_bo_put_basic
[16:50:30] [PASSED] ttm_bo_put_shared_resv
[16:50:30] [PASSED] ttm_bo_pin_basic
[16:50:30] [PASSED] ttm_bo_pin_unpin_resource
[16:50:30] [PASSED] ttm_bo_multiple_pin_one_unpin
[16:50:30] ===================== [PASSED] ttm_bo ======================
[16:50:30] ============== ttm_bo_validate (21 subtests) ===============
[16:50:30] ============== ttm_bo_init_reserved_sys_man  ===============
[16:50:30] [PASSED] Buffer object for userspace
[16:50:30] [PASSED] Kernel buffer object
[16:50:30] [PASSED] Shared buffer object
[16:50:30] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[16:50:30] ============== ttm_bo_init_reserved_mock_man  ==============
[16:50:30] [PASSED] Buffer object for userspace
[16:50:30] [PASSED] Kernel buffer object
[16:50:30] [PASSED] Shared buffer object
[16:50:30] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[16:50:30] [PASSED] ttm_bo_init_reserved_resv
[16:50:30] ================== ttm_bo_validate_basic  ==================
[16:50:30] [PASSED] Buffer object for userspace
[16:50:30] [PASSED] Kernel buffer object
[16:50:30] [PASSED] Shared buffer object
[16:50:30] ============== [PASSED] ttm_bo_validate_basic ==============
[16:50:30] [PASSED] ttm_bo_validate_invalid_placement
[16:50:30] ============= ttm_bo_validate_same_placement  ==============
[16:50:30] [PASSED] System manager
[16:50:30] [PASSED] VRAM manager
[16:50:30] ========= [PASSED] ttm_bo_validate_same_placement ==========
[16:50:30] [PASSED] ttm_bo_validate_failed_alloc
[16:50:30] [PASSED] ttm_bo_validate_pinned
[16:50:30] [PASSED] ttm_bo_validate_busy_placement
[16:50:30] ================ ttm_bo_validate_multihop  =================
[16:50:30] [PASSED] Buffer object for userspace
[16:50:30] [PASSED] Kernel buffer object
[16:50:30] [PASSED] Shared buffer object
[16:50:30] ============ [PASSED] ttm_bo_validate_multihop =============
[16:50:30] ========== ttm_bo_validate_no_placement_signaled  ==========
[16:50:30] [PASSED] Buffer object in system domain, no page vector
[16:50:30] [PASSED] Buffer object in system domain with an existing page vector
[16:50:30] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[16:50:30] ======== ttm_bo_validate_no_placement_not_signaled  ========
[16:50:30] [PASSED] Buffer object for userspace
[16:50:30] [PASSED] Kernel buffer object
[16:50:30] [PASSED] Shared buffer object
[16:50:30] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[16:50:30] [PASSED] ttm_bo_validate_move_fence_signaled
[16:50:31] ========= ttm_bo_validate_move_fence_not_signaled  =========
[16:50:31] [PASSED] Waits for GPU
[16:50:31] [PASSED] Tries to lock straight away
[16:50:31] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[16:50:31] [PASSED] ttm_bo_validate_happy_evict
[16:50:31] [PASSED] ttm_bo_validate_all_pinned_evict
[16:50:31] [PASSED] ttm_bo_validate_allowed_only_evict
[16:50:31] [PASSED] ttm_bo_validate_deleted_evict
[16:50:31] [PASSED] ttm_bo_validate_busy_domain_evict
[16:50:31] [PASSED] ttm_bo_validate_evict_gutting
[16:50:31] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[16:50:31] ================= [PASSED] ttm_bo_validate =================
[16:50:31] ============================================================
[16:50:31] Testing complete. Ran 101 tests: passed: 101
[16:50:31] Elapsed time: 12.149s total, 2.049s configuring, 9.884s building, 0.199s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ CI.checksparse: warning for drm/i915/vbt: cleanups and new fields

[Patchwork]

== Series Details ==

Series: drm/i915/vbt: cleanups and new fields
URL   : https://patchwork.freedesktop.org/series/152780/
State : warning

== Summary ==

+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 008ca7d455ca7f73eeca04881640f7c43a994370
Sparse version: 0.6.4 (Ubuntu: 0.6.4-4ubuntu3)
Fast mode used, each commit won't be checked separately.
-
+drivers/gpu/drm/i915/display/intel_alpm.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_cdclk.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_ddi.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2019:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2032:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2032:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_display_types.h:2032:24: warning: unreplaced symbol '<noident>'
+drivers/gpu/drm/i915/display/intel_hdcp.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_hotplug.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_pps.c: note: in included file:
+drivers/gpu/drm/i915/display/intel_psr.c: note: in included file:

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✗ Xe.CI.Full: failure for drm/i915/vbt: cleanups and new fields

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 368 bytes --]

== Series Details ==

Series: drm/i915/vbt: cleanups and new fields
URL   : https://patchwork.freedesktop.org/series/152780/
State : failure

== Summary ==

ERROR: The runconfig 'xe-3526-4b12b7a6ba18862389249ee1194c65ac2e5bc962_FULL' does not exist in the database

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-152780v1/index.html

[-- Attachment #2: Type: text/html, Size: 933 bytes --]

RE: [PATCH 1/4] drm/i915/vbt: split up DSI VBT defs to a separate file

[Kandpal, Suraj]

> Subject: [PATCH 1/4] drm/i915/vbt: split up DSI VBT defs to a separate file
> 
> The DSI VBT definitions have ended up in intel_bios.h, because intel_vbt_defs.h
> is supposed to be internal to intel_bios.c, but the DSI VBT definitions are
> needed in more places.
> 
> Split out the DSI VBT definitions to intel_dsi_vbt_defs.h. This will also help keep
> the definitions in sync with IGT.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_bios.h     | 174 -----------------
>  .../drm/i915/display/intel_display_types.h    |   1 +
>  .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 183 ++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
>  4 files changed, 185 insertions(+), 175 deletions(-)  create mode 100644
> drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
> b/drivers/gpu/drm/i915/display/intel_bios.h
> index 6cd7a011b8c4..8fdde85f7939 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.h
> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
> @@ -50,180 +50,6 @@ enum intel_backlight_type {
>  	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
>  };
> 
> -/*
> - * MIPI Sequence Block definitions
> - *
> - * Note the VBT spec has AssertReset / DeassertReset swapped from their
> - * usual naming, we use the proper names here to avoid confusion when
> - * reading the code.
> - */
> -enum mipi_seq {
> -	MIPI_SEQ_END = 0,
> -	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
> -	MIPI_SEQ_INIT_OTP,
> -	MIPI_SEQ_DISPLAY_ON,
> -	MIPI_SEQ_DISPLAY_OFF,
> -	MIPI_SEQ_ASSERT_RESET,		/* Spec says
> MipiDeassertResetPin */
> -	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
> -	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
> -	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
> -	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
> -	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
> -	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
> -	MIPI_SEQ_MAX
> -};
> -
> -enum mipi_seq_element {
> -	MIPI_SEQ_ELEM_END = 0,
> -	MIPI_SEQ_ELEM_SEND_PKT,
> -	MIPI_SEQ_ELEM_DELAY,
> -	MIPI_SEQ_ELEM_GPIO,
> -	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
> -	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
> -	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
> -	MIPI_SEQ_ELEM_MAX
> -};
> -
> -#define MIPI_DSI_UNDEFINED_PANEL_ID	0
> -#define MIPI_DSI_GENERIC_PANEL_ID	1
> -
> -struct mipi_config {
> -	u16 panel_id;
> -
> -	/* General Params */
> -	u32 enable_dithering:1;
> -	u32 rsvd1:1;
> -	u32 is_bridge:1;
> -
> -	u32 panel_arch_type:2;
> -	u32 is_cmd_mode:1;
> -
> -#define NON_BURST_SYNC_PULSE	0x1
> -#define NON_BURST_SYNC_EVENTS	0x2
> -#define BURST_MODE		0x3
> -	u32 video_transfer_mode:2;
> -
> -	u32 cabc_supported:1;
> -#define PPS_BLC_PMIC   0
> -#define PPS_BLC_SOC    1
> -	u32 pwm_blc:1;
> -
> -	/* Bit 13:10 */
> -#define PIXEL_FORMAT_RGB565			0x1
> -#define PIXEL_FORMAT_RGB666			0x2
> -#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
> -#define PIXEL_FORMAT_RGB888			0x4
> -	u32 videomode_color_format:4;
> -
> -	/* Bit 15:14 */
> -#define ENABLE_ROTATION_0	0x0
> -#define ENABLE_ROTATION_90	0x1
> -#define ENABLE_ROTATION_180	0x2
> -#define ENABLE_ROTATION_270	0x3
> -	u32 rotation:2;
> -	u32 bta_enabled:1;
> -	u32 rsvd2:15;
> -
> -	/* 2 byte Port Description */
> -#define DUAL_LINK_NOT_SUPPORTED	0
> -#define DUAL_LINK_FRONT_BACK	1
> -#define DUAL_LINK_PIXEL_ALT	2
> -	u16 dual_link:2;
> -	u16 lane_cnt:2;
> -	u16 pixel_overlap:3;
> -	u16 rgb_flip:1;
> -#define DL_DCS_PORT_A			0x00
> -#define DL_DCS_PORT_C			0x01
> -#define DL_DCS_PORT_A_AND_C		0x02
> -	u16 dl_dcs_cabc_ports:2;
> -	u16 dl_dcs_backlight_ports:2;
> -	u16 rsvd3:4;
> -
> -	u16 rsvd4;
> -
> -	u8 rsvd5;
> -	u32 target_burst_mode_freq;
> -	u32 dsi_ddr_clk;
> -	u32 bridge_ref_clk;
> -
> -#define  BYTE_CLK_SEL_20MHZ		0
> -#define  BYTE_CLK_SEL_10MHZ		1
> -#define  BYTE_CLK_SEL_5MHZ		2
> -	u8 byte_clk_sel:2;
> -
> -	u8 rsvd6:6;
> -
> -	/* DPHY Flags */
> -	u16 dphy_param_valid:1;
> -	u16 eot_pkt_disabled:1;
> -	u16 enable_clk_stop:1;
> -	u16 rsvd7:13;
> -
> -	u32 hs_tx_timeout;
> -	u32 lp_rx_timeout;
> -	u32 turn_around_timeout;
> -	u32 device_reset_timer;
> -	u32 master_init_timer;
> -	u32 dbi_bw_timer;
> -	u32 lp_byte_clk_val;
> -
> -	/*  4 byte Dphy Params */
> -	u32 prepare_cnt:6;
> -	u32 rsvd8:2;
> -	u32 clk_zero_cnt:8;
> -	u32 trail_cnt:5;
> -	u32 rsvd9:3;
> -	u32 exit_zero_cnt:6;
> -	u32 rsvd10:2;
> -
> -	u32 clk_lane_switch_cnt;
> -	u32 hl_switch_cnt;
> -
> -	u32 rsvd11[6];
> -
> -	/* timings based on dphy spec */
> -	u8 tclk_miss;
> -	u8 tclk_post;
> -	u8 rsvd12;
> -	u8 tclk_pre;
> -	u8 tclk_prepare;
> -	u8 tclk_settle;
> -	u8 tclk_term_enable;
> -	u8 tclk_trail;
> -	u16 tclk_prepare_clkzero;
> -	u8 rsvd13;
> -	u8 td_term_enable;
> -	u8 teot;
> -	u8 ths_exit;
> -	u8 ths_prepare;
> -	u16 ths_prepare_hszero;
> -	u8 rsvd14;
> -	u8 ths_settle;
> -	u8 ths_skip;
> -	u8 ths_trail;
> -	u8 tinit;
> -	u8 tlpx;
> -	u8 rsvd15[3];
> -
> -	/* GPIOs */
> -	u8 panel_enable;
> -	u8 bl_enable;
> -	u8 pwm_enable;
> -	u8 reset_r_n;
> -	u8 pwr_down_r;
> -	u8 stdby_r_n;
> -
> -} __packed;
> -
> -/* all delays have a unit of 100us */
> -struct mipi_pps_data {
> -	u16 panel_on_delay;
> -	u16 bl_enable_delay;
> -	u16 bl_disable_delay;
> -	u16 panel_off_delay;
> -	u16 panel_power_cycle_delay;
> -} __packed;
> -
>  void intel_bios_init(struct intel_display *display);  void
> intel_bios_init_panel_early(struct intel_display *display,
>  				 struct intel_panel *panel,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
> b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 35596f3921e8..0d945d1fedd6 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -50,6 +50,7 @@
>  #include "intel_display_limits.h"
>  #include "intel_display_power.h"
>  #include "intel_dpll_mgr.h"
> +#include "intel_dsi_vbt_defs.h"
>  #include "intel_wm_types.h"
> 
>  struct cec_notifier;
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> new file mode 100644
> index 000000000000..f83d42ed0c5a
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> @@ -0,0 +1,183 @@
> +/* SPDX-License-Identifier: MIT */
> +/* Copyright © 2025 Intel Corporation */
> +
> +#ifndef __INTEL_DSI_VBT_DEFS_H__
> +#define __INTEL_DSI_VBT_DEFS_H__
> +
> +#include <linux/types.h>
> +
> +/*
> + * MIPI Sequence Block definitions
> + *
> + * Note the VBT spec has AssertReset / DeassertReset swapped from their
> + * usual naming, we use the proper names here to avoid confusion when
> + * reading the code.
> + */
> +enum mipi_seq {
> +	MIPI_SEQ_END = 0,
> +	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
> +	MIPI_SEQ_INIT_OTP,
> +	MIPI_SEQ_DISPLAY_ON,
> +	MIPI_SEQ_DISPLAY_OFF,
> +	MIPI_SEQ_ASSERT_RESET,		/* Spec says
> MipiDeassertResetPin */
> +	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
> +	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
> +	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
> +	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
> +	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
> +	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
> +	MIPI_SEQ_MAX
> +};
> +
> +enum mipi_seq_element {
> +	MIPI_SEQ_ELEM_END = 0,
> +	MIPI_SEQ_ELEM_SEND_PKT,
> +	MIPI_SEQ_ELEM_DELAY,
> +	MIPI_SEQ_ELEM_GPIO,
> +	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
> +	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
> +	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
> +	MIPI_SEQ_ELEM_MAX
> +};
> +
> +#define MIPI_DSI_UNDEFINED_PANEL_ID	0
> +#define MIPI_DSI_GENERIC_PANEL_ID	1
> +
> +struct mipi_config {
> +	u16 panel_id;
> +
> +	/* General Params */
> +	u32 enable_dithering:1;
> +	u32 rsvd1:1;
> +	u32 is_bridge:1;
> +
> +	u32 panel_arch_type:2;
> +	u32 is_cmd_mode:1;
> +
> +#define NON_BURST_SYNC_PULSE	0x1
> +#define NON_BURST_SYNC_EVENTS	0x2
> +#define BURST_MODE		0x3
> +	u32 video_transfer_mode:2;
> +
> +	u32 cabc_supported:1;
> +#define PPS_BLC_PMIC   0
> +#define PPS_BLC_SOC    1
> +	u32 pwm_blc:1;
> +
> +	/* Bit 13:10 */
> +#define PIXEL_FORMAT_RGB565			0x1
> +#define PIXEL_FORMAT_RGB666			0x2
> +#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
> +#define PIXEL_FORMAT_RGB888			0x4
> +	u32 videomode_color_format:4;
> +
> +	/* Bit 15:14 */
> +#define ENABLE_ROTATION_0	0x0
> +#define ENABLE_ROTATION_90	0x1
> +#define ENABLE_ROTATION_180	0x2
> +#define ENABLE_ROTATION_270	0x3
> +	u32 rotation:2;
> +	u32 bta_enabled:1;
> +	u32 rsvd2:15;
> +
> +	/* 2 byte Port Description */
> +#define DUAL_LINK_NOT_SUPPORTED	0
> +#define DUAL_LINK_FRONT_BACK	1
> +#define DUAL_LINK_PIXEL_ALT	2
> +	u16 dual_link:2;
> +	u16 lane_cnt:2;
> +	u16 pixel_overlap:3;
> +	u16 rgb_flip:1;
> +#define DL_DCS_PORT_A			0x00
> +#define DL_DCS_PORT_C			0x01
> +#define DL_DCS_PORT_A_AND_C		0x02
> +	u16 dl_dcs_cabc_ports:2;
> +	u16 dl_dcs_backlight_ports:2;
> +	u16 rsvd3:4;
> +
> +	u16 rsvd4;
> +
> +	u8 rsvd5;
> +	u32 target_burst_mode_freq;
> +	u32 dsi_ddr_clk;
> +	u32 bridge_ref_clk;
> +
> +#define  BYTE_CLK_SEL_20MHZ		0
> +#define  BYTE_CLK_SEL_10MHZ		1
> +#define  BYTE_CLK_SEL_5MHZ		2
> +	u8 byte_clk_sel:2;
> +
> +	u8 rsvd6:6;
> +
> +	/* DPHY Flags */
> +	u16 dphy_param_valid:1;
> +	u16 eot_pkt_disabled:1;
> +	u16 enable_clk_stop:1;
> +	u16 rsvd7:13;
> +
> +	u32 hs_tx_timeout;
> +	u32 lp_rx_timeout;
> +	u32 turn_around_timeout;
> +	u32 device_reset_timer;
> +	u32 master_init_timer;
> +	u32 dbi_bw_timer;
> +	u32 lp_byte_clk_val;
> +
> +	/*  4 byte Dphy Params */
> +	u32 prepare_cnt:6;
> +	u32 rsvd8:2;
> +	u32 clk_zero_cnt:8;
> +	u32 trail_cnt:5;
> +	u32 rsvd9:3;
> +	u32 exit_zero_cnt:6;
> +	u32 rsvd10:2;
> +
> +	u32 clk_lane_switch_cnt;
> +	u32 hl_switch_cnt;
> +
> +	u32 rsvd11[6];
> +
> +	/* timings based on dphy spec */
> +	u8 tclk_miss;
> +	u8 tclk_post;
> +	u8 rsvd12;
> +	u8 tclk_pre;
> +	u8 tclk_prepare;
> +	u8 tclk_settle;
> +	u8 tclk_term_enable;
> +	u8 tclk_trail;
> +	u16 tclk_prepare_clkzero;
> +	u8 rsvd13;
> +	u8 td_term_enable;
> +	u8 teot;
> +	u8 ths_exit;
> +	u8 ths_prepare;
> +	u16 ths_prepare_hszero;
> +	u8 rsvd14;
> +	u8 ths_settle;
> +	u8 ths_skip;
> +	u8 ths_trail;
> +	u8 tinit;
> +	u8 tlpx;
> +	u8 rsvd15[3];
> +
> +	/* GPIOs */
> +	u8 panel_enable;
> +	u8 bl_enable;
> +	u8 pwm_enable;
> +	u8 reset_r_n;
> +	u8 pwr_down_r;
> +	u8 stdby_r_n;
> +
> +} __packed;
> +
> +/* all delays have a unit of 100us */
> +struct mipi_pps_data {
> +	u16 panel_on_delay;
> +	u16 bl_enable_delay;
> +	u16 bl_disable_delay;
> +	u16 panel_off_delay;
> +	u16 panel_power_cycle_delay;
> +} __packed;
> +
> +#endif /* __INTEL_DSI_VBT_DEFS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> index 92c04811aa28..6612d3a4ec49 100644
> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
> @@ -37,7 +37,7 @@
>  #ifndef _INTEL_VBT_DEFS_H_
>  #define _INTEL_VBT_DEFS_H_
> 
> -#include "intel_bios.h"
> +#include "intel_dsi_vbt_defs.h"
> 
>  /* EDID derived structures */
>  struct bdb_edid_pnp_id {
> --
> 2.47.2

RE: [PATCH 2/4] drm/i915/vbt: add anonymous structs to group DSI VBT defs

[Kandpal, Suraj]

> Subject: [PATCH 2/4] drm/i915/vbt: add anonymous structs to group DSI VBT
> defs
> 
> The grouping of DSI VBT definitions is hard to follow and match against the
> spec. Use anonymous structs and add comments with the spec description.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 87 ++++++++++---------
>  1 file changed, 47 insertions(+), 40 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> index f83d42ed0c5a..7ac872dbba8d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> @@ -47,53 +47,55 @@ struct mipi_config {
>  	u16 panel_id;
> 
>  	/* General Params */
> -	u32 enable_dithering:1;
> -	u32 rsvd1:1;
> -	u32 is_bridge:1;
> +	struct {
> +		u32 enable_dithering:1;
> +		u32 rsvd1:1;
> +		u32 is_bridge:1;
> 
> -	u32 panel_arch_type:2;
> -	u32 is_cmd_mode:1;
> +		u32 panel_arch_type:2;
> +		u32 is_cmd_mode:1;
> 
>  #define NON_BURST_SYNC_PULSE	0x1
>  #define NON_BURST_SYNC_EVENTS	0x2
>  #define BURST_MODE		0x3
> -	u32 video_transfer_mode:2;
> +		u32 video_transfer_mode:2;
> 
> -	u32 cabc_supported:1;
> +		u32 cabc_supported:1;
>  #define PPS_BLC_PMIC   0
>  #define PPS_BLC_SOC    1
> -	u32 pwm_blc:1;
> +		u32 pwm_blc:1;
> 
> -	/* Bit 13:10 */
>  #define PIXEL_FORMAT_RGB565			0x1
>  #define PIXEL_FORMAT_RGB666			0x2
>  #define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
>  #define PIXEL_FORMAT_RGB888			0x4
> -	u32 videomode_color_format:4;
> +		u32 videomode_color_format:4;
> 
> -	/* Bit 15:14 */
>  #define ENABLE_ROTATION_0	0x0
>  #define ENABLE_ROTATION_90	0x1
>  #define ENABLE_ROTATION_180	0x2
>  #define ENABLE_ROTATION_270	0x3
> -	u32 rotation:2;
> -	u32 bta_enabled:1;
> -	u32 rsvd2:15;
> +		u32 rotation:2;
> +		u32 bta_enabled:1;
> +		u32 rsvd2:15;
> +	} __packed;
> 
> -	/* 2 byte Port Description */
> +	/* Port Desc */
> +	struct {
>  #define DUAL_LINK_NOT_SUPPORTED	0
>  #define DUAL_LINK_FRONT_BACK	1
>  #define DUAL_LINK_PIXEL_ALT	2
> -	u16 dual_link:2;
> -	u16 lane_cnt:2;
> -	u16 pixel_overlap:3;
> -	u16 rgb_flip:1;
> +		u16 dual_link:2;
> +		u16 lane_cnt:2;
> +		u16 pixel_overlap:3;
> +		u16 rgb_flip:1;
>  #define DL_DCS_PORT_A			0x00
>  #define DL_DCS_PORT_C			0x01
>  #define DL_DCS_PORT_A_AND_C		0x02
> -	u16 dl_dcs_cabc_ports:2;
> -	u16 dl_dcs_backlight_ports:2;
> -	u16 rsvd3:4;
> +		u16 dl_dcs_cabc_ports:2;
> +		u16 dl_dcs_backlight_ports:2;
> +		u16 rsvd3:4;
> +	} __packed;
> 
>  	u16 rsvd4;
> 
> @@ -102,18 +104,22 @@ struct mipi_config {
>  	u32 dsi_ddr_clk;
>  	u32 bridge_ref_clk;
> 
> +	/* LP Byte Clock */
> +	struct {
>  #define  BYTE_CLK_SEL_20MHZ		0
>  #define  BYTE_CLK_SEL_10MHZ		1
>  #define  BYTE_CLK_SEL_5MHZ		2
> -	u8 byte_clk_sel:2;
> -
> -	u8 rsvd6:6;
> -
> -	/* DPHY Flags */
> -	u16 dphy_param_valid:1;
> -	u16 eot_pkt_disabled:1;
> -	u16 enable_clk_stop:1;
> -	u16 rsvd7:13;
> +		u8 byte_clk_sel:2;
> +		u8 rsvd6:6;
> +	} __packed;
> +
> +	/* DPhy Flags */
> +	struct {
> +		u16 dphy_param_valid:1;
> +		u16 eot_pkt_disabled:1;
> +		u16 enable_clk_stop:1;
> +		u16 rsvd7:13;
> +	} __packed;
> 
>  	u32 hs_tx_timeout;
>  	u32 lp_rx_timeout;
> @@ -123,14 +129,16 @@ struct mipi_config {
>  	u32 dbi_bw_timer;
>  	u32 lp_byte_clk_val;
> 
> -	/*  4 byte Dphy Params */
> -	u32 prepare_cnt:6;
> -	u32 rsvd8:2;
> -	u32 clk_zero_cnt:8;
> -	u32 trail_cnt:5;
> -	u32 rsvd9:3;
> -	u32 exit_zero_cnt:6;
> -	u32 rsvd10:2;
> +	/*  DPhy Params */
> +	struct {
> +		u32 prepare_cnt:6;
> +		u32 rsvd8:2;
> +		u32 clk_zero_cnt:8;
> +		u32 trail_cnt:5;
> +		u32 rsvd9:3;
> +		u32 exit_zero_cnt:6;
> +		u32 rsvd10:2;
> +	} __packed;
> 
>  	u32 clk_lane_switch_cnt;
>  	u32 hl_switch_cnt;
> @@ -168,7 +176,6 @@ struct mipi_config {
>  	u8 reset_r_n;
>  	u8 pwr_down_r;
>  	u8 stdby_r_n;
> -
>  } __packed;
> 
>  /* all delays have a unit of 100us */
> --
> 2.47.2

RE: [PATCH 3/4] drm/i915/vbt: flip bta_enabled to bta_disable

[Kandpal, Suraj]

> Subject: [PATCH 3/4] drm/i915/vbt: flip bta_enabled to bta_disable
> 
> The meaning is disable, so flip the member name.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsi_vbt.c      | 2 +-
>  drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index e6a851d276f8..23402408e172 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -777,7 +777,7 @@ bool intel_dsi_vbt_init(struct intel_dsi *intel_dsi, u16
> panel_id)
>  	intel_dsi->init_count = mipi_config->master_init_timer;
>  	intel_dsi->bw_timer = mipi_config->dbi_bw_timer;
>  	intel_dsi->video_frmt_cfg_bits =
> -		mipi_config->bta_enabled ? DISABLE_VIDEO_BTA : 0;
> +		mipi_config->bta_disable ? DISABLE_VIDEO_BTA : 0;
>  	intel_dsi->bgr_enabled = mipi_config->rgb_flip;
> 
>  	/* Starting point, adjusted depending on dual link and burst mode */
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> index 7ac872dbba8d..3f9b9ed6592c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> @@ -76,7 +76,7 @@ struct mipi_config {
>  #define ENABLE_ROTATION_180	0x2
>  #define ENABLE_ROTATION_270	0x3
>  		u32 rotation:2;
> -		u32 bta_enabled:1;
> +		u32 bta_disable:1;
>  		u32 rsvd2:15;
>  	} __packed;
> 
> --
> 2.47.2

RE: [PATCH 4/4] drm/i915/vbt: add missing DSI VBT defs

[Kandpal, Suraj]

> Subject: [PATCH 4/4] drm/i915/vbt: add missing DSI VBT defs
> 
> Add some missing DSI VBT definitions.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>

LGTM,
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h | 13 ++++++++++---
>  1 file changed, 10 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> index 3f9b9ed6592c..edc7331dcca2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
> @@ -94,10 +94,15 @@ struct mipi_config {
>  #define DL_DCS_PORT_A_AND_C		0x02
>  		u16 dl_dcs_cabc_ports:2;
>  		u16 dl_dcs_backlight_ports:2;
> -		u16 rsvd3:4;
> +		u16 port_sync:1;				/* 219-230
> */
> +		u16 rsvd3:3;
>  	} __packed;
> 
> -	u16 rsvd4;
> +	/* DSI Controller Parameters */
> +	struct {
> +		u16 dsi_usage:1;
> +		u16 rsvd4:15;
> +	} __packed;
> 
>  	u8 rsvd5;
>  	u32 target_burst_mode_freq;
> @@ -118,7 +123,9 @@ struct mipi_config {
>  		u16 dphy_param_valid:1;
>  		u16 eot_pkt_disabled:1;
>  		u16 enable_clk_stop:1;
> -		u16 rsvd7:13;
> +		u16 blanking_packets_during_bllp:1;		/* 219+ */
> +		u16 lp_clock_during_lpm:1;			/* 219+ */
> +		u16 rsvd7:11;
>  	} __packed;
> 
>  	u32 hs_tx_timeout;
> --
> 2.47.2

RE: [PATCH 1/4] drm/i915/vbt: split up DSI VBT defs to a separate file

[Jani Nikula]

On Tue, 12 Aug 2025, "Kandpal, Suraj" <suraj.kandpal@intel.com> wrote:
>> Subject: [PATCH 1/4] drm/i915/vbt: split up DSI VBT defs to a separate file
>> 
>> The DSI VBT definitions have ended up in intel_bios.h, because intel_vbt_defs.h
>> is supposed to be internal to intel_bios.c, but the DSI VBT definitions are
>> needed in more places.
>> 
>> Split out the DSI VBT definitions to intel_dsi_vbt_defs.h. This will also help keep
>> the definitions in sync with IGT.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>
> LGTM,
> Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>

Thanks for the reviews, series pushed to din.

BR,
Jani.

>
>> ---
>>  drivers/gpu/drm/i915/display/intel_bios.h     | 174 -----------------
>>  .../drm/i915/display/intel_display_types.h    |   1 +
>>  .../gpu/drm/i915/display/intel_dsi_vbt_defs.h | 183 ++++++++++++++++++
>>  drivers/gpu/drm/i915/display/intel_vbt_defs.h |   2 +-
>>  4 files changed, 185 insertions(+), 175 deletions(-)  create mode 100644
>> drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_bios.h
>> b/drivers/gpu/drm/i915/display/intel_bios.h
>> index 6cd7a011b8c4..8fdde85f7939 100644
>> --- a/drivers/gpu/drm/i915/display/intel_bios.h
>> +++ b/drivers/gpu/drm/i915/display/intel_bios.h
>> @@ -50,180 +50,6 @@ enum intel_backlight_type {
>>  	INTEL_BACKLIGHT_VESA_EDP_AUX_INTERFACE,
>>  };
>> 
>> -/*
>> - * MIPI Sequence Block definitions
>> - *
>> - * Note the VBT spec has AssertReset / DeassertReset swapped from their
>> - * usual naming, we use the proper names here to avoid confusion when
>> - * reading the code.
>> - */
>> -enum mipi_seq {
>> -	MIPI_SEQ_END = 0,
>> -	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
>> -	MIPI_SEQ_INIT_OTP,
>> -	MIPI_SEQ_DISPLAY_ON,
>> -	MIPI_SEQ_DISPLAY_OFF,
>> -	MIPI_SEQ_ASSERT_RESET,		/* Spec says
>> MipiDeassertResetPin */
>> -	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
>> -	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
>> -	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
>> -	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
>> -	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
>> -	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
>> -	MIPI_SEQ_MAX
>> -};
>> -
>> -enum mipi_seq_element {
>> -	MIPI_SEQ_ELEM_END = 0,
>> -	MIPI_SEQ_ELEM_SEND_PKT,
>> -	MIPI_SEQ_ELEM_DELAY,
>> -	MIPI_SEQ_ELEM_GPIO,
>> -	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
>> -	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
>> -	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
>> -	MIPI_SEQ_ELEM_MAX
>> -};
>> -
>> -#define MIPI_DSI_UNDEFINED_PANEL_ID	0
>> -#define MIPI_DSI_GENERIC_PANEL_ID	1
>> -
>> -struct mipi_config {
>> -	u16 panel_id;
>> -
>> -	/* General Params */
>> -	u32 enable_dithering:1;
>> -	u32 rsvd1:1;
>> -	u32 is_bridge:1;
>> -
>> -	u32 panel_arch_type:2;
>> -	u32 is_cmd_mode:1;
>> -
>> -#define NON_BURST_SYNC_PULSE	0x1
>> -#define NON_BURST_SYNC_EVENTS	0x2
>> -#define BURST_MODE		0x3
>> -	u32 video_transfer_mode:2;
>> -
>> -	u32 cabc_supported:1;
>> -#define PPS_BLC_PMIC   0
>> -#define PPS_BLC_SOC    1
>> -	u32 pwm_blc:1;
>> -
>> -	/* Bit 13:10 */
>> -#define PIXEL_FORMAT_RGB565			0x1
>> -#define PIXEL_FORMAT_RGB666			0x2
>> -#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
>> -#define PIXEL_FORMAT_RGB888			0x4
>> -	u32 videomode_color_format:4;
>> -
>> -	/* Bit 15:14 */
>> -#define ENABLE_ROTATION_0	0x0
>> -#define ENABLE_ROTATION_90	0x1
>> -#define ENABLE_ROTATION_180	0x2
>> -#define ENABLE_ROTATION_270	0x3
>> -	u32 rotation:2;
>> -	u32 bta_enabled:1;
>> -	u32 rsvd2:15;
>> -
>> -	/* 2 byte Port Description */
>> -#define DUAL_LINK_NOT_SUPPORTED	0
>> -#define DUAL_LINK_FRONT_BACK	1
>> -#define DUAL_LINK_PIXEL_ALT	2
>> -	u16 dual_link:2;
>> -	u16 lane_cnt:2;
>> -	u16 pixel_overlap:3;
>> -	u16 rgb_flip:1;
>> -#define DL_DCS_PORT_A			0x00
>> -#define DL_DCS_PORT_C			0x01
>> -#define DL_DCS_PORT_A_AND_C		0x02
>> -	u16 dl_dcs_cabc_ports:2;
>> -	u16 dl_dcs_backlight_ports:2;
>> -	u16 rsvd3:4;
>> -
>> -	u16 rsvd4;
>> -
>> -	u8 rsvd5;
>> -	u32 target_burst_mode_freq;
>> -	u32 dsi_ddr_clk;
>> -	u32 bridge_ref_clk;
>> -
>> -#define  BYTE_CLK_SEL_20MHZ		0
>> -#define  BYTE_CLK_SEL_10MHZ		1
>> -#define  BYTE_CLK_SEL_5MHZ		2
>> -	u8 byte_clk_sel:2;
>> -
>> -	u8 rsvd6:6;
>> -
>> -	/* DPHY Flags */
>> -	u16 dphy_param_valid:1;
>> -	u16 eot_pkt_disabled:1;
>> -	u16 enable_clk_stop:1;
>> -	u16 rsvd7:13;
>> -
>> -	u32 hs_tx_timeout;
>> -	u32 lp_rx_timeout;
>> -	u32 turn_around_timeout;
>> -	u32 device_reset_timer;
>> -	u32 master_init_timer;
>> -	u32 dbi_bw_timer;
>> -	u32 lp_byte_clk_val;
>> -
>> -	/*  4 byte Dphy Params */
>> -	u32 prepare_cnt:6;
>> -	u32 rsvd8:2;
>> -	u32 clk_zero_cnt:8;
>> -	u32 trail_cnt:5;
>> -	u32 rsvd9:3;
>> -	u32 exit_zero_cnt:6;
>> -	u32 rsvd10:2;
>> -
>> -	u32 clk_lane_switch_cnt;
>> -	u32 hl_switch_cnt;
>> -
>> -	u32 rsvd11[6];
>> -
>> -	/* timings based on dphy spec */
>> -	u8 tclk_miss;
>> -	u8 tclk_post;
>> -	u8 rsvd12;
>> -	u8 tclk_pre;
>> -	u8 tclk_prepare;
>> -	u8 tclk_settle;
>> -	u8 tclk_term_enable;
>> -	u8 tclk_trail;
>> -	u16 tclk_prepare_clkzero;
>> -	u8 rsvd13;
>> -	u8 td_term_enable;
>> -	u8 teot;
>> -	u8 ths_exit;
>> -	u8 ths_prepare;
>> -	u16 ths_prepare_hszero;
>> -	u8 rsvd14;
>> -	u8 ths_settle;
>> -	u8 ths_skip;
>> -	u8 ths_trail;
>> -	u8 tinit;
>> -	u8 tlpx;
>> -	u8 rsvd15[3];
>> -
>> -	/* GPIOs */
>> -	u8 panel_enable;
>> -	u8 bl_enable;
>> -	u8 pwm_enable;
>> -	u8 reset_r_n;
>> -	u8 pwr_down_r;
>> -	u8 stdby_r_n;
>> -
>> -} __packed;
>> -
>> -/* all delays have a unit of 100us */
>> -struct mipi_pps_data {
>> -	u16 panel_on_delay;
>> -	u16 bl_enable_delay;
>> -	u16 bl_disable_delay;
>> -	u16 panel_off_delay;
>> -	u16 panel_power_cycle_delay;
>> -} __packed;
>> -
>>  void intel_bios_init(struct intel_display *display);  void
>> intel_bios_init_panel_early(struct intel_display *display,
>>  				 struct intel_panel *panel,
>> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h
>> b/drivers/gpu/drm/i915/display/intel_display_types.h
>> index 35596f3921e8..0d945d1fedd6 100644
>> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
>> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>> @@ -50,6 +50,7 @@
>>  #include "intel_display_limits.h"
>>  #include "intel_display_power.h"
>>  #include "intel_dpll_mgr.h"
>> +#include "intel_dsi_vbt_defs.h"
>>  #include "intel_wm_types.h"
>> 
>>  struct cec_notifier;
>> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
>> b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
>> new file mode 100644
>> index 000000000000..f83d42ed0c5a
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt_defs.h
>> @@ -0,0 +1,183 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/* Copyright © 2025 Intel Corporation */
>> +
>> +#ifndef __INTEL_DSI_VBT_DEFS_H__
>> +#define __INTEL_DSI_VBT_DEFS_H__
>> +
>> +#include <linux/types.h>
>> +
>> +/*
>> + * MIPI Sequence Block definitions
>> + *
>> + * Note the VBT spec has AssertReset / DeassertReset swapped from their
>> + * usual naming, we use the proper names here to avoid confusion when
>> + * reading the code.
>> + */
>> +enum mipi_seq {
>> +	MIPI_SEQ_END = 0,
>> +	MIPI_SEQ_DEASSERT_RESET,	/* Spec says MipiAssertResetPin */
>> +	MIPI_SEQ_INIT_OTP,
>> +	MIPI_SEQ_DISPLAY_ON,
>> +	MIPI_SEQ_DISPLAY_OFF,
>> +	MIPI_SEQ_ASSERT_RESET,		/* Spec says
>> MipiDeassertResetPin */
>> +	MIPI_SEQ_BACKLIGHT_ON,		/* sequence block v2+ */
>> +	MIPI_SEQ_BACKLIGHT_OFF,		/* sequence block v2+ */
>> +	MIPI_SEQ_TEAR_ON,		/* sequence block v2+ */
>> +	MIPI_SEQ_TEAR_OFF,		/* sequence block v3+ */
>> +	MIPI_SEQ_POWER_ON,		/* sequence block v3+ */
>> +	MIPI_SEQ_POWER_OFF,		/* sequence block v3+ */
>> +	MIPI_SEQ_MAX
>> +};
>> +
>> +enum mipi_seq_element {
>> +	MIPI_SEQ_ELEM_END = 0,
>> +	MIPI_SEQ_ELEM_SEND_PKT,
>> +	MIPI_SEQ_ELEM_DELAY,
>> +	MIPI_SEQ_ELEM_GPIO,
>> +	MIPI_SEQ_ELEM_I2C,		/* sequence block v2+ */
>> +	MIPI_SEQ_ELEM_SPI,		/* sequence block v3+ */
>> +	MIPI_SEQ_ELEM_PMIC,		/* sequence block v3+ */
>> +	MIPI_SEQ_ELEM_MAX
>> +};
>> +
>> +#define MIPI_DSI_UNDEFINED_PANEL_ID	0
>> +#define MIPI_DSI_GENERIC_PANEL_ID	1
>> +
>> +struct mipi_config {
>> +	u16 panel_id;
>> +
>> +	/* General Params */
>> +	u32 enable_dithering:1;
>> +	u32 rsvd1:1;
>> +	u32 is_bridge:1;
>> +
>> +	u32 panel_arch_type:2;
>> +	u32 is_cmd_mode:1;
>> +
>> +#define NON_BURST_SYNC_PULSE	0x1
>> +#define NON_BURST_SYNC_EVENTS	0x2
>> +#define BURST_MODE		0x3
>> +	u32 video_transfer_mode:2;
>> +
>> +	u32 cabc_supported:1;
>> +#define PPS_BLC_PMIC   0
>> +#define PPS_BLC_SOC    1
>> +	u32 pwm_blc:1;
>> +
>> +	/* Bit 13:10 */
>> +#define PIXEL_FORMAT_RGB565			0x1
>> +#define PIXEL_FORMAT_RGB666			0x2
>> +#define PIXEL_FORMAT_RGB666_LOOSELY_PACKED	0x3
>> +#define PIXEL_FORMAT_RGB888			0x4
>> +	u32 videomode_color_format:4;
>> +
>> +	/* Bit 15:14 */
>> +#define ENABLE_ROTATION_0	0x0
>> +#define ENABLE_ROTATION_90	0x1
>> +#define ENABLE_ROTATION_180	0x2
>> +#define ENABLE_ROTATION_270	0x3
>> +	u32 rotation:2;
>> +	u32 bta_enabled:1;
>> +	u32 rsvd2:15;
>> +
>> +	/* 2 byte Port Description */
>> +#define DUAL_LINK_NOT_SUPPORTED	0
>> +#define DUAL_LINK_FRONT_BACK	1
>> +#define DUAL_LINK_PIXEL_ALT	2
>> +	u16 dual_link:2;
>> +	u16 lane_cnt:2;
>> +	u16 pixel_overlap:3;
>> +	u16 rgb_flip:1;
>> +#define DL_DCS_PORT_A			0x00
>> +#define DL_DCS_PORT_C			0x01
>> +#define DL_DCS_PORT_A_AND_C		0x02
>> +	u16 dl_dcs_cabc_ports:2;
>> +	u16 dl_dcs_backlight_ports:2;
>> +	u16 rsvd3:4;
>> +
>> +	u16 rsvd4;
>> +
>> +	u8 rsvd5;
>> +	u32 target_burst_mode_freq;
>> +	u32 dsi_ddr_clk;
>> +	u32 bridge_ref_clk;
>> +
>> +#define  BYTE_CLK_SEL_20MHZ		0
>> +#define  BYTE_CLK_SEL_10MHZ		1
>> +#define  BYTE_CLK_SEL_5MHZ		2
>> +	u8 byte_clk_sel:2;
>> +
>> +	u8 rsvd6:6;
>> +
>> +	/* DPHY Flags */
>> +	u16 dphy_param_valid:1;
>> +	u16 eot_pkt_disabled:1;
>> +	u16 enable_clk_stop:1;
>> +	u16 rsvd7:13;
>> +
>> +	u32 hs_tx_timeout;
>> +	u32 lp_rx_timeout;
>> +	u32 turn_around_timeout;
>> +	u32 device_reset_timer;
>> +	u32 master_init_timer;
>> +	u32 dbi_bw_timer;
>> +	u32 lp_byte_clk_val;
>> +
>> +	/*  4 byte Dphy Params */
>> +	u32 prepare_cnt:6;
>> +	u32 rsvd8:2;
>> +	u32 clk_zero_cnt:8;
>> +	u32 trail_cnt:5;
>> +	u32 rsvd9:3;
>> +	u32 exit_zero_cnt:6;
>> +	u32 rsvd10:2;
>> +
>> +	u32 clk_lane_switch_cnt;
>> +	u32 hl_switch_cnt;
>> +
>> +	u32 rsvd11[6];
>> +
>> +	/* timings based on dphy spec */
>> +	u8 tclk_miss;
>> +	u8 tclk_post;
>> +	u8 rsvd12;
>> +	u8 tclk_pre;
>> +	u8 tclk_prepare;
>> +	u8 tclk_settle;
>> +	u8 tclk_term_enable;
>> +	u8 tclk_trail;
>> +	u16 tclk_prepare_clkzero;
>> +	u8 rsvd13;
>> +	u8 td_term_enable;
>> +	u8 teot;
>> +	u8 ths_exit;
>> +	u8 ths_prepare;
>> +	u16 ths_prepare_hszero;
>> +	u8 rsvd14;
>> +	u8 ths_settle;
>> +	u8 ths_skip;
>> +	u8 ths_trail;
>> +	u8 tinit;
>> +	u8 tlpx;
>> +	u8 rsvd15[3];
>> +
>> +	/* GPIOs */
>> +	u8 panel_enable;
>> +	u8 bl_enable;
>> +	u8 pwm_enable;
>> +	u8 reset_r_n;
>> +	u8 pwr_down_r;
>> +	u8 stdby_r_n;
>> +
>> +} __packed;
>> +
>> +/* all delays have a unit of 100us */
>> +struct mipi_pps_data {
>> +	u16 panel_on_delay;
>> +	u16 bl_enable_delay;
>> +	u16 bl_disable_delay;
>> +	u16 panel_off_delay;
>> +	u16 panel_power_cycle_delay;
>> +} __packed;
>> +
>> +#endif /* __INTEL_DSI_VBT_DEFS_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> index 92c04811aa28..6612d3a4ec49 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> +++ b/drivers/gpu/drm/i915/display/intel_vbt_defs.h
>> @@ -37,7 +37,7 @@
>>  #ifndef _INTEL_VBT_DEFS_H_
>>  #define _INTEL_VBT_DEFS_H_
>> 
>> -#include "intel_bios.h"
>> +#include "intel_dsi_vbt_defs.h"
>> 
>>  /* EDID derived structures */
>>  struct bdb_edid_pnp_id {
>> --
>> 2.47.2
>

-- 
Jani Nikula, Intel