messages from 2025-10-30 22:24:27 to 2025-10-31 18:10:45 UTC [more...]
[PULL] drm-misc-fixes
2025-10-31 18:10 UTC (2+ messages)
[PATCH v6 0/6] Fix serialization on burst of unbinds - v2
2025-10-31 18:09 UTC (7+ messages)
` [PATCH v6 1/6] drm/xe: Enforce correct user fence signaling order using
` [PATCH v6 2/6] drm/xe: Attach last fence to TLB invalidation job queues
` [PATCH v6 3/6] drm/xe: Decouple bind queue last fence from TLB invalidations
` [PATCH v6 4/6] drm/xe: Skip TLB invalidation waits in page fault binds
` [PATCH v6 5/6] drm/xe: Disallow input fences on zero batch execs and zero binds
` [PATCH v6 6/6] drm/xe: Remove last fence dependency check from binds and execs
[PULL] drm-intel-fixes
2025-10-31 18:09 UTC (2+ messages)
[PATCH v4 0/7] Pagefault refactor
2025-10-31 18:01 UTC (10+ messages)
` [PATCH v4 1/7] drm/xe: Stub out new pagefault layer
` [PATCH v4 2/7] drm/xe: Implement xe_pagefault_init
` [PATCH v4 3/7] drm/xe: Implement xe_pagefault_reset
` [PATCH v4 4/7] drm/xe: Implement xe_pagefault_handler
` [PATCH v4 5/7] drm/xe: Implement xe_pagefault_queue_work
` [PATCH v4 6/7] drm/xe: Add xe_guc_pagefault layer
` [PATCH v4 7/7] drm/xe: Remove unused GT page fault code
` ✗ CI.checkpatch: warning for Pagefault refactor (rev3)
` ✓ CI.KUnit: success "
[PATCH v2] drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec
2025-10-31 17:57 UTC
[PATCH v4] drm/xe/gt_throttle: Avoid TOCTOU when monitoring reasons
2025-10-31 17:55 UTC (4+ messages)
` ✗ CI.checkpatch: warning for "
` ✓ CI.KUnit: success "
` ✓ Xe.CI.BAT: "
[PULL] drm-misc-next
2025-10-31 17:53 UTC (2+ messages)
[PULL] drm-xe-next
2025-10-31 17:46 UTC (2+ messages)
[PATCH v3 00/28] vfio/xe: Add driver variant for Xe VF migration
2025-10-31 17:39 UTC (22+ messages)
` [PATCH v3 03/28] drm/xe/pf: Convert control state to bitmap
` [PATCH v3 05/28] drm/xe/pf: Add data structures and handlers for migration rings
` [PATCH v3 07/28] drm/xe/pf: Add support for encap/decap of bitstream to/from packet
` [PATCH v3 08/28] drm/xe/pf: Add minimalistic migration descriptor
` [PATCH v3 12/28] drm/xe/pf: Increase PF GuC Buffer Cache size and use it for VF migration
` [PATCH v3 17/28] drm/xe/pf: Add helpers for VF GGTT migration data handling
` [PATCH v3 24/28] drm/xe/pf: Enable SR-IOV VF migration
` [PATCH v3 25/28] drm/xe/pci: Introduce a helper to allow VF access to PF xe_device
` ✗ CI.checkpatch: warning for vfio/xe: Add driver variant for Xe VF migration (rev3)
` ✓ CI.KUnit: success "
` ✓ Xe.CI.BAT: "
` ✗ Xe.CI.Full: failure "
[PATCH v2 00/32] drm/i915/display: Add initial support for Xe3p_LPD
2025-10-31 17:36 UTC (7+ messages)
` [PATCH v2 13/32] drm/i915/xe3p_lpd: Adapt to updates on MBUS_CTL/DBUF_CTL registers
` [PATCH v2 19/32] drm/i915/xe3p_lpd: PSR SU minimum lines is 4
[FOR CI 0/8] Testing PREEMPT_RT with disabling irqs in the most critical section
2025-10-31 16:46 UTC (13+ messages)
` [FOR CI 8/8] drm/i915/display: Use intel_de_write_fw in intel_pipe_fastset
` ✗ Xe.CI.Full: failure for Testing PREEMPT_RT with disabling irqs in the most critical section
` ✗ CI.checkpatch: warning for Testing PREEMPT_RT with disabling irqs in the most critical section. (rev2)
` ✓ CI.KUnit: success "
` ✗ CI.checksparse: warning "
` ✓ Xe.CI.BAT: success "
[PATCH v3 0/7] Pagefault refactor
2025-10-31 16:41 UTC (7+ messages)
` [PATCH v3 1/7] drm/xe: Stub out new pagefault layer
` [PATCH v3 2/7] drm/xe: Implement xe_pagefault_init
[PATCH v2 0/2] Fix user-after-free during driver unbind
2025-10-31 16:32 UTC (11+ messages)
` [PATCH v2 1/2] drm/xe/gt: Synchronize GT reset with device unbind
` [PATCH v2 2/2] drm/xe/guc: Synchronize Dead CT worker with unbind
[PATCH] drm/xe/xe3: Extend wa_14023061436
2025-10-31 16:02 UTC (3+ messages)
` ✗ Xe.CI.Full: failure for "
[PATCH] drm/xe: Dump PAT entries with reserved mark
2025-10-31 15:49 UTC (8+ messages)
` [PATCH v3] drm/xe: highlight reserved PAT entries in dump output
` ✗ Xe.CI.Full: failure for drm/xe: Dump PAT entries with reserved mark (rev2)
` ✓ CI.KUnit: success for drm/xe: Dump PAT entries with reserved mark (rev3)
` ✓ Xe.CI.BAT: "
` ✓ Xe.CI.Full: "
[PATCH v2] drm/xe/uapi: Implement DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION flag
2025-10-31 15:47 UTC (3+ messages)
` ✓ CI.KUnit: success for drm/xe/uapi: Implement DRM_XE_GEM_CREATE_FLAG_NO_COMPRESSION flag (rev2)
` ✓ Xe.CI.BAT: "
[PATCH] drm/xe: share USM BCS engine via root-tile helper
2025-10-31 15:08 UTC (4+ messages)
` ✓ CI.KUnit: success for drm/xe: share USM BCS engine via root-tile helper (rev2)
` ✓ Xe.CI.BAT: "
` ✗ Xe.CI.Full: failure "
[PATCH v8 0/4] Introduce GT runtime suspend/resume
2025-10-31 15:04 UTC (4+ messages)
` [PATCH v8 3/4] drm/xe/pm: Assert on runtime suspend if VFs are enabled
[PATCH] drm/xe: Do clean shutdown also when using flr
2025-10-31 14:37 UTC (3+ messages)
` ✓ CI.KUnit: success for "
` ✓ Xe.CI.BAT: "
[CI 00/32] [PATCH 00/32] drm/i915/display: Add MTL+ platforms to support dpll framework
2025-10-31 13:54 UTC (37+ messages)
` [CI 01/32] drm/i915/display: Rename TBT functions to be ICL specific
` [CI 02/32] drm/i915/display: Factor out C10 msgbus access start/end helpers
` [CI 03/32] drm/i915/display: Sanitize setting the Cx0 PLL use_c10 flag
` [CI 04/32] drm/i915/display: Sanitize calculating C20 PLL state from tables
` [CI 05/32] drm/i915/display: Track the C20 PHY VDR state in the PLL state
` [CI 06/32] drm/i915/display: Move definition of Cx0 PHY functions earlier
` [CI 07/32] drm/i915/display: Add macro to get DDI port width from a register value
` [CI 08/32] drm/i915/display: Track the Cx0 PHY enabled lane count in the PLL state
` [CI 09/32] drm/i915/display: Sanitize C10 PHY PLL SSC register setup
` [CI 10/32] drm/i915/display: Read out the Cx0 PHY SSC enabled state
` [CI 11/32] drm/i915/display: Determine Cx0 PLL DP mode from PLL state
` [CI 12/32] drm/i915/display: Determine Cx0 PLL port clock "
` [CI 13/32] drm/i915/display: Zero Cx0 PLL state before compute and HW readout
` [CI 14/32] drm/i915/display: Print additional Cx0 PLL HW state
` [CI 15/32] drm/i915/display: Remove state verification
` [CI 16/32] drm/i915/display: PLL information for MTL+
` [CI 17/32] drm/i915/display: Update C10/C20 state calculation
` [CI 18/32] drm/i915/display: Compute plls for MTL+ platform
` [CI 19/32] drm/i915/display: MTL+ .get_dplls
` [CI 20/32] drm/i915/display: MTL+ .put_dplls
` [CI 21/32] drm/i915/display: Add .update_active_dpll
` [CI 22/32] drm/i915/display: Add .update_dpll_ref_clks
` [CI 23/32] drm/i915/display: Add .dump_hw_state
` [CI 24/32] drm/i915/display: Add .compare_hw_state
` [CI 25/32] drm/i915/display: Add .get_hw_state to MTL+ platforms
` [CI 26/32] drm/i915/display: Add .get_freq "
` [CI 27/32] drm/i915/display: Add .crtc_get_dpll hook
` [CI 28/32] drm/i915/display: PLL verify debug state print
` [CI 29/32] drm/i915/display: Add .enable_clock on DDI for MTL+ platforms
` [CI 30/32] drm/i915/display: Get configuration for C10 and C20
` [CI 31/32] drm/i915/display: Add Thunderbolt support
` [CI 32/32] drm/i915/display: Enable dpll framework for MTL+
` ✗ CI.checkpatch: warning for drm/i915/display: Add MTL+ platforms to support dpll framework (rev2)
` ✓ CI.KUnit: success "
` ✗ CI.checksparse: warning "
` ✓ Xe.CI.BAT: success "
[PATCH v2] drm/xe/pf: Allow to lockdown the PF using custom guard
2025-10-31 13:39 UTC (6+ messages)
` ✗ CI.checkpatch: warning for "
` ✓ CI.KUnit: success "
` ✓ Xe.CI.BAT: "
` ✗ Xe.CI.Full: failure "
[PATCH v3 00/17] PF: Add sriov_admin sysfs tree
2025-10-31 13:24 UTC (17+ messages)
` [PATCH v3 06/17] drm/xe/pf: Relax report helper to accept PF in bulk configs
` [PATCH v3 08/17] drm/xe/pf: Add functions to bulk configure EQ/PT on GT
` [PATCH v3 10/17] drm/xe/pf: Allow bulk change all VFs EQ/PT using sysfs
` [PATCH v3 11/17] drm/xe/pf: Add functions to provision scheduling priority
` [PATCH v3 12/17] drm/xe/pf: Allow bulk change all VFs priority using sysfs
` [PATCH v3 13/17] drm/xe/pf: Allow change PF scheduling "
` [PATCH v3 14/17] drm/xe/pf: Promote xe_pci_sriov_get_vf_pdev
` [PATCH v3 15/17] drm/xe/pf: Add sysfs device symlinks to enabled VFs
` [PATCH v3 16/17] drm/xe/pf: Allow to stop the VF using sysfs
` [PATCH v3 17/17] drm/xe/pf: Add documentation for sriov_admin attributes
` ✗ CI.checkpatch: warning for PF: Add sriov_admin sysfs tree (rev3)
` ✓ CI.KUnit: success "
` ✓ Xe.CI.BAT: "
` ✗ Xe.CI.Full: failure "
[RFC v2 0/8] dma-buf: Add support for mapping dmabufs via interconnects
2025-10-31 13:16 UTC (7+ messages)
[PATCH v2 00/17] PF: Add sriov_admin sysfs tree
2025-10-31 12:35 UTC (4+ messages)
` [PATCH v2 17/17] drm/xe/pf: Add documentation for sriov_admin attributes
[PATCH v3 0/6] Use display parent interface for runtime pm
2025-10-31 12:29 UTC (5+ messages)
` ✓ Xe.CI.BAT: success for Use display parent interface for runtime pm (rev3)
` ✗ Xe.CI.Full: failure "
[PATCH v2 0/4] drm/i915/x3p_lpd: FBC related patches
2025-10-31 11:37 UTC (4+ messages)
` [PATCH v2 4/4] drm/i915/xe3p_lpd: use pixel normalizer for fp16 formats for FBC
[PATCH v3 00/25] Enable LT PHY
2025-10-31 11:31 UTC (30+ messages)
` [PATCH v3 01/25] drm/i915/ltphy: Add LT Phy related VDR and Pipe Registers
` [PATCH v3 02/25] drm/i915/cx0: Change register bit naming for powerdown values
` [PATCH v3 03/25] drm/i915/ltphy: Phy lane reset for LT Phy
` [PATCH v3 04/25] drm/i915/cx0: Move the HDMI FRL function to intel_hdmi
` [PATCH v3 05/25] drm/i915/ltphy: Program sequence for PORT_CLOCK_CTL for LT Phy
` [PATCH v3 06/25] drm/i915/ltphy: Add a wrapper for LT Phy powerdown change sequence
` [PATCH v3 07/25] drm/i915/ltphy: Read PHY_VDR_0_CONFIG register
` [PATCH v3 08/25] drm/i915/ltphy: Add LT Phy Programming recipe tables
` [PATCH v3 09/25] drm/i915/ltphy: Program the VDR PLL registers for LT PHY
` [PATCH v3 10/25] drm/i915/ltphy: Update the ltpll config table value for eDP
` [PATCH v3 11/25] drm/i915/ltphy: Enable SSC during port clock programming
` [PATCH v3 12/25] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v3 13/25] drm/i915/ltphy: Program the P2P Transaction flow for LT Phy
` [PATCH v3 14/25] drm/i915/ltphy: Program the rest of the PORT_CLOCK_CTL steps
` [PATCH v3 15/25] drm/i915/ltphy: Program the rest of the LT Phy Enable sequence
` [PATCH v3 16/25] drm/i915/ltphy: Program LT Phy Non-TBT PLL disable sequence
` [PATCH v3 17/25] drm/i915/ltphy: Hook up LT Phy Enable & Disable sequences
` [PATCH v3 18/25] drm/i915/ddi: Define LT Phy Swing tables
` [PATCH v3 19/25] drm/i915/ltphy: Program LT Phy Voltage Swing
` [PATCH v3 20/25] drm/i915/ltphy: Enable/Disable Tx after Non TBT Enable sequence
` [PATCH v3 21/25] drm/i915/ltphy: Define the LT Phy state compare function
` [PATCH v3 22/25] drm/i915/ltphy: Define function to readout LT Phy PLL state
` [PATCH v3 23/25] drm/i915/ltphy: Define LT PHY PLL state verify function
` [PATCH v3 24/25] drm/i915/display: Aux Enable and Display powerwell timeouts
` [PATCH v3 25/25] drm/i915/ltphy: Modify the step that need to be skipped
` ✗ CI.checkpatch: warning for Enable LT PHY (rev3)
` ✓ CI.KUnit: success "
` ✗ CI.checksparse: warning "
[PATCH 0/6] drm/i915: i915_utils.h refactoring
2025-10-31 11:26 UTC (6+ messages)
` [PATCH 3/6] drm/i915/display: add intel_display_run_as_guest()
[PATCH v2 1/2] drm/i915/dsi: log send packet sequence errors
2025-10-31 11:06 UTC (3+ messages)
[PATCH v3] drm/xe/xe_guc: Dynamically decide g2g buffer owner
2025-10-31 10:11 UTC (4+ messages)
` ✓ CI.KUnit: success for drm/xe/xe_guc: Dynamically decide g2g buffer owner (rev3)
` ✓ Xe.CI.BAT: "
` ✓ Xe.CI.Full: "
[PATCH v3 0/4] drm: replace drm_print.h includes from headers with a forward declaration
2025-10-31 10:01 UTC (4+ messages)
[PATCH] drm/display/dp: Rename bit 4 of DPCD TEST_REQUEST to match DP2.1 spec
2025-10-31 9:35 UTC (4+ messages)
[PATCH v2 0/4] PF: Add support for MERT
2025-10-31 9:29 UTC (8+ messages)
` [PATCH v2 1/4] drm/xe: Add device flag to indicate standalone MERT
` [PATCH v2 2/4] drm/xe/pf: Configure LMTT in MERT
` [PATCH v2 3/4] drm/xe/pf: Add TLB invalidation support for MERT
` [PATCH v2 4/4] drm/xe/pf: Handle MERT catastrophic errors
` ✗ CI.checkpatch: warning for PF: Add support for MERT
` ✓ CI.KUnit: success "
` ✓ Xe.CI.BAT: "
[FOR CI 7/8] With disabled irqs instead
2025-10-31 8:40 UTC (2+ messages)
` [FOR CI FIXED] "
[PATCH v2] drm/xe/pm: Enable WAKE# support
2025-10-31 8:03 UTC (3+ messages)
[PATCH v2 00/26] Enable LT PHY
2025-10-31 6:24 UTC (5+ messages)
` [PATCH v2 12/26] drm/i915/ltphy: Add function to calculate LT PHY port clock
` [PATCH v2 26/26] drm/i915/ltphy: Implement HDMI Algo for Pll state
[PATCH v3 0/8] drm/xe: CRI support in gt_throttle + refactors
2025-10-31 6:08 UTC (9+ messages)
` [PATCH v3 8/8] drm/xe/gt_throttle: Avoid TOCTOU when monitoring reasons
[PATCH 0/2] Introduce DRM_RAS using generic netlink for RAS
2025-10-31 5:38 UTC (6+ messages)
` [PATCH 1/2] drm/ras: Introduce the DRM RAS infrastructure over generic netlink
` DRM_RAS for CPER Error logging?!
[CI] drm/xe: Inline gt_reset in the worker
2025-10-31 4:28 UTC (2+ messages)
` ✗ Xe.CI.Full: failure for "
[drm-xe:drm-xe-next] BUILD SUCCESS d24f7d1f62e2ed1bce9664566c32ea13677958f4
2025-10-31 3:22 UTC
[drm-xe:drm-xe-fixes] BUILD SUCCESS b3fbda1a630a9439c885b2a5dc5230cc49a87e9e
2025-10-30 22:29 UTC
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