RE: [PATCH v2 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout

["Kahola, Mika" <mika.kahola@intel.com>]

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Tuesday, 5 August 2025 12.34
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Cc: stable@vger.kernel.org; Lin, Charlton <charlton.lin@intel.com>; Almahallawy, Khaled <khaled.almahallawy@intel.com>
> Subject: [PATCH v2 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout
> 
> On LNL+ for a disconnected sink the pin assignment value gets cleared by the HW/FW as soon as the sink gets disconnected, even
> if the PHY ownership got acquired already by the BIOS/driver (and hence the PHY itself is still connected and used by the display).
> During HW readout this can result in detecting the PHY's max lane count as 0 - matching the above cleared aka NONE pin
> assignment HW state. For a connected PHY the driver in general (outside of intel_tc.c) expects the max lane count value to be
> valid for the video mode enabled on the corresponding output (1, 2 or 4). Ensure this by setting the max lane count to 4 in this case.
> Note, that it doesn't matter if this lane count happened to be more than the max lane count with which the PHY got connected and
> enabled, since the only thing the driver can do with such an output - where the DP-alt sink is disconnected - is to disable the
> output.
> 
> v2: Rebased on change reading out the pin configuration only if the PHY
>     is connected.
> 
> Cc: stable@vger.kernel.org # v6.8+
> Reported-by: Charlton Lin <charlton.lin@intel.com>
> Tested-by: Khaled Almahallawy <khaled.almahallawy@intel.com>

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_tc.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index b8453fc3ab688..a89fbbf848d7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -23,6 +23,7 @@
>  #include "intel_modeset_lock.h"
>  #include "intel_tc.h"
> 
> +#define DP_PIN_ASSIGNMENT_NONE	0x0
>  #define DP_PIN_ASSIGNMENT_C	0x3
>  #define DP_PIN_ASSIGNMENT_D	0x4
>  #define DP_PIN_ASSIGNMENT_E	0x5
> @@ -308,6 +309,8 @@ static int lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
>  		REG_FIELD_GET(TCSS_DDI_STATUS_PIN_ASSIGNMENT_MASK, val);
> 
>  	switch (pin_assignment) {
> +	case DP_PIN_ASSIGNMENT_NONE:
> +		return 0;
>  	default:
>  		MISSING_CASE(pin_assignment);
>  		fallthrough;
> @@ -1159,6 +1162,12 @@ static void xelpdp_tc_phy_get_hw_state(struct intel_tc_port *tc)
>  		tc->lock_wakeref = tc_cold_block(tc);
> 
>  		read_pin_configuration(tc);
> +		/*
> +		 * Set a valid lane count value for a DP-alt sink which got
> +		 * disconnected. The driver can only disable the output on this PHY.
> +		 */
> +		if (tc->max_lane_count == 0)
> +			tc->max_lane_count = 4;
>  	}
> 
>  	drm_WARN_ON(display->drm,
> --
> 2.49.1