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From: "Kahola, Mika" <mika.kahola@intel.com>
To: "Deak, Imre" <imre.deak@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>,
	"intel-xe@lists.freedesktop.org" <intel-xe@lists.freedesktop.org>
Subject: RE: [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum
Date: Thu, 7 Aug 2025 12:56:40 +0000	[thread overview]
Message-ID: <DS4PPF69154114FA1CB30995D5AFB7CCA7AEF2CA@DS4PPF69154114F.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20250805073700.642107-11-imre.deak@intel.com>

> -----Original Message-----
> From: Intel-gfx <intel-gfx-bounces@lists.freedesktop.org> On Behalf Of Imre Deak
> Sent: Tuesday, 5 August 2025 10.37
> To: intel-gfx@lists.freedesktop.org; intel-xe@lists.freedesktop.org
> Subject: [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum
> 
> Pass around the pin assignment value via the corresponding enum instead of a plain integer.
> 
> While at it rename intel_tc_port_get_pin_assignment_mask() to intel_tc_port_get_pin_assignment(), since the value returned is
> not a mask.
> 

Reviewed-by: Mika Kahola <mika.kahola@intel.com>

> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c | 19 ++++++++++---------  drivers/gpu/drm/i915/display/intel_tc.c  | 14 ++++++++------
> drivers/gpu/drm/i915/display/intel_tc.h  |  3 ++-
>  3 files changed, 20 insertions(+), 16 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 866ed3e466645..2ed9fdd499c39 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -2166,7 +2166,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,  {
>  	struct intel_display *display = to_intel_display(crtc_state);
>  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
> -	u32 ln0, ln1, pin_assignment;
> +	enum intel_tc_pin_assignment pin_assignment;
> +	u32 ln0, ln1;
>  	u8 width;
> 
>  	if (DISPLAY_VER(display) >= 14)
> @@ -2188,11 +2189,11 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  	ln1 &= ~(MG_DP_MODE_CFG_DP_X1_MODE | MG_DP_MODE_CFG_DP_X2_MODE);
> 
>  	/* DPPATC */
> -	pin_assignment = intel_tc_port_get_pin_assignment_mask(dig_port);
> +	pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
>  	width = crtc_state->lane_count;
> 
>  	switch (pin_assignment) {
> -	case 0x0:
> +	case INTEL_TC_PIN_ASSIGNMENT_NONE:
>  		drm_WARN_ON(display->drm,
>  			    !intel_tc_port_in_legacy_mode(dig_port));
>  		if (width == 1) {
> @@ -2202,20 +2203,20 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  		}
>  		break;
> -	case 0x1:
> +	case INTEL_TC_PIN_ASSIGNMENT_A:
>  		if (width == 4) {
>  			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  		}
>  		break;
> -	case 0x2:
> +	case INTEL_TC_PIN_ASSIGNMENT_B:
>  		if (width == 2) {
>  			ln0 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  		}
>  		break;
> -	case 0x3:
> -	case 0x5:
> +	case INTEL_TC_PIN_ASSIGNMENT_C:
> +	case INTEL_TC_PIN_ASSIGNMENT_E:
>  		if (width == 1) {
>  			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
>  			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> @@ -2224,8 +2225,8 @@ icl_program_mg_dp_mode(struct intel_digital_port *dig_port,
>  			ln1 |= MG_DP_MODE_CFG_DP_X2_MODE;
>  		}
>  		break;
> -	case 0x4:
> -	case 0x6:
> +	case INTEL_TC_PIN_ASSIGNMENT_D:
> +	case INTEL_TC_PIN_ASSIGNMENT_F:
>  		if (width == 1) {
>  			ln0 |= MG_DP_MODE_CFG_DP_X1_MODE;
>  			ln1 |= MG_DP_MODE_CFG_DP_X1_MODE;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
> index 9a40ad07830f5..05df252640f46 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.c
> +++ b/drivers/gpu/drm/i915/display/intel_tc.c
> @@ -277,7 +277,8 @@ static u32 intel_tc_port_get_lane_mask(struct intel_digital_port *dig_port)
>  	return lane_mask >> DP_LANE_ASSIGNMENT_SHIFT(tc->phy_fia_idx);
>  }
> 
> -u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port)
> +enum intel_tc_pin_assignment
> +intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port)
>  {
>  	struct intel_display *display = to_intel_display(dig_port);
>  	struct intel_tc_port *tc = to_tc_port(dig_port); @@ -299,8 +300,9 @@ static int lnl_tc_port_get_max_lane_count(struct
> intel_digital_port *dig_port)
>  	struct intel_display *display = to_intel_display(dig_port);
>  	enum tc_port tc_port = intel_encoder_to_tc(&dig_port->base);
>  	struct intel_tc_port *tc = to_tc_port(dig_port);
> +	enum intel_tc_pin_assignment pin_assignment;
>  	intel_wakeref_t wakeref;
> -	u32 val, pin_assignment;
> +	u32 val;
> 
>  	with_intel_display_power(display, POWER_DOMAIN_DISPLAY_CORE, wakeref)
>  		val = intel_de_read(display, TCSS_DDI_STATUS(tc_port)); @@ -327,13 +329,13 @@ static int
> lnl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)
> 
>  static int mtl_tc_port_get_max_lane_count(struct intel_digital_port *dig_port)  {
> -	u32 pin_mask;
> +	enum intel_tc_pin_assignment pin_assignment;
> 
> -	pin_mask = intel_tc_port_get_pin_assignment_mask(dig_port);
> +	pin_assignment = intel_tc_port_get_pin_assignment(dig_port);
> 
> -	switch (pin_mask) {
> +	switch (pin_assignment) {
>  	default:
> -		MISSING_CASE(pin_mask);
> +		MISSING_CASE(pin_assignment);
>  		fallthrough;
>  	case INTEL_TC_PIN_ASSIGNMENT_D:
>  		return 2;
> diff --git a/drivers/gpu/drm/i915/display/intel_tc.h b/drivers/gpu/drm/i915/display/intel_tc.h
> index d35d9aae3b889..3ecb3de54e874 100644
> --- a/drivers/gpu/drm/i915/display/intel_tc.h
> +++ b/drivers/gpu/drm/i915/display/intel_tc.h
> @@ -88,7 +88,8 @@ bool intel_tc_port_handles_hpd_glitches(struct intel_digital_port *dig_port);
> 
>  bool intel_tc_port_connected(struct intel_encoder *encoder);
> 
> -u32 intel_tc_port_get_pin_assignment_mask(struct intel_digital_port *dig_port);
> +enum intel_tc_pin_assignment
> +intel_tc_port_get_pin_assignment(struct intel_digital_port *dig_port);
>  int intel_tc_port_max_lane_count(struct intel_digital_port *dig_port);  void intel_tc_port_set_fia_lane_count(struct
> intel_digital_port *dig_port,
>  				      int required_lanes);
> --
> 2.49.1


  reply	other threads:[~2025-08-07 12:56 UTC|newest]

Thread overview: 65+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-05  7:36 [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Imre Deak
2025-08-05  7:36 ` [PATCH 01/19] drm/i915/lnl+/tc: Fix handling of an enabled/disconnected dp-alt sink Imre Deak
2025-08-07  7:06   ` Kahola, Mika
2025-08-07 10:59   ` Luca Coelho
2025-08-07 11:38     ` Imre Deak
2025-08-07 12:19       ` Jani Nikula
2025-08-07 12:32         ` Imre Deak
2025-08-07 12:50           ` Imre Deak
2025-08-07 13:05             ` Jani Nikula
2025-08-07 13:24               ` Imre Deak
2025-08-07 14:10             ` Luca Coelho
2025-08-05  7:36 ` [PATCH 02/19] drm/i915/icl+/tc: Cache the max lane count value Imre Deak
2025-08-05  9:33   ` [PATCH v2 " Imre Deak
2025-08-07  8:07     ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 03/19] drm/i915/lnl+/tc: Fix max lane count HW readout Imre Deak
2025-08-05  9:33   ` [PATCH v2 " Imre Deak
2025-08-07  8:36     ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 04/19] drm/i915/lnl+/tc: Use the cached max lane count value Imre Deak
2025-08-07  8:49   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 05/19] drm/i915/icl+/tc: Convert AUX powered WARN to a debug message Imre Deak
2025-08-07 12:29   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 06/19] drm/i915/tc: Use the cached max lane count value Imre Deak
2025-08-06 12:02   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 07/19] drm/i915/tc: Move getting the power domain before reading DFLEX registers Imre Deak
2025-08-06 12:56   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 08/19] drm/i915/tc: Move asserting the power state after reading TCSS_DDI_STATUS Imre Deak
2025-08-06 13:22   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 09/19] drm/i915/tc: Add an enum for the TypeC pin assignment Imre Deak
2025-08-07 12:39   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 10/19] drm/i915/tc: Pass pin assignment value around using the pin assignment enum Imre Deak
2025-08-07 12:56   ` Kahola, Mika [this message]
2025-08-05  7:36 ` [PATCH 11/19] drm/i915/tc: Handle pin assignment NONE on all platforms Imre Deak
2025-08-07 12:57   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 12/19] drm/i915/tc: Validate the pin assignment " Imre Deak
2025-08-07 13:08   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 13/19] drm/i915/tc: Unify the way to get " Imre Deak
2025-08-08  6:44   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 14/19] drm/i915/tc: Unify the way to get the max lane count value on MTL+ Imre Deak
2025-08-08  7:32   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 15/19] drm/i915/tc: Handle non-TC encoders when getting the pin assignment Imre Deak
2025-08-08  7:45   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 16/19] drm/i915/tc: Pass intel_tc_port to internal lane mask/count helpers Imre Deak
2025-08-08  8:25   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 17/19] dmc/i915/tc: Report pin assignment NONE in TBT-alt mode Imre Deak
2025-08-08  8:26   ` Kahola, Mika
2025-08-05  7:36 ` [PATCH 18/19] drm/i915/tc: Cache the pin assignment value Imre Deak
2025-08-08  8:27   ` Kahola, Mika
2025-08-05  7:37 ` [PATCH 19/19] drm/i915/tc: Debug print the pin assignment and max lane count Imre Deak
2025-08-08  8:28   ` Kahola, Mika
2025-08-05  7:46 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Patchwork
2025-08-05  7:47 ` ✓ CI.KUnit: success " Patchwork
2025-08-05  8:02 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05  8:49 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-08-05 10:08 ` ✓ Xe.CI.Full: success " Patchwork
2025-08-05 11:41 ` ✗ CI.checkpatch: warning for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Patchwork
2025-08-05 11:42 ` ✓ CI.KUnit: success " Patchwork
2025-08-05 11:57 ` ✗ CI.checksparse: warning " Patchwork
2025-08-05 13:02 ` ✓ Xe.CI.BAT: success " Patchwork
2025-08-05 15:31 ` ✓ Xe.CI.Full: " Patchwork
2025-08-06 11:44 ` [PATCH 00/19] drm/i915/tc: Fix enabled/disconnected DP-alt sink handling Luca Coelho
2025-08-06 11:54   ` Imre Deak
2025-08-06 12:54     ` Luca Coelho
2025-08-06 13:12       ` Imre Deak
2025-08-06 13:16         ` Luca Coelho
     [not found] ` <175439829105.213103.3969215907569188087@1538d3639d33>
2025-08-13 12:43   ` ✗ i915.CI.Full: failure for drm/i915/tc: Fix enabled/disconnected DP-alt sink handling (rev3) Imre Deak

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