RE: [PATCH v3 05/13] drm/xe/psmi: Add Wa_16023683509

["Bhadane, Dnyaneshwar" <dnyaneshwar.bhadane@intel.com>]

> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi@intel.com>
> Sent: Friday, August 8, 2025 11:00 PM
> To: intel-xe@lists.freedesktop.org
> Cc: De Marchi, Lucas <lucas.demarchi@intel.com>; Kumar, Prashanth
> <prashanth.kumar@intel.com>; Bhadane, Dnyaneshwar
> <dnyaneshwar.bhadane@intel.com>; Belgaumkar, Vinay
> <vinay.belgaumkar@intel.com>
> Subject: [PATCH v3 05/13] drm/xe/psmi: Add Wa_16023683509
> 
> From: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> 
> This WA ensures GuC will restore the media MCFG registers at C6 exit.
> 
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>


There is minor conflict while applying this patch. 

Dnyaneshwar 

> ---
> v2:
>  - Enable only when PSMI is enabled
> ---
>  drivers/gpu/drm/xe/xe_guc.c        | 3 +++
>  drivers/gpu/drm/xe/xe_guc_fwif.h   | 1 +
>  drivers/gpu/drm/xe/xe_wa_oob.rules | 2 ++
>  3 files changed, 6 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c index
> cb757a53de856..f55c4a37cfed1 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -219,6 +219,9 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
>  	if (XE_WA(gt, 14018913170))
>  		flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6;
> 
> +	if (XE_WA(gt, 16023683509))
> +		flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6;
> +
>  	return flags;
>  }
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h
> b/drivers/gpu/drm/xe/xe_guc_fwif.h
> index 4dc000c977faf..a169ad0da0d47 100644
> --- a/drivers/gpu/drm/xe/xe_guc_fwif.h
> +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h
> @@ -108,6 +108,7 @@ struct guc_update_exec_queue_policy {
>  #define   GUC_WA_RENDER_RST_RC6_EXIT	BIT(19)
>  #define   GUC_WA_RCS_REGS_IN_CCS_REGS_LIST	BIT(21)
>  #define   GUC_WA_ENABLE_TSC_CHECK_ON_RC6	BIT(22)
> +#define   GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6	BIT(25)
> 
>  #define GUC_CTL_FEATURE			2
>  #define   GUC_CTL_ENABLE_SLPC		BIT(2)
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules
> b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index 303a5e05d9932..fe369e8a01012 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -72,6 +72,8 @@ no_media_l3	MEDIA_VERSION(3000)
>  		MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
>  		MEDIA_VERSION(3000), FUNC(xe_rtp_match_psmi_enabled)
>  		MEDIA_VERSION(3002), FUNC(xe_rtp_match_psmi_enabled)
> +16023683509	MEDIA_VERSION(2000), FUNC(xe_rtp_match_psmi_enabled)
> +		MEDIA_VERSION(3000), GRAPHICS_STEP(A0, B0),
> +FUNC(xe_rtp_match_psmi_enabled)
> 
>  # SoC workaround - currently applies to all platforms with the following  #
> primary GT GMDID
> 
> --
> 2.50.1