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From: Raag Jadav <raag.jadav@intel.com>
To: "Nilawar, Badal" <badal.nilawar@intel.com>
Cc: lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
	intel-xe@lists.freedesktop.org, anshuman.gupta@intel.com,
	riana.tauro@intel.com
Subject: Re: [PATCH v1 1/2] drm/xe/debugfs: Expose PCIe Gen5 update telemetry
Date: Thu, 3 Apr 2025 06:38:44 +0300	[thread overview]
Message-ID: <Z-4CxE_CDYHk_nxS@black.fi.intel.com> (raw)
In-Reply-To: <2cdb9c41-6b0f-4399-b2c5-f9651a0b98a8@intel.com>

On Wed, Apr 02, 2025 at 11:54:26PM +0530, Nilawar, Badal wrote:
> On 31-03-2025 19:53, Raag Jadav wrote:
> > Expose debugfs telemetry required for PCIe Gen5 firmware update for
> > discrete GPUs.
> > 
> > Signed-off-by: Raag Jadav <raag.jadav@intel.com>
> > ---
> >   drivers/gpu/drm/xe/xe_debugfs.c   | 93 +++++++++++++++++++++++++++++++
> >   drivers/gpu/drm/xe/xe_pcode_api.h |  4 ++
> >   2 files changed, 97 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_debugfs.c b/drivers/gpu/drm/xe/xe_debugfs.c
> > index d0503959a8ed..67c941abf4fe 100644
> > --- a/drivers/gpu/drm/xe/xe_debugfs.c
> > +++ b/drivers/gpu/drm/xe/xe_debugfs.c
> > @@ -17,6 +17,9 @@
> >   #include "xe_gt_debugfs.h"
> >   #include "xe_gt_printk.h"
> >   #include "xe_guc_ads.h"
> > +#include "xe_mmio.h"
> > +#include "xe_pcode_api.h"
> > +#include "xe_pcode.h"
> >   #include "xe_pm.h"
> >   #include "xe_pxp_debugfs.h"
> >   #include "xe_sriov.h"
> > @@ -191,6 +194,89 @@ static const struct file_operations wedged_mode_fops = {
> >   	.write = wedged_mode_set,
> >   };
> > +/**
> > + * DOC: PCIe Gen5 Update Limitations
> > + *
> > + * Default link speed of discrete GPUs is determined by FIT parameters stored
> > + * in their flash memory, which are subject to override through user initiated
> > + * firmware updates. It has been observed that devices configured with PCIe
> > + * Gen5 as their default speed can come across link quality issues due to host
> > + * or motherboard limitations and may have to auto-downspeed to PCIe Gen4 when
> > + * faced with unstable link at Gen5. The users are required to ensure that the
> > + * device is capable of auto-downspeeding to PCIe Gen4 before pushing the image
> > + * with Gen5 as default configuration. This can be done by reading
> > + * ``pcie_gen4_downspeed_capable`` debugfs entry, which will denote PCIe Gen4
> > + * auto-downspeed capability of the device with boolean output value of ``0``
> > + * or ``1``, meaning `incapable` or `capable` respectively.
> > + *
> > + * .. code-block:: shell
> > + *
> > + *    $ cat /sys/kernel/debug/dri/<N>/pcie_gen4_downspeed_capable
> 
> Why not on sysfs?
> 
> So how about simply using "downgrade" instead of "downspeed" through out the
> code?

It might be confused between PCI link and firmware.

Raag

  reply	other threads:[~2025-04-03  3:38 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-03-31 14:23 [PATCH v1 0/2] DGFX PCIe Gen5 update telemetry and usage Raag Jadav
2025-03-31 14:23 ` [PATCH v1 1/2] drm/xe/debugfs: Expose PCIe Gen5 update telemetry Raag Jadav
2025-03-31 14:52   ` Lucas De Marchi
2025-03-31 15:23     ` Rodrigo Vivi
2025-03-31 15:15   ` Rodrigo Vivi
2025-04-02 18:24   ` Nilawar, Badal
2025-04-03  3:38     ` Raag Jadav [this message]
2025-03-31 14:23 ` [PATCH v1 2/2] drm/xe/doc: Wire up PCIe Gen5 update limitations Raag Jadav
2025-03-31 15:24   ` Rodrigo Vivi
2025-04-02 10:22     ` Raag Jadav
2025-03-31 14:29 ` ✓ CI.Patch_applied: success for DGFX PCIe Gen5 update telemetry and usage Patchwork
2025-03-31 14:30 ` ✗ CI.checkpatch: warning " Patchwork
2025-03-31 14:31 ` ✓ CI.KUnit: success " Patchwork
2025-03-31 14:47 ` ✓ CI.Build: " Patchwork
2025-03-31 14:50 ` ✓ CI.Hooks: " Patchwork
2025-03-31 14:51 ` ✓ CI.checksparse: " Patchwork
2025-03-31 15:37 ` ✓ Xe.CI.BAT: " Patchwork
2025-03-31 16:54 ` ✗ Xe.CI.Full: failure " Patchwork

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