From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0E86AC0218B for ; Fri, 24 Jan 2025 11:39:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CAC5C10E7EC; Fri, 24 Jan 2025 11:39:15 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="Pv50HaJq"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.8]) by gabe.freedesktop.org (Postfix) with ESMTPS id A1FCB10E7EC; Fri, 24 Jan 2025 11:39:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1737718755; x=1769254755; h=date:from:to:cc:subject:message-id:references: mime-version:content-transfer-encoding:in-reply-to; bh=1WFnZE0g5Od//th/kGnu+9lebBp6E93P0h5suYoT6KM=; b=Pv50HaJqucLQsHpdM3jN6+XqyRZRmCVCyLjad2GqzgvFrAhP0heUi24C 9g1NRb/Ur7A65sVS+8Yy7mxucjTj3CU3sXTQbyERe4hCx1dKreEsz75PZ WIFYdcWZ+scshtWenm5pnkOUlYkEJB9Mn4nwh7TqUUG0j0uBMwbonB9Tk khLsj2QFn2WoN8xMdg3B84XqRXiTKZWZkwMVNmPcON7Gdp+rvZqPhfntZ 4tKmhqEhzR3gvCqhrUZ89mqrX5qB92/LpCsoa0T7Cwz+i14j+nWu6Rg1N +hUxIbr3DBxChyZ25FQkjMwDzUjvpQcRL9k5m8GAiMlnisJDgDISz7/Ad w==; X-CSE-ConnectionGUID: ZaWQ44EFR8q9cuLzWZeEhQ== X-CSE-MsgGUID: CvvCeFVYS+OpXbwKl+4KdQ== X-IronPort-AV: E=McAfee;i="6700,10204,11325"; a="55795624" X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="55795624" Received: from fmviesa008.fm.intel.com ([10.60.135.148]) by fmvoesa102.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Jan 2025 03:39:15 -0800 X-CSE-ConnectionGUID: oN5k/cWLSFOwjV5A7zj/dQ== X-CSE-MsgGUID: G+jaVTRVQPSlzf9GTmQPzA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,231,1732608000"; d="scan'208";a="107873470" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 24 Jan 2025 03:39:12 -0800 Received: by stinkbox (sSMTP sendmail emulation); Fri, 24 Jan 2025 13:39:10 +0200 Date: Fri, 24 Jan 2025 13:39:10 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Jouni =?iso-8859-1?Q?H=F6gander?= Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, animesh.manna@intel.com, ville.syrjala@intel.com Subject: Re: [PATCH v4 11/13] drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled Message-ID: References: <20250124105625.822459-1-jouni.hogander@intel.com> <20250124105625.822459-12-jouni.hogander@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250124105625.822459-12-jouni.hogander@intel.com> X-Patchwork-Hint: comment X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, Jan 24, 2025 at 12:56:22PM +0200, Jouni Högander wrote: > PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On > wake-up scanline counting starts from vblank_start - 1. We don't know if > wake-up is already ongoing when evasion starts. In worst case PIPEDSL could > start reading valid value right after checking the scanline. In this > scenario we wouldn't have enough time to write all registers. To tackle > this evade scanline 0 as well. As a drawback we have 1 frame delay in flip > when waking up. > > Signed-off-by: Jouni Högander > --- > drivers/gpu/drm/i915/display/intel_dsb.c | 12 ++++++++++++ > 1 file changed, 12 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_dsb.c b/drivers/gpu/drm/i915/display/intel_dsb.c > index bb77ded8bf726..914f0be4491c4 100644 > --- a/drivers/gpu/drm/i915/display/intel_dsb.c > +++ b/drivers/gpu/drm/i915/display/intel_dsb.c > @@ -528,6 +528,18 @@ void intel_dsb_vblank_evade(struct intel_atomic_state *state, > int latency = intel_usecs_to_scanlines(&crtc_state->hw.adjusted_mode, 20); > int start, end; > > + /* > + * PIPEDSL is reading as 0 when in SRDENT(PSR1) or DEEP_SLEEP(PSR2). On > + * wake-up scanline counting starts from vblank_start - 1. We don't know > + * if wake-up is already ongoing when evasion starts. In worst case > + * PIPEDSL could start reading valid value right after checking the > + * scanline. In this scenario we wouldn't have enough time to write all > + * registers. To tackle this evade scanline 0 as well. As a drawback we > + * have 1 frame delay in flip when waking up. > + */ > + if (crtc_state->has_psr && !crtc_state->has_panel_replay) What's the deal with panel replay here? > + intel_dsb_wait_scanline_out(state, dsb, 0, 0); This needs to be a raw intel_dsb_emit_wait_dsl(dsb, DSB_OPCODE_WAIT_DSL_OUT, 0, 0) because we need to evade the hw scanline 0. What the software thinks is scanline 0 is a bit different (see scanline_offset). > + > if (pre_commit_is_vrr_active(state, crtc)) { > int vblank_delay = intel_vrr_vblank_delay(crtc_state); > > -- > 2.43.0 -- Ville Syrjälä Intel