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d="scan'208";a="132889148" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by fmviesa002-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2025 05:44:32 -0800 Date: Fri, 31 Jan 2025 15:45:29 +0200 From: Imre Deak To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org Subject: Re: [PATCH 02/14] drm/i915/dp: Add intel_dp_dsc_bpp_step_x16() helper to get DSC BPP precision Message-ID: References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, Jan 31, 2025 at 02:49:55PM +0200, Jani Nikula wrote: > Add a platform independent helper for getting the supported DSC BPP step > for the link. > > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/display/intel_dp.c | 21 ++++++++++++++++----- > 1 file changed, 16 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c > index ecf192262eb9..a7a5bb2075da 100644 > --- a/drivers/gpu/drm/i915/display/intel_dp.c > +++ b/drivers/gpu/drm/i915/display/intel_dp.c > @@ -2054,6 +2054,21 @@ static int dsc_src_max_compressed_bpp(struct intel_dp *intel_dp) > return 27; > } > > +/* > + * Note: for pre-13 display you still need to check the validity of each step. > + */ > +static int intel_dp_dsc_bpp_step_x16(const struct intel_connector *connector) Nit: there was a guideline that these KMS objects should be passed around via non-const pointers vs. state pointers which should be const if possible. > +{ > + struct intel_display *display = to_intel_display(connector); > + u8 incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); > + > + if (DISPLAY_VER(display) < 14 || !incr) > + return fxp_q4_from_int(1); > + > + /* fxp q4 */ > + return 16 / incr; Nit: could've been fxp_q4_from_int(1) / incr; Regardless of the nits, patch looks ok: Reviewed-by: Imre Deak > +} > + > /* > * From a list of valid compressed bpps try different compressed bpp and find a > * suitable link configuration that can support it. > @@ -2110,16 +2125,12 @@ xelpd_dsc_compute_link_config(struct intel_dp *intel_dp, > int timeslots) > { > struct intel_display *display = to_intel_display(intel_dp); > - u8 bppx16_incr = drm_dp_dsc_sink_bpp_incr(connector->dp.dsc_dpcd); > int output_bpp = intel_dp_output_bpp(pipe_config->output_format, pipe_bpp); > u16 compressed_bppx16; > u8 bppx16_step; > int ret; > > - if (DISPLAY_VER(display) < 14 || bppx16_incr <= 1) > - bppx16_step = 16; > - else > - bppx16_step = 16 / bppx16_incr; > + bppx16_step = intel_dp_dsc_bpp_step_x16(connector); > > /* Compressed BPP should be less than the Input DSC bpp */ > dsc_max_bpp = min(dsc_max_bpp << 4, (output_bpp << 4) - bppx16_step); > -- > 2.39.5 >