From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 29EE2C02192 for ; Wed, 5 Feb 2025 14:51:10 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D29CE10E1E4; Wed, 5 Feb 2025 14:51:09 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="bHFuu5QU"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.11]) by gabe.freedesktop.org (Postfix) with ESMTPS id 866CA10E1E4; Wed, 5 Feb 2025 14:51:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1738767069; x=1770303069; h=date:from:to:cc:subject:message-id:reply-to:references: mime-version:in-reply-to; bh=EY66mrNLtPH76VnatY6wzkEwmLd8oTFleXbC9MHTUhk=; b=bHFuu5QUQZu3tZxUWY+gWo+RnIwOMau+TLoRmwJOVwaPU4VWT1O0xO1j QFFFcnvnxa2h67tVlJcwIGWsrzs1DVFv0m3Bh+vQ9QFzupv8o57tP5NJ7 RcI0XNQnETBDdBDi5RV0pOaMV+cWulKKuCevVNnul29kv9iTnPSZyrkz8 7o1Iz5d1xaCbDM1NaDMhHqUkxOzs5GCbPfW5uY2LVFUUbhqW4ujiOXq6H MDw1R87BhoQ04ATBrte1rXwS2v0iZlSJqP4Qn4LIZLXJcFVJBPj4WM0zb tU/gbQeU26xn3TKZrcFMozN4dP4yJpS8PSewKH/dQWi0bPMT08jGyyAWG w==; X-CSE-ConnectionGUID: l+IbGwzIRPSLWoBOQzoYSg== X-CSE-MsgGUID: O9p2Z0FMStGueVEqkBC4MA== X-IronPort-AV: E=McAfee;i="6700,10204,11336"; a="49951166" X-IronPort-AV: E=Sophos;i="6.13,261,1732608000"; d="scan'208";a="49951166" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa105.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2025 06:51:08 -0800 X-CSE-ConnectionGUID: V7Vx2SX9TFWZ/5iylrbpAA== X-CSE-MsgGUID: cCeKz1SPTP2JEo5FPzezmQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,261,1732608000"; d="scan'208";a="110704727" Received: from ideak-desk.fi.intel.com ([10.237.72.78]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2025 06:51:06 -0800 Date: Wed, 5 Feb 2025 16:52:04 +0200 From: Imre Deak To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, Imre Deak Subject: Re: [PATCH 11/17] drm/i915/ddi: Sanitize DDI_BUF_CTL register definitions Message-ID: References: <20250129200221.2508101-1-imre.deak@intel.com> <20250129200221.2508101-12-imre.deak@intel.com> <87cyfw4kqv.fsf@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <87cyfw4kqv.fsf@intel.com> X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: imre.deak@intel.com Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, Feb 05, 2025 at 02:52:08PM +0200, Jani Nikula wrote: > On Wed, 29 Jan 2025, Imre Deak wrote: > > From: Imre Deak > > > > Align the DDI_BUF_CTL register flag definitions with how this is done > > elsewhere. > > > > Signed-off-by: Imre Deak > > --- > > drivers/gpu/drm/i915/i915_reg.h | 22 ++++++++++++---------- > > 1 file changed, 12 insertions(+), 10 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > > index 7fe4e71fc08ec..5cee6a96270af 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -3621,27 +3621,29 @@ enum skl_power_gate { > > #define _DDI_BUF_CTL_B 0x64100 > > /* Known as DDI_CTL_DE in MTL+ */ > > #define DDI_BUF_CTL(port) _MMIO_PORT(port, _DDI_BUF_CTL_A, _DDI_BUF_CTL_B) > > -#define DDI_BUF_CTL_ENABLE (1 << 31) > > +#define DDI_BUF_CTL_ENABLE REG_BIT(31) > > #define XE2LPD_DDI_BUF_D2D_LINK_ENABLE REG_BIT(29) > > #define XE2LPD_DDI_BUF_D2D_LINK_STATE REG_BIT(28) > > -#define DDI_BUF_TRANS_SELECT(n) ((n) << 24) > > -#define DDI_BUF_EMP_MASK (0xf << 24) > > -#define DDI_BUF_PHY_LINK_RATE(r) ((r) << 20) > > +#define DDI_BUF_EMP_MASK REG_GENMASK(27, 24) > > +#define DDI_BUF_TRANS_SELECT(n) REG_FIELD_PREP(DDI_BUF_EMP_MASK, n) > > +#define DDI_BUF_PHY_LINK_RATE_MASK REG_GENMASK(23, 20) > > +#define DDI_BUF_PHY_LINK_RATE(r) REG_FIELD_PREP(DDI_BUF_PHY_LINK_RATE_MASK, r) > > Ville has been advocating wrapping macro arguments in parens also in > these cases, and I'm starting to lean that way too. That is parens around 'r' above, ok I suppose that's more robust (in case the called macros don't use parens when required). > Other than that, > > Reviewed-by: Jani Nikula > > > > #define DDI_BUF_PORT_DATA_MASK REG_GENMASK(19, 18) > > #define DDI_BUF_PORT_DATA_10BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 0) > > #define DDI_BUF_PORT_DATA_20BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 1) > > #define DDI_BUF_PORT_DATA_40BIT REG_FIELD_PREP(DDI_BUF_PORT_DATA_MASK, 2) > > -#define DDI_BUF_PORT_REVERSAL (1 << 16) > > +#define DDI_BUF_PORT_REVERSAL REG_BIT(16) > > #define DDI_BUF_LANE_STAGGER_DELAY_MASK REG_GENMASK(15, 8) > > #define DDI_BUF_LANE_STAGGER_DELAY(symbols) REG_FIELD_PREP(DDI_BUF_LANE_STAGGER_DELAY_MASK, \ > > symbols) > > -#define DDI_BUF_IS_IDLE (1 << 7) > > +#define DDI_BUF_IS_IDLE REG_BIT(7) > > #define DDI_BUF_CTL_TC_PHY_OWNERSHIP REG_BIT(6) > > -#define DDI_A_4_LANES (1 << 4) > > -#define DDI_PORT_WIDTH(width) (((width) == 3 ? 4 : ((width) - 1)) << 1) > > -#define DDI_PORT_WIDTH_MASK (7 << 1) > > +#define DDI_A_4_LANES REG_BIT(4) > > +#define DDI_PORT_WIDTH_MASK REG_GENMASK(3, 1) > > +#define DDI_PORT_WIDTH(width) REG_FIELD_PREP(DDI_PORT_WIDTH_MASK, \ > > + (width) == 3 ? 4 : (width) - 1) > > #define DDI_PORT_WIDTH_SHIFT 1 > > -#define DDI_INIT_DISPLAY_DETECTED (1 << 0) > > +#define DDI_INIT_DISPLAY_DETECTED REG_BIT(0) > > > > /* DDI Buffer Translations */ > > #define _DDI_BUF_TRANS_A 0x64E00 > > -- > Jani Nikula, Intel