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d="scan'208";a="114382183" Received: from stinkpipe.fi.intel.com (HELO stinkbox) ([10.237.72.74]) by fmviesa008.fm.intel.com with SMTP; 17 Feb 2025 10:06:52 -0800 Received: by stinkbox (sSMTP sendmail emulation); Mon, 17 Feb 2025 20:06:52 +0200 Date: Mon, 17 Feb 2025 20:06:52 +0200 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= To: Ankit Nautiyal Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org, jani.nikula@linux.intel.com, mitulkumar.ajitkumar.golani@intel.com Subject: Re: [PATCH 05/19] drm/i915/vrr: Track vrr.enable only for variable timing Message-ID: References: <20250214121130.1808451-1-ankit.k.nautiyal@intel.com> <20250214121130.1808451-6-ankit.k.nautiyal@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20250214121130.1808451-6-ankit.k.nautiyal@intel.com> X-Patchwork-Hint: comment X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Fri, Feb 14, 2025 at 05:41:15PM +0530, Ankit Nautiyal wrote: > Since CMRR is now disabled, use the flag vrr.enable to tracks if vrr timing > generator is used with variable timings. > > Avoid setting vrr.enable for CMRR and adjust readout to not set vrr.enable > when vmax == vmin == flipline (fixed refresh rate timing). > > Signed-off-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 0ee7fb0362ce..efa2aa284285 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -226,7 +226,6 @@ cmrr_get_vtotal(struct intel_crtc_state *crtc_state, bool video_mode_required) > static > void intel_vrr_compute_cmrr_timings(struct intel_crtc_state *crtc_state) > { > - crtc_state->vrr.enable = true; > crtc_state->cmrr.enable = true; > /* > * TODO: Compute precise target refresh rate to determine > @@ -528,6 +527,14 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > intel_de_write(display, TRANS_PUSH(display, cpu_transcoder), 0); > } > > +static > +bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state) > +{ > + return crtc_state->vrr.flipline && > + crtc_state->vrr.flipline == crtc_state->vrr.vmax && > + crtc_state->vrr.flipline == crtc_state->vrr.vmin; crtc_state->vrr.flipling == intel_vrr_vmin_flipline(...) to make this also do the right thing for icl/tgl. > +} > + > void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > { > struct intel_display *display = to_intel_display(crtc_state); > @@ -537,7 +544,6 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > trans_vrr_ctl = intel_de_read(display, > TRANS_VRR_CTL(display, cpu_transcoder)); > > - crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE; > if (HAS_CMRR(display)) > crtc_state->cmrr.enable = (trans_vrr_ctl & VRR_CTL_CMRR_ENABLE); > > @@ -577,6 +583,9 @@ void intel_vrr_get_config(struct intel_crtc_state *crtc_state) > } > } > > + crtc_state->vrr.enable = trans_vrr_ctl & VRR_CTL_VRR_ENABLE && > + !intel_vrr_is_fixed_rr(crtc_state); > + > if (crtc_state->vrr.enable) > crtc_state->mode_flags |= I915_MODE_FLAG_VRR; > } > -- > 2.45.2 -- Ville Syrjälä Intel