Re: [Intel-xe] [PATCH] drm/xe: Fix duplicated setting for register 0x6604

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Mar 06, 2023 at 01:24:50PM -0800, Lucas De Marchi wrote:
> The following warning shows up for TGL:
> 
> 		[drm:xe_reg_sr_add [xe]] *ERROR* Discarding save-restore reg 6604 (clear: 00ff0000, set: 00040000, masked: no): ret=-22
> 		[drm:xe_reg_sr_add [xe]] *ERROR* Discarding save-restore reg 6604 (clear: 00ff0000, set: 00040000, masked: no): ret=-22
> 
> That is because the same register is being set both by the WAs and the
> tunings. Like was done in i915, prefer the tuning over the workaround
> since that is applicable for more platforms. Also fix the tuning: it
> was incorrectly using the MCR version of the register, but that only
> became true in XEHP.
> 
> References: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/233
> Reported-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 -
>  drivers/gpu/drm/xe/xe_tuning.c       | 11 ++++++-----
>  drivers/gpu/drm/xe/xe_wa.c           | 10 +++-------
>  3 files changed, 9 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 4d0f09cd447c..c025c6dbf3a9 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -70,7 +70,6 @@
>  #define XEHP_FLAT_CCS_BASE_ADDR			MCR_REG(0x4910)
>  
>  #define GEN12_FF_MODE2				_MMIO(0x6604)
> -#define XEHP_FF_MODE2				MCR_REG(0x6604)
>  #define   FF_MODE2_GS_TIMER_MASK		REG_GENMASK(31, 24)
>  #define   FF_MODE2_GS_TIMER_224			REG_FIELD_PREP(FF_MODE2_GS_TIMER_MASK, 224)
>  #define   FF_MODE2_TDS_TIMER_MASK		REG_GENMASK(23, 16)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index 624b257ecfbc..2861a014c85c 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -24,11 +24,12 @@ static const struct xe_rtp_entry gt_tunings[] = {
>  };
>  
>  static const struct xe_rtp_entry lrc_tunings[] = {
> -	{ XE_RTP_NAME("1604555607"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION(1200)),
> -	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(XEHP_FF_MODE2,
> -						FF_MODE2_TDS_TIMER_MASK,
> -						FF_MODE2_TDS_TIMER_128))
> +	{ XE_RTP_NAME("Tuning: ganged timer, also known as 16011163337"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
> +	  /* read verification is ignored due to 1608008084. */
> +	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2,
> +						FF_MODE2_GS_TIMER_MASK,
> +						FF_MODE2_GS_TIMER_224))
>  	},
>  	{}
>  };
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index df72b15dfeb0..71e9e1a111f8 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -265,13 +265,9 @@ static const struct xe_rtp_entry lrc_was[] = {
>  				   GEN9_PREEMPT_GPGPU_THREAD_GROUP_LEVEL,
>  				   XE_RTP_ACTION_FLAG(MASKED_REG)))
>  	},
> -	{ XE_RTP_NAME("16011163337"),
> -	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
> -	  /* read verification is ignored due to 1608008084. */
> -	  XE_RTP_ACTIONS(FIELD_SET_NO_READ_MASK(GEN12_FF_MODE2,
> -						FF_MODE2_GS_TIMER_MASK,
> -						FF_MODE2_GS_TIMER_224))
> -	},
> +
> +	/* DG1 */
> +
>  	{ XE_RTP_NAME("1409044764"),
>  	  XE_RTP_RULES(PLATFORM(DG1)),
>  	  XE_RTP_ACTIONS(CLR(GEN11_COMMON_SLICE_CHICKEN3,
> -- 
> 2.39.0
>