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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?iso-8859-1?Q?qgofkkpTgdlQeww2IJccXhOekhvEsh5SMmDSzaoj2Sp26wd1B1c7AFFfOr?= =?iso-8859-1?Q?pzDpQoAUVWtvuO/ktpW0illpiRbBbZE42CWB4bRxpAQeV8wXQFHm0vAFF/?= =?iso-8859-1?Q?UwdPnOwAE2GabMtErx6qhvn9tUwfRN8HJwQHT/FuJ+sdwItBiGkul0im43?= =?iso-8859-1?Q?ohPcjwtSfa4t4TMz3/vzHPmzJ5f8My0c3cQdARpSKlVeFXcm7fqL1LSL9t?= =?iso-8859-1?Q?uuXH0z6yiFiUMDWIgO6/c8jwN2VEJEtQ45/RrjbHx3+DF3igHfbGzWQRok?= =?iso-8859-1?Q?c04KRRFRSB5Ep3mgvXclIK3jgiqYCoiqyfEbQ4dzxhqxbMfALfOdPqrbe/?= =?iso-8859-1?Q?LYdKjD/ajinQu9TSiL3yEcXNVgZgNEphwGtaduD2uGU7ziuw1wxgLw873N?= =?iso-8859-1?Q?TSm/zRkYSfu/GDklr7/67ATZLAZb8yGeQYIQF15zuC+hIIh9oSCvjjBGOc?= =?iso-8859-1?Q?j4TFfXwHOePrzoFuqsx5h5XEp8LolZGVHFdBbrp3A69OgAmhguJFJPIQfP?= =?iso-8859-1?Q?G7T6p7irtv7cuf4Ja60wvThnWFxWzT5jysTZ4AdgGNlIkZ/OLqdIlgPeIf?= =?iso-8859-1?Q?GJvSVQwr2OJ1yW05rdJ+fNOz9KcoiCoOr5d7BtLtBF/z4U7O6YZ/OHaGiO?= =?iso-8859-1?Q?SDZoAw5GqgPeVAUzpFOiKrodVPTpYxN3i3zB3XjvtPoScJ+Fl+MFH2tDuV?= =?iso-8859-1?Q?1BLGVrmGkpynHSrZQA99v2F6l5usDL/THzMP3QZ3FJnUJ2zOGmgXLqi50p?= =?iso-8859-1?Q?DBZS+oUTqcTqlM3yaFGwizG4HgLr0Ifb4cziSRWIQ8G2pEwwq6gACu1Til?= =?iso-8859-1?Q?gsgfBTqLSbwFc/K1L/2q6S3VxS8OYjC9v1ZWbwWeTs3ecO24WT0+prk//M?= =?iso-8859-1?Q?ZD/zu9RUsn9q281CGi5wNRb1tgIuJmPr42Os/sAv/N8RZ7Q58yPV5uQv+c?= =?iso-8859-1?Q?aamlVrZ22jwS2xK3iN8/1mUV+kJh3SsZq2W41Ayhzu8v3vKrdiCoPRKiRY?= =?iso-8859-1?Q?h3Sjzs/TPOPCCpfdv7gPG44dQWEVZ9qiyxM2LvV3+cmjedGW/htplKBhoZ?= =?iso-8859-1?Q?vZbrs+5G9zwdNWy1LkLJ8WdKwcfazpcCUbi0T2glx9wX/KJLK8usSqPGn/?= =?iso-8859-1?Q?7XPF+WnLx5d+0HnN/fB+rQ6UlLy0w9cTcL7oQAxxXfcASwMJJBICxZJqV2?= =?iso-8859-1?Q?EdTWq9X9P1PxtWjfk1vUmq24/tdX9i064uuV1/xudSxz1LplJmXMOgrbug?= =?iso-8859-1?Q?8ntR+3NnY34vDPp3YV2nuffcjOc0X8rKxzDlidDMNxGrKgSRHt5PHBmpsx?= =?iso-8859-1?Q?F2fmDa5xlO8lQ/uMkTl9hR1IdPrnCIX4UWFdJxvzJFj4Q7z8nKcbu3CQoq?= =?iso-8859-1?Q?N0zUmPdW2+6Dzxxs9T5NRQIrJ0vbUiUw1oLTEdUz/HjPG15+NT/YWdVfFq?= =?iso-8859-1?Q?eCHwhwVt1NlIXBNZTxqIWSUGrd19jp5M6kyXNpptQIP+/4PnyrJww5b1r1?= =?iso-8859-1?Q?YwL42jyUpSRJ8HOlrpiUMmORVk+9/7E2+4BOWgCe1AOWbU+80XbXZifDHa?= =?iso-8859-1?Q?4rfXfu3aJTDqT1kOb8iaSeq4FMDhbSsQj3YX5vkQLYUIm1zY9NLVtNKp0U?= =?iso-8859-1?Q?YquKxwCzK4D3xNdBDu9BDoNWGqzCbdJPkAVTSxEru7t9lPs3QruhdpxA?= =?iso-8859-1?Q?=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: 350a76f7-7148-4b6d-4b78-08db690181b1 X-MS-Exchange-CrossTenant-AuthSource: PH7PR11MB6522.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jun 2023 15:52:20.2906 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HLDVVirYdx9e8jRb2nYK+8683+siHnAq0CZMs5cuD0A81B47zzuWHNKMS8bvOyMhjkJU9fFeRTQuT1J+0oCSIg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR11MB7504 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH 1/2] drm/xe: Invalidate TLB also on bind if in scratch page mode X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, Jun 07, 2023 at 07:47:28PM +0200, Thomas Hellström wrote: > For scratch table mode we need to cover the case where a scratch PTE might > have been pre-fetched and cached and used instead of that of the newly > bound vma. > For compute vms, invalidate TLB globally using GuC before signalling > bind complete. For !long-running vms, invalidate TLB at batch start. > > Also document how TLB invalidation works. > > Signed-off-by: Thomas Hellström > --- > drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 1 + > drivers/gpu/drm/xe/xe_pt.c | 17 +++++++++++++++-- > drivers/gpu/drm/xe/xe_ring_ops.c | 15 ++++++++++++--- > 3 files changed, 28 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h > index 0f9c5b0b8a3b..d2d41f717525 100644 > --- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h > +++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h > @@ -73,6 +73,7 @@ > #define PIPE_CONTROL_STORE_DATA_INDEX (1<<21) > #define PIPE_CONTROL_CS_STALL (1<<20) > #define PIPE_CONTROL_GLOBAL_SNAPSHOT_RESET (1<<19) > +#define PIPE_CONTROL_TLB_INVALIDATE (1<<18) > #define PIPE_CONTROL_PSD_SYNC (1<<17) > #define PIPE_CONTROL_QW_WRITE (1<<14) > #define PIPE_CONTROL_DEPTH_STALL (1<<13) > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c > index bef265715000..e817fa9fe65e 100644 > --- a/drivers/gpu/drm/xe/xe_pt.c > +++ b/drivers/gpu/drm/xe/xe_pt.c > @@ -1297,7 +1297,20 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > xe_vm_dbg_print_entries(tile_to_xe(tile), entries, num_entries); > > - if (rebind && !xe_vm_no_dma_fences(vma->vm)) { > + /* > + * If rebind, we have to invalidate TLB on !LR vms to invalidate > + * cached PTEs point to freed memory. on LR vms this is done > + * automatically when the context is re-enabled by the rebind worker, > + * or in fault mode it was invalidated on PTE zapping. > + * > + * If !rebind, and scratch enabled VMs, there is a chance the scratch > + * PTE is already cached in the TLB so it needs to be invalidated. > + * on !LR VMs this is done in the ring ops preceding a batch, but on > + * non-faulting LR, in particular on user-space batch buffer chaining, > + * it needs to be done here. > + */ > + if ((rebind && !xe_vm_no_dma_fences(vm)) || > + (!rebind && vm->scratch_bo[tile->id] && xe_vm_in_compute_mode(vm))) { > ifence = kzalloc(sizeof(*ifence), GFP_KERNEL); > if (!ifence) > return ERR_PTR(-ENOMEM); > @@ -1313,7 +1326,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > LLIST_HEAD(deferred); > > /* TLB invalidation must be done before signaling rebind */ > - if (rebind && !xe_vm_no_dma_fences(vma->vm)) { > + if (ifence) { > int err = invalidation_fence_init(tile->primary_gt, ifence, fence, > vma); > if (err) { > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c > index 2deee7a2bb14..c20fe41c0729 100644 > --- a/drivers/gpu/drm/xe/xe_ring_ops.c > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c > @@ -15,6 +15,7 @@ > #include "xe_macros.h" > #include "xe_sched_job.h" > #include "xe_vm_types.h" > +#include "xe_vm.h" > > /* > * 3D-related flags that can't be set on _engines_ that lack access to the 3D > @@ -107,7 +108,7 @@ static int emit_flush_invalidate(u32 flag, u32 *dw, int i) > return i; > } > > -static int emit_pipe_invalidate(u32 mask_flags, u32 *dw, int i) > +static int emit_pipe_invalidate(u32 mask_flags, u32 extra_flags, u32 *dw, int i) > { > u32 flags = PIPE_CONTROL_CS_STALL | > PIPE_CONTROL_COMMAND_CACHE_INVALIDATE | > @@ -117,7 +118,8 @@ static int emit_pipe_invalidate(u32 mask_flags, u32 *dw, int i) > PIPE_CONTROL_CONST_CACHE_INVALIDATE | > PIPE_CONTROL_STATE_CACHE_INVALIDATE | > PIPE_CONTROL_QW_WRITE | > - PIPE_CONTROL_STORE_DATA_INDEX; > + PIPE_CONTROL_STORE_DATA_INDEX | > + extra_flags; > > flags &= ~mask_flags; > > @@ -250,14 +252,21 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, > struct xe_gt *gt = job->engine->gt; > struct xe_device *xe = gt_to_xe(gt); > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); > + struct xe_vm *vm = job->engine->vm; > u32 mask_flags = 0; > + u32 extra_flags = 0; > > dw[i++] = preparser_disable(true); > if (lacks_render) > mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; > else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) > mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS; > - i = emit_pipe_invalidate(mask_flags, dw, i); > + > + /* See xe_pt.c for a discussion on TLB invalidations. */ > + if (!xe_vm_no_dma_fences(vm) && vm->scratch_bo[gt_to_tile(gt)->id]) > + extra_flags = PIPE_CONTROL_TLB_INVALIDATE; I think we need a similar if statement + emit_flush_invalidate call in the functions that emit jobs for different classes too, right? e.g. emit_job_gen12_copy, emit_job_gen12_video Matt > + > + i = emit_pipe_invalidate(mask_flags, extra_flags, dw, i); > > /* hsdes: 1809175790 */ > if (has_aux_ccs(xe)) > -- > 2.39.2 >