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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?lUib7GUn0HU+Cz+ZSfAFXRBezz/O8/fQUbqdTsLuzJFBGtnTaPOci7C2C15X?= =?us-ascii?Q?n8IJKngi1uT/RPs7PDtR27KBznx6DBmdWq/mCBSVHu0f+oYpZFrHLNgqUQ7y?= =?us-ascii?Q?0ucHGTUNijLpWjS0B5gu+uk9X+YheEJAHyd7iW3Y2MNWUxZZmeNnzaihqHL+?= =?us-ascii?Q?WFZCbPcpb4RX7SHH8bRvh4mrkuVFIo5wXmdRJsARpcWH8cfRmXoFwJSvh+kh?= =?us-ascii?Q?x5si0CoxVvPsrIRmXLWK3qeKFN+eela0IJhrgcGmCnjDD7FaYYHS5G6FcSo2?= =?us-ascii?Q?cPMYWUW7ttAAuG8KTTWv/VHwlVbAboCzoaBOhOWEBqu6GDQlr7yQvHV+X6SH?= =?us-ascii?Q?WS085FlV4d5A4G2eoUNAi7GeyOKwQ4gsxutbY6pfm8HqkMLYYWrf9LPROqy7?= =?us-ascii?Q?rqlqx83ko8p633W9EwhNhcGcyYiZZAYQpOYgMuaWUBwv95qGQgoujvGS8ffY?= =?us-ascii?Q?s1dcoY44ixGxaRhHpI1nI6nkn8GC10tOL6KoMrlUgu8BPfv+Gl6FqC6fFEiZ?= =?us-ascii?Q?ZSnLLGgSgmri0jBQqkzFio3d0qEkUhhMWdydh/x+zGggHQ3Ks48sPRUfed2Z?= =?us-ascii?Q?Gcbv8txasKK5QUiGe1P8PUppyyqFidfqMCStLodCcMMMcky5FVTma8DbrMV0?= =?us-ascii?Q?UJcpJ+hy+TD6Nhv7/CmDavo2RPrMO3rfUkHoFoG11309ReWoiHlNFajbgmZM?= =?us-ascii?Q?u7xeMBV4rTfv2/vm5s3eeCKWvtzJZoxD+KOgs+3DNIpqi3HM3l+Bhs/Wgy3i?= =?us-ascii?Q?WX/FFeARLHyZShXwHtc3i5O1e4CuKSZ5T99pk5KN/3/t4ZWcgoYqGrRVFFkR?= =?us-ascii?Q?ILiO0za/GmLWN+KpS6eDT7/T1BgozZrgGP1kr/Q00PZ3ZP7MjtvyHHsHwoSS?= =?us-ascii?Q?ZhkV+c1vh8RpPZlHcE3oJsj5vABOz6vd+v3Bel03taxcXhgQw8yoZ1Ue1h6q?= =?us-ascii?Q?Zg/QKMEg1MxKGP+MENfPQCd0vwjIXXI5VoWPbEbrubfR0Wgf8odiI658XdiQ?= =?us-ascii?Q?7YPFzlQ++dsAAhwkWXmlAeyE/oMRzjYHkAUWMqzU43FnHgnnUIGv7qX4/8Hc?= =?us-ascii?Q?5wGviTrlIoRmTm8w980qGYI2PuAHepmZhpXMmQ/rVDAQlZ7av+hRl6817EBm?= =?us-ascii?Q?95KTSDia7KI74MKWGna4Snp2hO4aPqPhx3CrybDLdFMcEfXWFD1VV7IIEaNS?= =?us-ascii?Q?p7X6NYG5n8eiHRsuQniavPMYcQ8bc6HwuoLC+jlxOjbw9PD3EgBXogAmREk1?= =?us-ascii?Q?NDO6LRnWeCxaM9XKxiXITDgzVVCnI8YY8kIy8J9eTB66UKYe6ahypWGt2wSZ?= =?us-ascii?Q?gEaNv1VSxsAhDgvPpamvsTDVISTYCCKbhhWOQXUod9MmGPuSPAd7c5xiMU56?= =?us-ascii?Q?ccXEL69H0wi/kW2SjEchTKeziwDBcVZE4+x65x4XrQuKOg+sMfKl1u9T5jvr?= =?us-ascii?Q?qJ18sf5MeDDsB92vh9j0KJBIin0cPDue23294JY9a6hZHulm0+2t+atejgz/?= =?us-ascii?Q?KtVlOS47KTMitB5ArSJhyANAvJ0/fy+c3oDzRkGFKSTk7HLR4GfsX4icchBW?= =?us-ascii?Q?Q0Lc/Gat3cFQGk8nIanQd1yRXF7Lu2wthivXf9gF?= X-MS-Exchange-CrossTenant-Network-Message-Id: 9663a3ae-9c20-438d-f86a-08db83deca8e X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 13 Jul 2023 20:21:51.0749 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: X0bK364ou3FLwxsFo02NPgOf7RXPsmYKa4SkA6eB212P48JU9ORjsV/v/6xYpYy52qCkwv8k5tzOR+9wz8ETxQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR11MB7201 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH 3/5] drm/xe: Change tile masks from u64 to u8 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Tue, Jul 11, 2023 at 02:27:46PM -0700, Matthew Brost wrote: > This will save us a few bytes in the xe_vma structure. > > Signed-off-by: Matthew Brost > --- > drivers/gpu/drm/xe/xe_vm.c | 8 ++++---- > drivers/gpu/drm/xe/xe_vm_types.h | 28 ++++++++++++++-------------- > 2 files changed, 18 insertions(+), 18 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index b2847be6de6a..762aefa75ed4 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -871,7 +871,7 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm, > u64 start, u64 end, > bool read_only, > bool is_null, > - u64 tile_mask) > + u8 tile_mask) > { > struct xe_vma *vma; > struct xe_tile *tile; > @@ -2246,7 +2246,7 @@ static void print_op(struct xe_device *xe, struct drm_gpuva_op *op) > static struct drm_gpuva_ops * > vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, > u64 bo_offset_or_userptr, u64 addr, u64 range, > - u32 operation, u64 tile_mask, u32 region) > + u32 operation, u8 tile_mask, u32 region) > { > struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL; > struct ww_acquire_ctx ww; > @@ -2343,7 +2343,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, > } > > static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op, > - u64 tile_mask, bool read_only, bool is_null) > + u8 tile_mask, bool read_only, bool is_null) > { > struct xe_bo *bo = op->gem.obj ? gem_to_xe_bo(op->gem.obj) : NULL; > struct xe_vma *vma; > @@ -3323,7 +3323,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > u64 addr = bind_ops[i].addr; > u32 op = bind_ops[i].op; > u64 obj_offset = bind_ops[i].obj_offset; > - u64 tile_mask = bind_ops[i].tile_mask; > + u8 tile_mask = bind_ops[i].tile_mask; > u32 region = bind_ops[i].region; > > ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset, > diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h > index 84bf1620214c..2a8691a48c55 100644 > --- a/drivers/gpu/drm/xe/xe_vm_types.h > +++ b/drivers/gpu/drm/xe/xe_vm_types.h > @@ -37,18 +37,6 @@ struct xe_vma { > /** @gpuva: Base GPUVA object */ > struct drm_gpuva gpuva; > > - /** @tile_mask: Tile mask of where to create binding for this VMA */ > - u64 tile_mask; > - > - /** > - * @tile_present: GT mask of binding are present for this VMA. > - * protected by vm->lock, vm->resv and for userptrs, > - * vm->userptr.notifier_lock for writing. Needs either for reading, > - * but if reading is done under the vm->lock only, it needs to be held > - * in write mode. > - */ > - u64 tile_present; > - > /** @combined_links: links into lists which are mutually exclusive */ > union { > /** @userptr: link into VM repin list if userptr */ > @@ -97,9 +85,21 @@ struct xe_vma { > /** @usm: unified shared memory state */ > struct { > /** @tile_invalidated: VMA has been invalidated */ > - u64 tile_invalidated; > + u8 tile_invalidated; > } usm; > > + /** @tile_mask: Tile mask of where to create binding for this VMA */ > + u8 tile_mask; > + > + /** > + * @tile_present: GT mask of binding are present for this VMA. > + * protected by vm->lock, vm->resv and for userptrs, > + * vm->userptr.notifier_lock for writing. Needs either for reading, > + * but if reading is done under the vm->lock only, it needs to be held > + * in write mode. > + */ > + u8 tile_present; > + > struct { > struct list_head rebind_link; > } notifier; > @@ -386,7 +386,7 @@ struct xe_vma_op { > */ > struct async_op_fence *fence; > /** @tile_mask: gt mask for this operation */ > - u64 tile_mask; > + u8 tile_mask; I'm seeing us to use hweight_long on this tile_mask... > /** @flags: operation flags */ > enum xe_vma_op_flags flags; > > -- > 2.34.1 >