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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?j9JD6UI5mJszxI9W6Gjhb/b7h/RY66XiTHAQCrpICk7eH9sYzYNI7LxjEaBZ?= =?us-ascii?Q?sQedY7UOZbgJVlUvjo0mhGd7DmhwmPsjzJURt825ya6S9/s7g2kWGwKSUfeW?= =?us-ascii?Q?oV4BFsG/mgP6bNPrmtjjdBB8sEuv7+as8JNmjTLQdjYlSCJLx39aLA7aS1tf?= =?us-ascii?Q?n8e8KROv8/jEZwRFnqv81/QuPhiHiREaxsPDw+92hGe04pUtkpGDH9IYWZGU?= =?us-ascii?Q?xLG/8mU4lzxt35qD9ulrliYJj8GzCFzhRX5rNlCNaqJcqShmU7EDwAdJ2NZj?= =?us-ascii?Q?6YESmEnjcL6NgZFjyFIINHppbNu+VTYqWvGFtY74fy9KdUxknZuS83NxQN+y?= =?us-ascii?Q?Qbm1sEcqzWklcKGV9VSXrScvPDrSG6p4fl2Q076GM661tMbJtf1J6kQRdgIk?= =?us-ascii?Q?LqdGArnR3hjCcCauhFV7X+cu5F47T5LxecGT+qZg3hWtlEuZXBmIkY3h3HUE?= =?us-ascii?Q?k664+fp0qcRpwt3elQLGEeobBpArfYoTHV+u7OujhguTmjpoqOSAMYb0Ffbm?= =?us-ascii?Q?LY69ssDIc6J9pD1cm/UGrZNruq5/Jby+lezyH3+V3gcNnz1UzaZy9n9urBNZ?= =?us-ascii?Q?x8D08RHrC41nkxXBPG+mPRaQnEIOyRGiO88gbDSaEZsLLgo5LiuDrueGM4em?= =?us-ascii?Q?lTOduErnNlsjE3Qgxjh47sQjATqlvq1cKhYRkHo1+xiiqhQie9ppN9iE0DBR?= =?us-ascii?Q?mB/LlpjXF6hxvK2QGanlffOi8IOCWiRZwtOSloVquPrWrFfVBZ9B8tiHiuxz?= =?us-ascii?Q?fTiMchrQKc6OFx3/k4ler7jCSdGVeaPupQl+G1As2jQ6IneEF1DdqhHF/UJb?= =?us-ascii?Q?HrXibJ1bNoVBtgHZRKAikou+MMVfsC1ogyg4aoYzTP2/JpuRuMHD9quR5a5A?= =?us-ascii?Q?c6MpMJRzWAkhK8+y552919fWjf8YuvKHkQwTM2vXEALBL/1HjNTg5uJDlU8L?= =?us-ascii?Q?NiqLwkj4HYia/l1FfRCwiY+fCn3pv5PetGlNDdWBE2Q1ZXNO/ccw29yWL3gA?= =?us-ascii?Q?v6ea4ViBNCAHx6wKxI1gU1MxNP17vsJgeXGFhQVfawAPZUOzoS6IEynoqOym?= =?us-ascii?Q?A5a6t1l7vDZ5mcdFkgZFvZpfowvwMlIxvYeuHHcJTQf08hGzm0S4wEpSpx6Z?= =?us-ascii?Q?/SrDInacsW2jUOo+6q0DGugHcq/rZvdMx1mOxyiUoLEw/9kSFYcWK6rurWm9?= =?us-ascii?Q?8/i5rrsmtJ9j3yMH9XZFXBe9oNzJ1vS3qn0jizooqn7mTOCBlbp3UGjt4Qd7?= =?us-ascii?Q?Qt9p/hUc3OdpcYs1fZ98SK1Ao/4eXVU9arQiwQ1jKZ9Fxyvf430Yg1Yo3Nnq?= =?us-ascii?Q?9cygnYrJrlTG8QDP+7n9ap16KV1Jyp5DeSzAKrUAtiM/nPT/izOscc1HR7TK?= =?us-ascii?Q?1JSV1i+HC1iaweUOsjIeY3NB9nYep2F4iTp5iRjS2vO9BMST8n2HlPdqn5z4?= =?us-ascii?Q?AR93pK9ZRtancSBc9Kvr5x/rd1ssqpJ37aVgyJg/z2/QUsNNhQQwfYVwb1Eb?= =?us-ascii?Q?EM56/dTodZ5HBfWnvc5qej3OUzWkychW+e7kVoIl0wqOn7KcHwEisrc4sJW8?= =?us-ascii?Q?OjIXsg/01qkgGqV3AERRI+XE2FNeUMhgkQek3Rxp6bsEAOi7vCmrL2oxr3B5?= =?us-ascii?Q?UQ=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: bfeb646e-cfea-4d5b-33be-08db8938d3e7 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2023 15:48:57.3063 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: 8v2EYG8S5lhn9m8mvRNPfP+tJPAGKW02nn4AF2dJArqppYpuiagfFIgwSECYdzvq0OYHCz4m2+ELz8JAcyfPLg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR11MB7810 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH v2 4/6] drm/xe: Change tile masks from u64 to u8 X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: intel-xe@lists.freedesktop.org Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Wed, Jul 19, 2023 at 09:10:55PM -0700, Matthew Brost wrote: > This will save us a few bytes in the xe_vma structure. > > v2: Use hweight8 rather than hweight_long (Rodrigo) > > Signed-off-by: Matthew Brost Reviewed-by: Rodrigo Vivi > --- > drivers/gpu/drm/xe/xe_vm.c | 12 ++++++------ > drivers/gpu/drm/xe/xe_vm_types.h | 28 ++++++++++++++-------------- > 2 files changed, 20 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index 1ed3bc2541f2..92d97d347a44 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -871,7 +871,7 @@ static struct xe_vma *xe_vma_create(struct xe_vm *vm, > u64 start, u64 end, > bool read_only, > bool is_null, > - u64 tile_mask) > + u8 tile_mask) > { > struct xe_vma *vma; > struct xe_tile *tile; > @@ -1574,7 +1574,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > struct dma_fence_array *cf = NULL; > struct xe_vm *vm = xe_vma_vm(vma); > int cur_fence = 0, i; > - int number_tiles = hweight_long(vma->tile_present); > + int number_tiles = hweight8(vma->tile_present); > int err; > u8 id; > > @@ -1649,7 +1649,7 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > struct dma_fence_array *cf = NULL; > struct xe_vm *vm = xe_vma_vm(vma); > int cur_fence = 0, i; > - int number_tiles = hweight_long(vma->tile_mask); > + int number_tiles = hweight8(vma->tile_mask); > int err; > u8 id; > > @@ -2245,7 +2245,7 @@ static void print_op(struct xe_device *xe, struct drm_gpuva_op *op) > static struct drm_gpuva_ops * > vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, > u64 bo_offset_or_userptr, u64 addr, u64 range, > - u32 operation, u64 tile_mask, u32 region) > + u32 operation, u8 tile_mask, u32 region) > { > struct drm_gem_object *obj = bo ? &bo->ttm.base : NULL; > struct ww_acquire_ctx ww; > @@ -2342,7 +2342,7 @@ vm_bind_ioctl_ops_create(struct xe_vm *vm, struct xe_bo *bo, > } > > static struct xe_vma *new_vma(struct xe_vm *vm, struct drm_gpuva_op_map *op, > - u64 tile_mask, bool read_only, bool is_null) > + u8 tile_mask, bool read_only, bool is_null) > { > struct xe_bo *bo = op->gem.obj ? gem_to_xe_bo(op->gem.obj) : NULL; > struct xe_vma *vma; > @@ -3327,7 +3327,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > u64 addr = bind_ops[i].addr; > u32 op = bind_ops[i].op; > u64 obj_offset = bind_ops[i].obj_offset; > - u64 tile_mask = bind_ops[i].tile_mask; > + u8 tile_mask = bind_ops[i].tile_mask; > u32 region = bind_ops[i].region; > > ops[i] = vm_bind_ioctl_ops_create(vm, bos[i], obj_offset, > diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h > index f1f3b619d996..268d2475f2ae 100644 > --- a/drivers/gpu/drm/xe/xe_vm_types.h > +++ b/drivers/gpu/drm/xe/xe_vm_types.h > @@ -37,18 +37,6 @@ struct xe_vma { > /** @gpuva: Base GPUVA object */ > struct drm_gpuva gpuva; > > - /** @tile_mask: Tile mask of where to create binding for this VMA */ > - u64 tile_mask; > - > - /** > - * @tile_present: GT mask of binding are present for this VMA. > - * protected by vm->lock, vm->resv and for userptrs, > - * vm->userptr.notifier_lock for writing. Needs either for reading, > - * but if reading is done under the vm->lock only, it needs to be held > - * in write mode. > - */ > - u64 tile_present; > - > /** @combined_links: links into lists which are mutually exclusive */ > union { > /** > @@ -106,9 +94,21 @@ struct xe_vma { > /** @usm: unified shared memory state */ > struct { > /** @tile_invalidated: VMA has been invalidated */ > - u64 tile_invalidated; > + u8 tile_invalidated; > } usm; > > + /** @tile_mask: Tile mask of where to create binding for this VMA */ > + u8 tile_mask; > + > + /** > + * @tile_present: GT mask of binding are present for this VMA. > + * protected by vm->lock, vm->resv and for userptrs, > + * vm->userptr.notifier_lock for writing. Needs either for reading, > + * but if reading is done under the vm->lock only, it needs to be held > + * in write mode. > + */ > + u8 tile_present; > + > struct { > struct list_head rebind_link; > } notifier; > @@ -395,7 +395,7 @@ struct xe_vma_op { > */ > struct async_op_fence *fence; > /** @tile_mask: gt mask for this operation */ > - u64 tile_mask; > + u8 tile_mask; > /** @flags: operation flags */ > enum xe_vma_op_flags flags; > > -- > 2.34.1 >