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DIR:OUT; SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?x6vtvmcwqyq6eZn+4OQrNMYmF3QOzozzxLbDvO40yOh0IOIlBIHWiaRA/AHV?= =?us-ascii?Q?RGOCDW6EwpYH1Rb7+ROk7yPYGkUQUOLSMNqqtF5Wl67pvWkBVoWnyz7w5NLn?= =?us-ascii?Q?7IEw4FEJC0obbwzkRGDKoGNCHfh188ohABL00XnT3pomSGop/yN8Dr/EQsp2?= =?us-ascii?Q?yFhz94LjTIVmtGsWGSHNDjya40dhpOPo/zAOqG7El7oPhJsM31uFUrve3dfg?= =?us-ascii?Q?rlzmaUT9EQ7axvMNiDenJotEEyxEPtJ+eqUANPA0mv2eyp4rogvWJMyeDMER?= =?us-ascii?Q?9jouTo9H4PbltDjxSE6hc78ZoySCLP34AIdNHaDGisDBlBuR/cSDBkpBRhyS?= =?us-ascii?Q?8z7Tbo6iOBsq0j/ho4AcR2EOE+saRQWTbcIJT2YgjmNPbC3beKqwC1M/+qVu?= =?us-ascii?Q?NK3TXV2Jj52AHl6tHbqDy7H+XgnJUCBJYNDD4jeHJryGYBWSUCzlI6717uob?= =?us-ascii?Q?IsWHmFBFx+n5Qe62HXCf2i4ikC+VjK89dZWNTuKfuPNVHs1ctO6dVWXe97qz?= =?us-ascii?Q?lz0XNkggHp4dv+b4Ndxh6E5Zadqmi6s28xhrwmwtCsLy6VQCnir7Tkk1jtFA?= =?us-ascii?Q?QeaPlUBU4jJCpeIY257UL7ofpZNRqahJRFl6bxtZhmgzgfqVzgVFyTpZpW48?= =?us-ascii?Q?xrZycVDL6BEk9Ykmiht372djmTsb5X+3lvZSjYrhatLcnG/MYep+rmtoChPp?= =?us-ascii?Q?FgCgS34hSM5b5DCKJNpCMgaeSs//l7nxj3Rlxet0UhA6oIuraCNUmdV4Ty+X?= =?us-ascii?Q?6Z9R7AUMuu9ktNDveO78YeJOfZqN5WYLJKauWlmdAp7/94M4zqRzm04rQcR2?= =?us-ascii?Q?1yshkAxelmEF4ftFSuruXsdxjtXuNtciYVFdsUoVDb6rwuzGikQK2dTgrYKb?= =?us-ascii?Q?yapw6Osa89m37Jsm+R2M3UCY5jJi6D76tp/50824aRNIoR/bd1GIKfOJCpUO?= =?us-ascii?Q?HjgSXexYgszD/sDasYuZfpBMr86+70HJWbZvIx31PsL64xsz1n03zKux6cym?= =?us-ascii?Q?D+wWqz5+ey5fnVKHX576mFhroTCJ7cDsWkOfqY5FS2P8cyfoSjNj04L49M5v?= =?us-ascii?Q?ekFrjFnaD8PiN+dkxP1sF4nvPSl8UqQOlKP5McCWq7i7zqCcMj0ND4R8Iboz?= =?us-ascii?Q?xASWP5OR8uFDnUxVvPIpQQlUh/5bZ/bQXTXuvxpMmDeEpZmCxptKyUl5EW4e?= =?us-ascii?Q?3296e5wjTg1tipcbZHKo45DOpAjNcseDjRgUiWh0aNTCCHYa3r2lFPZI+DQB?= =?us-ascii?Q?tPY0Oe/9RHcNkdJzPW7gnQEhtyGHxvBNDYkMIhkADCR+ZGRRJqadlRPV+z4S?= =?us-ascii?Q?oJgeNhDW4hehpHkkclFY+UyY2TBx+KKYM1VbDXSkRUh/KHG94mRnHVZTqFuz?= =?us-ascii?Q?iTriTtBMG9A8D1DmS7kwd3GKedNHlswG4vDR7C5Q9EQO1Akpx0dT91E4HiXr?= =?us-ascii?Q?5lsJbQelgh8HgmblW6pKbALyJwT7DkK5I8EKQQ2/cFi+kV2VuhDcSayJHLIc?= =?us-ascii?Q?vnP41ele9Wwz+k5RPb8Gl7Vfr+zDKMQQ2VO/9Emvz601RKMwvGixYS3pACQR?= =?us-ascii?Q?IHMLWt9cynsLxIaHHJqxdxBgHhgjul1qCj/2HEeY0wsm/ya5jy/pmQ4LlJjW?= =?us-ascii?Q?6Q=3D=3D?= X-MS-Exchange-CrossTenant-Network-Message-Id: aa4b2b11-84eb-4cbe-26fd-08db99ec8c46 X-MS-Exchange-CrossTenant-AuthSource: MN0PR11MB6059.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 10 Aug 2023 21:55:45.1324 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 46c98d88-e344-4ed4-8496-4ed7712e255d X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HvG3e8asCKQJfXey80IQaDsuRa2aI3eRNYoXELFGWcyeJAA4NzFroO1QCTAWeyXXWiJdEa/ENyN/lLtRqp1dig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH0PR11MB5540 X-OriginatorOrg: intel.com Subject: Re: [Intel-xe] [PATCH v3 2/2] drm/xe/pmu: Enable PMU interface X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Bommu Krishnaiah , intel-xe@lists.freedesktop.org, Tvrtko Ursulin Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, Aug 10, 2023 at 01:40:16PM +0530, Iddamsetty, Aravind wrote: > > > On 10-08-2023 08:10, Dixit, Ashutosh wrote: > > Hi Ashutosh, > > > On Wed, 09 Aug 2023 06:11:48 -0700, Iddamsetty, Aravind wrote: > > > > Hi Aravind, > > > >> On 09-08-2023 17:27, Iddamsetty, Aravind wrote: > >>> On 09-08-2023 15:25, Iddamsetty, Aravind wrote: > >>>> On 09-08-2023 12:58, Dixit, Ashutosh wrote: > >>>>> On Tue, 08 Aug 2023 04:54:36 -0700, Aravind Iddamsetty wrote: > >>>>> > >>>>> Spotted a few remaining things. See if it's possible to fix these up and > >>>>> send another version. > >>>>> > >>>>>> diff --git a/drivers/gpu/drm/xe/xe_pmu.c b/drivers/gpu/drm/xe/xe_pmu.c > >>>>>> new file mode 100644 > >>>>>> index 000000000000..9637f8283641 > >>>>>> --- /dev/null > >>>>>> +++ b/drivers/gpu/drm/xe/xe_pmu.c > >>>>>> @@ -0,0 +1,673 @@ > >>>> > >>>> > >>>>>> +static u64 __engine_group_busyness_read(struct xe_gt *gt, int sample_type) > >>>>>> +{ > >>>>>> + u64 val = 0; > >>>>>> + > >>>>> > >>>>> What is the forcewake domain for these registers? Don't we need to get > >>>>> forcewake before reading these. Something like: > >>>>> > >>>>> XE_WARN_ON(xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); > >>>> > >>>> based on BSPEC:67609 these belong to GT power domain, so acquiring that > >>>> should be sufficient. > >>> > >>> But if i understand correctly taking forcewake is not allowed here as it > >>> is an atomic context and forcewake can sleep and that is what I'm seeing > >>> as well, might also be the reason why i915 didn't do that as well. > >>> > >>> [ 899.114316] BUG: sleeping function called from invalid context at > >>> kernel/locking/mutex.c:580 > >>> [ 899.115768] in_atomic(): 1, irqs_disabled(): 1, non_block: 0, pid: > >>> 290, name: kworker/27:1 > >> > >> that is the reason why in i915 we were doing similar thing of storing > >> the counter as we enter rc6, not sure how do we do that in xe. > > > > Just to check, which code path(s) is/are aotmic context: > > > > a. xe_pm_suspend > > b. xe_pm_runtime_suspend > > c. xe_pmu_event_read > > pmu_event_read and runtime_suspend are atomic contexts. what about doing this at xe_pci_runtime_idle() ? This will run after the autosuspend time elapses, but before calling any suspend. Also, there's no requirement of that function to be in atomic context. So you could forcewake_get/put and stash your registers before we go runtime_suspend. > > > > > Now I am wondering if GuC should provide these counters too along with > > other busyness values it provides, since GuC is what control RC6 > > entry/exit. But let's try to understand the issue some more first. > > do you mean GuC reading these registers and presenting us in a way, will > need to think over how does it fit in the PMU. > > Thanks, > Aravind. > > > > > Thanks. > > -- > > Ashutosh > > > > > >>>>> > >>>>>> + switch (sample_type) { > >>>>>> + case __XE_SAMPLE_RENDER_GROUP_BUSY: > >>>>>> + val = xe_mmio_read32(gt, XE_OAG_RENDER_BUSY_FREE); > >>>>>> + break; > >>>>>> + case __XE_SAMPLE_COPY_GROUP_BUSY: > >>>>>> + val = xe_mmio_read32(gt, XE_OAG_BLT_BUSY_FREE); > >>>>>> + break; > >>>>>> + case __XE_SAMPLE_MEDIA_GROUP_BUSY: > >>>>>> + val = xe_mmio_read32(gt, XE_OAG_ANY_MEDIA_FF_BUSY_FREE); > >>>>>> + break; > >>>>>> + case __XE_SAMPLE_ANY_ENGINE_GROUP_BUSY: > >>>>>> + val = xe_mmio_read32(gt, XE_OAG_RC0_ANY_ENGINE_BUSY_FREE); > >>>>>> + break; > >>>>>> + default: > >>>>>> + drm_warn(>->tile->xe->drm, "unknown pmu event\n"); > >>>>>> + } > >>>>> > >>>>> And similarly here: > >>>>> > >>>>> XE_WARN_ON(xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL));