Re: [Intel-xe] [PATCH v2 12/15] drm/xe/xe2: Program GuC's MOCS on Xe2 and beyond

[Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>]

On 18.08.2023 15:08, Lucas De Marchi wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> As with PVC, Xe2 platforms require that the index of an uncached MOCS
> entry be programmed into the GUC_SHIM_CONTROL register.  This will
> likely be needed on future platforms as well.
> 
> Xe2 also extends the size of the MOCS index register field from two bits
> to four bits.  Since these extra bits were unused on PVC, it should be
> safe to just increase the size of the mask.
> 
> Bspec: 60592
> Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_guc_regs.h | 2 +-
>  drivers/gpu/drm/xe/xe_guc.c           | 2 +-
>  2 files changed, 2 insertions(+), 2 deletions(-)

Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com>

Regards,
Bala

> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> index fcb747201bc1..ba375fc51a87 100644
> --- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
> @@ -45,7 +45,7 @@
>  #define   GUC_WOPCM_SIZE_LOCKED			REG_BIT(0)
>  
>  #define GUC_SHIM_CONTROL			XE_REG(0xc064)
> -#define   GUC_MOCS_INDEX_MASK			REG_GENMASK(25, 24)
> +#define   GUC_MOCS_INDEX_MASK			REG_GENMASK(27, 24)
>  #define   GUC_SHIM_WC_ENABLE			REG_BIT(21)
>  #define   GUC_ENABLE_MIA_CLOCK_GATING		REG_BIT(15)
>  #define   GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA	REG_BIT(10)
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 2493c5859948..e102637c0695 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -326,7 +326,7 @@ static void guc_prepare_xfer(struct xe_guc *guc)
>  		shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES |
>  				GUC_ENABLE_MIA_CACHING;
>  
> -	if (xe->info.platform == XE_PVC)
> +	if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC)
>  		shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index);
>  
>  	/* Must program this register before loading the ucode with DMA */
> -- 
> 2.40.1
>