From: Andi Shyti <andi.shyti@linux.intel.com>
To: Badal Nilawar <badal.nilawar@intel.com>
Cc: linux-hwmon@vger.kernel.org, rodrigo.vivi@intel.com,
intel-xe@lists.freedesktop.org, linux@roeck-us.net
Subject: Re: [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes
Date: Fri, 22 Sep 2023 19:24:46 +0200 [thread overview]
Message-ID: <ZQ3N3vvbkh9xPX40@ashyti-mobl2.lan> (raw)
In-Reply-To: <20230921102519.3355538-3-badal.nilawar@intel.com>
Hi Badal,
[...]
> +static int xe_hwmon_power_max_write(struct xe_hwmon *hwmon, long value)
> +{
> + u32 reg_val;
> +
> + /* Disable PL1 limit and verify, as limit cannot be disabled on all platforms */
> + if (value == PL1_DISABLE) {
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_READ, ®_val,
> + PKG_PWR_LIM_1_EN, 0);
> +
> + if (reg_val & PKG_PWR_LIM_1_EN)
> + return -ENODEV;
so, here you are trying to disable PL1 and check then if it's
disabled. Shall we try at least twice before returning error?
And why ENODEV? It might be that we failed to write on the
register but it doesn't mean that the device is wrong.
> + }
> +
> + /* Computation in 64-bits to avoid overflow. Round to nearest. */
> + reg_val = DIV_ROUND_CLOSEST_ULL((u64)value << hwmon->scl_shift_power, SF_POWER);
> + reg_val = PKG_PWR_LIM_1_EN | REG_FIELD_PREP(PKG_PWR_LIM_1, reg_val);
> +
> + xe_hwmon_process_reg(hwmon, REG_PKG_RAPL_LIMIT, REG_RMW, ®_val,
> + PKG_PWR_LIM_1_EN | PKG_PWR_LIM_1, reg_val);
> +
> + return 0;
> +}
[...]
> + /* hwmon_dev points to device hwmon<i> */
> + hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
> + "xe",
> + hwmon,
> + &hwmon_chip_info,
> + NULL);
here the allignment is a bit fancy... in this cases I wouldn't
mind going up to 100 characters or not align under the bracket.
I would write it like this
hwmon->hwmon_dev = devm_hwmon_device_register_with_info(dev,
"xe", hwmon, &hwmon_chip_info, NULL);
but, of course, it's a matter of taste. Up to you.
Andi
next prev parent reply other threads:[~2023-09-22 17:25 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-21 10:25 [Intel-xe] [PATCH v5 0/6] Add HWMON support for DGFX Badal Nilawar
2023-09-21 10:21 ` [Intel-xe] ✓ CI.Patch_applied: success for Add HWMON support for DGFX (rev5) Patchwork
2023-09-21 10:21 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-21 10:23 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 1/6] drm/xe: Add XE_MISSING_CASE macro Badal Nilawar
2023-09-21 16:03 ` Rodrigo Vivi
2023-09-21 16:59 ` Nilawar, Badal
2023-09-22 10:05 ` Jani Nikula
2023-09-22 15:16 ` Andi Shyti
2023-09-22 15:19 ` Gupta, Anshuman
2023-09-25 12:08 ` Jani Nikula
2023-09-22 19:03 ` Rodrigo Vivi
2023-09-25 4:07 ` Nilawar, Badal
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 2/6] drm/xe/hwmon: Expose power attributes Badal Nilawar
2023-09-21 13:22 ` Riana Tauro
2023-09-21 16:25 ` Rodrigo Vivi
2023-09-22 9:57 ` Nilawar, Badal
2023-09-22 17:24 ` Andi Shyti [this message]
2023-09-25 4:34 ` Nilawar, Badal
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 3/6] drm/xe/hwmon: Expose card reactive critical power Badal Nilawar
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 4/6] drm/xe/hwmon: Expose input voltage attribute Badal Nilawar
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 5/6] drm/xe/hwmon: Expose hwmon energy attribute Badal Nilawar
2023-09-21 14:09 ` Riana Tauro
2023-09-21 10:25 ` [Intel-xe] [PATCH v5 6/6] drm/xe/hwmon: Expose power1_max_interval Badal Nilawar
2023-09-21 11:43 ` Ghimiray, Himal Prasad
2023-09-22 9:49 ` Nilawar, Badal
2023-09-22 12:43 ` Ghimiray, Himal Prasad
2023-09-21 10:30 ` [Intel-xe] ✓ CI.Build: success for Add HWMON support for DGFX (rev5) Patchwork
2023-09-21 10:30 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-21 10:31 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-21 11:05 ` [Intel-xe] ✗ CI.BAT: failure " Patchwork
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