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From: Matthew Brost <matthew.brost@intel.com>
To: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Cc: intel-xe@lists.freedesktop.org
Subject: Re: [PATCH v2 1/2] drm/xe: Restrict huge PTEs to 1GiB
Date: Fri, 8 Dec 2023 12:30:03 +0000	[thread overview]
Message-ID: <ZXMMS7ozbgNwV+Iq@DUT025-TGLU.fm.intel.com> (raw)
In-Reply-To: <20231208112918.15411-2-thomas.hellstrom@linux.intel.com>

On Fri, Dec 08, 2023 at 12:29:17PM +0100, Thomas Hellström wrote:
> Add a define for the highest level for which we can encode a huge PTE,
> and use it for page-table building. Also update an assert that checks that
> we don't try to encode for larger sizes.
> 
> Signed-off-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pt.c | 3 +++
>  drivers/gpu/drm/xe/xe_pt.h | 3 +++
>  drivers/gpu/drm/xe/xe_vm.c | 2 +-
>  3 files changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index 35bd7940a571..699a255d75f5 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -430,6 +430,9 @@ static bool xe_pt_hugepte_possible(u64 addr, u64 next, unsigned int level,
>  {
>  	u64 size, dma;
>  
> +	if (level > MAX_HUGEPTE_LEVEL)
> +		return false;
> +
>  	/* Does the virtual range requested cover a huge pte? */
>  	if (!xe_pt_covers(addr, next, level, &xe_walk->base))
>  		return false;
> diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h
> index d5460e58dbbf..ba2f3325c84d 100644
> --- a/drivers/gpu/drm/xe/xe_pt.h
> +++ b/drivers/gpu/drm/xe/xe_pt.h
> @@ -18,6 +18,9 @@ struct xe_tile;
>  struct xe_vm;
>  struct xe_vma;
>  
> +/* Largest huge pte is currently 1GiB. May become device dependent. */
> +#define MAX_HUGEPTE_LEVEL 2
> +

I thought devices with 57 bits of address space support 512GiB pages?

Anyways the patch does LGTM and comment seems to address that is can
change.

With that:
Reviewed-by: Matthew Brost <matthew.brost@intel.com>

>  #define xe_pt_write(xe, map, idx, data) \
>  	xe_map_wr(xe, map, (idx) * sizeof(u64), u64, data)
>  
> diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c
> index e09050f16f07..f585cc7df071 100644
> --- a/drivers/gpu/drm/xe/xe_vm.c
> +++ b/drivers/gpu/drm/xe/xe_vm.c
> @@ -1239,7 +1239,7 @@ static u64 pte_encode_pat_index(struct xe_device *xe, u16 pat_index,
>  
>  static u64 pte_encode_ps(u32 pt_level)
>  {
> -	XE_WARN_ON(pt_level > 2);
> +	XE_WARN_ON(pt_level > MAX_HUGEPTE_LEVEL);
>  
>  	if (pt_level == 1)
>  		return XE_PDE_PS_2M;
> -- 
> 2.42.0
> 

  reply	other threads:[~2023-12-08 19:31 UTC|newest]

Thread overview: 8+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-08 11:29 [PATCH v2 0/2] Huge PTE and scratch page updates Thomas Hellström
2023-12-08 11:29 ` [PATCH v2 1/2] drm/xe: Restrict huge PTEs to 1GiB Thomas Hellström
2023-12-08 12:30   ` Matthew Brost [this message]
2023-12-08 19:35   ` Welty, Brian
2023-12-08 11:29 ` [PATCH v2 2/2] drm/xe: Use NULL PTEs as scratch PTEs Thomas Hellström
2023-12-08 19:37   ` Welty, Brian
2023-12-09 15:13     ` Thomas Hellström
2023-12-08 18:53 ` ✗ CI.Patch_applied: failure for Huge PTE and scratch page updates Patchwork

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