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Fortunately, it is able > to access a curated subset that is needed to initialize the driver by > communicating with SR-IOV PF using GuC CT. > Initialize GuC earlier in order to keep the unified probe ordering > between VF and PF modes. > > Signed-off-by: Michał Winiarski > Reviewed-by: Matthew Brost > --- > drivers/gpu/drm/xe/xe_device.c | 6 ++++ > drivers/gpu/drm/xe/xe_gt.c | 57 +++++++++++++++++++++++----------- > drivers/gpu/drm/xe/xe_gt.h | 1 + > drivers/gpu/drm/xe/xe_uc.c | 8 +++-- > 4 files changed, 52 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 5b84d73055202..3d10018957c46 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -471,6 +471,12 @@ int xe_device_probe(struct xe_device *xe) > } > } > > + for_each_gt(gt, xe, id) { > + err = xe_gt_init_hwconfig(gt); > + if (err) > + return err; > + } > + > err = drmm_add_action_or_reset(&xe->drm, xe_driver_flr_fini, xe); > if (err) > return err; > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > index 0bc59a4dbb496..312469b5dcc9b 100644 > --- a/drivers/gpu/drm/xe/xe_gt.c > +++ b/drivers/gpu/drm/xe/xe_gt.c > @@ -315,7 +315,6 @@ int xe_gt_init_early(struct xe_gt *gt) > return err; > > xe_gt_topology_init(gt); > - xe_gt_mcr_init(gt); > > err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); > if (err) > @@ -354,8 +353,6 @@ static int gt_fw_domain_init(struct xe_gt *gt) > if (err) > goto err_hw_fence_irq; > > - xe_pat_init(gt); > - > if (!xe_gt_is_media_type(gt)) { > err = xe_ggtt_init(gt_to_tile(gt)->mem.ggtt); > if (err) > @@ -364,19 +361,8 @@ static int gt_fw_domain_init(struct xe_gt *gt) > xe_lmtt_init(>_to_tile(gt)->sriov.pf.lmtt); > } > > - err = xe_uc_init(>->uc); > - if (err) > - goto err_force_wake; > - > - err = xe_uc_init_hwconfig(>->uc); > - if (err) > - goto err_force_wake; > - > xe_gt_idle_sysfs_init(>->gtidle); > > - /* XXX: Fake that we pull the engine mask from hwconfig blob */ > - gt->info.engine_mask = gt->info.__engine_mask; > - > /* Enable per hw engine IRQs */ > xe_irq_enable_hwe(gt); > > @@ -444,10 +430,6 @@ static int all_fw_domain_init(struct xe_gt *gt) > if (err) > goto err_force_wake; > > - err = xe_uc_init_post_hwconfig(>->uc); > - if (err) > - goto err_force_wake; > - > if (!xe_gt_is_media_type(gt)) { > /* > * USM has its only SA pool to non-block behind user operations > @@ -471,6 +453,10 @@ static int all_fw_domain_init(struct xe_gt *gt) > } > } > > + err = xe_uc_init_post_hwconfig(>->uc); > + if (err) > + goto err_force_wake; > + > err = xe_uc_init_hw(>->uc); > if (err) > goto err_force_wake; > @@ -500,6 +486,41 @@ static int all_fw_domain_init(struct xe_gt *gt) > return err; > } > > +/* > + * Initialize enough GT to be able to load GuC in order to obtain hwconfig and > + * enable CTB communication. > + */ > +int xe_gt_init_hwconfig(struct xe_gt *gt) > +{ > + int err; > + > + xe_device_mem_access_get(gt_to_xe(gt)); > + err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); > + if (err) > + goto out; > + > + xe_gt_mcr_init(gt); > + xe_pat_init(gt); > + > + err = xe_uc_init(>->uc); > + if (err) > + goto out_fw; > + > + err = xe_uc_init_hwconfig(>->uc); > + if (err) > + goto out_fw; > + > + /* XXX: Fake that we pull the engine mask from hwconfig blob */ > + gt->info.engine_mask = gt->info.__engine_mask; > + > +out_fw: > + xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); > +out: > + xe_device_mem_access_put(gt_to_xe(gt)); > + > + return err; > +} > + > int xe_gt_init(struct xe_gt *gt) > { > int err; > diff --git a/drivers/gpu/drm/xe/xe_gt.h b/drivers/gpu/drm/xe/xe_gt.h > index c1675bd44cf6d..ed6ea8057e35f 100644 > --- a/drivers/gpu/drm/xe/xe_gt.h > +++ b/drivers/gpu/drm/xe/xe_gt.h > @@ -33,6 +33,7 @@ static inline bool xe_fault_inject_gt_reset(void) > #endif > > struct xe_gt *xe_gt_alloc(struct xe_tile *tile); > +int xe_gt_init_hwconfig(struct xe_gt *gt); > int xe_gt_init_early(struct xe_gt *gt); > int xe_gt_init(struct xe_gt *gt); > int xe_gt_record_default_lrcs(struct xe_gt *gt); > diff --git a/drivers/gpu/drm/xe/xe_uc.c b/drivers/gpu/drm/xe/xe_uc.c > index d62137306d280..9e51aa6a29604 100644 > --- a/drivers/gpu/drm/xe/xe_uc.c > +++ b/drivers/gpu/drm/xe/xe_uc.c > @@ -32,13 +32,15 @@ uc_to_xe(struct xe_uc *uc) > /* Should be called once at driver load only */ > int xe_uc_init(struct xe_uc *uc) > { > + struct xe_device *xe = uc_to_xe(uc); > int ret; > > + xe_device_mem_access_get(xe); > + > /* > * We call the GuC/HuC/GSC init functions even if GuC submission is off > * to correctly move our tracking of the FW state to "disabled". > */ > - > ret = xe_guc_init(&uc->guc); > if (ret) > goto err; > @@ -52,7 +54,7 @@ int xe_uc_init(struct xe_uc *uc) > goto err; > > if (!xe_device_uc_enabled(uc_to_xe(uc))) > - return 0; > + goto err; > > ret = xe_wopcm_init(&uc->wopcm); > if (ret) > @@ -69,6 +71,8 @@ int xe_uc_init(struct xe_uc *uc) > return 0; > > err: > + xe_device_mem_access_put(xe); I was going to push this series, but then I noticed this is making mem_access unbalanced here. This reference is never put back on success above. > + > return ret; > } > > -- > 2.43.0 >