Re: [PATCH V2 3/3] drm/xe/arl: Add Arrow Lake H support

[Matt Atwood <matthew.s.atwood@intel.com>]

On Thu, Feb 29, 2024 at 11:43:31AM +0530, Dnyaneshwar Bhadane wrote:
> ARL-H uses the same media and display IP as MTL, and a version 12.74
> graphics IP (referred to as Xe_LPG+). From a driver point of view, we
> should be able to just treat the whole platform as MTL and rely on
> GRAPHICS_VERx100 checks to handle any spots where ARL's Xe_LPG+ needs
> different handling from MTL's Xe_LPG (i.e., workarounds).
> 
> v2: Resolve confict and reorder PCI ids in sorted order
> 
> Bspec: 55420
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/xe_pciids.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/drm/xe_pciids.h b/include/drm/xe_pciids.h
> index 2b7c2003ddb4..ab4a8987ac65 100644
> --- a/include/drm/xe_pciids.h
> +++ b/include/drm/xe_pciids.h
> @@ -176,10 +176,13 @@
>  /* MTL / ARL */
>  #define XE_MTL_IDS(MACRO__, ...)		\
>  	MACRO__(0x7D40, ## __VA_ARGS__),	\
> +	MACRO__(0x7D41, ## __VA_ARGS__),	\
>  	MACRO__(0x7D45, ## __VA_ARGS__),	\
> +	MACRO__(0x7D51, ## __VA_ARGS__),        \
>  	MACRO__(0x7D55, ## __VA_ARGS__),	\
>  	MACRO__(0x7D60, ## __VA_ARGS__),	\
>  	MACRO__(0x7D67, ## __VA_ARGS__),	\
> +	MACRO__(0x7DD1, ## __VA_ARGS__),        \
>  	MACRO__(0x7DD5, ## __VA_ARGS__)
>  
>  /* PVC */
> -- 
> 2.34.1
>