From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Jani Nikula <jani.nikula@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org
Subject: Re: [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h
Date: Fri, 12 Apr 2024 18:19:50 +0300 [thread overview]
Message-ID: <ZhlRFum4FT-I3o35@intel.com> (raw)
In-Reply-To: <e82ca633fbe0c39d3d72379866737b509c05ece4.1712933479.git.jani.nikula@intel.com>
On Fri, Apr 12, 2024 at 05:52:54PM +0300, Jani Nikula wrote:
> For some reason the paletter registers were missed when adding
> intel_color_regs.h. Finish the job.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> .../gpu/drm/i915/display/intel_color_regs.h | 30 +++++++++++++++++++
> drivers/gpu/drm/i915/i915_reg.h | 30 -------------------
> 2 files changed, 30 insertions(+), 30 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
> index 9f4ae58f3e7e..969745821172 100644
> --- a/drivers/gpu/drm/i915/display/intel_color_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
> @@ -8,6 +8,36 @@
>
> #include "intel_display_reg_defs.h"
>
> +/*
> + * Palette regs
> + */
Quite redundant. If we want to keep a comment then it
should be adjusted to say these are for gmch platforms.
> +#define _PALETTE_A 0xa000
> +#define _PALETTE_B 0xa800
> +#define _CHV_PALETTE_C 0xc000
> +/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
> +#define PALETTE_RED_MASK REG_GENMASK(23, 16)
> +#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> +#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> +/* pre-i965 10bit interpolated mode ldw */
> +#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
> +#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
> +#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
> +/* pre-i965 10bit interpolated mode udw */
> +#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
> +#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
> +#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
> +#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
> +#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
> +#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
> +#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
> +#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
> +#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
> +#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> + _PICK_EVEN_2RANGES(pipe, 2, \
> + _PALETTE_A, _PALETTE_B, \
> + _CHV_PALETTE_C, _CHV_PALETTE_C) + \
> + (i) * 4)
> +
> /* legacy palette */
and then this should be adjusted to indicate ilk+
Otherwise
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> #define _LGC_PALETTE_A 0x4a000
> #define _LGC_PALETTE_B 0x4a800
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index c689bc7e2867..b74965383a56 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1700,36 +1700,6 @@
>
> #define GMBUSFREQ_VLV _MMIO(VLV_DISPLAY_BASE + 0x6510)
>
> -/*
> - * Palette regs
> - */
> -#define _PALETTE_A 0xa000
> -#define _PALETTE_B 0xa800
> -#define _CHV_PALETTE_C 0xc000
> -/* 8bit mode / i965+ 10.6 interpolated mode ldw/udw */
> -#define PALETTE_RED_MASK REG_GENMASK(23, 16)
> -#define PALETTE_GREEN_MASK REG_GENMASK(15, 8)
> -#define PALETTE_BLUE_MASK REG_GENMASK(7, 0)
> -/* pre-i965 10bit interpolated mode ldw */
> -#define PALETTE_10BIT_RED_LDW_MASK REG_GENMASK(23, 16)
> -#define PALETTE_10BIT_GREEN_LDW_MASK REG_GENMASK(15, 8)
> -#define PALETTE_10BIT_BLUE_LDW_MASK REG_GENMASK(7, 0)
> -/* pre-i965 10bit interpolated mode udw */
> -#define PALETTE_10BIT_RED_EXP_MASK REG_GENMASK(23, 22)
> -#define PALETTE_10BIT_RED_MANT_MASK REG_GENMASK(21, 18)
> -#define PALETTE_10BIT_RED_UDW_MASK REG_GENMASK(17, 16)
> -#define PALETTE_10BIT_GREEN_EXP_MASK REG_GENMASK(15, 14)
> -#define PALETTE_10BIT_GREEN_MANT_MASK REG_GENMASK(13, 10)
> -#define PALETTE_10BIT_GREEN_UDW_MASK REG_GENMASK(9, 8)
> -#define PALETTE_10BIT_BLUE_EXP_MASK REG_GENMASK(7, 6)
> -#define PALETTE_10BIT_BLUE_MANT_MASK REG_GENMASK(5, 2)
> -#define PALETTE_10BIT_BLUE_UDW_MASK REG_GENMASK(1, 0)
> -#define PALETTE(pipe, i) _MMIO(DISPLAY_MMIO_BASE(dev_priv) + \
> - _PICK_EVEN_2RANGES(pipe, 2, \
> - _PALETTE_A, _PALETTE_B, \
> - _CHV_PALETTE_C, _CHV_PALETTE_C) + \
> - (i) * 4)
> -
> #define PEG_BAND_GAP_DATA _MMIO(0x14d68)
>
> #define BXT_RP_STATE_CAP _MMIO(0x138170)
> --
> 2.39.2
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2024-04-12 15:19 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-04-12 14:52 [PATCH 0/6] drm/i915: i915_reg.h cleanups Jani Nikula
2024-04-12 14:52 ` [PATCH 1/6] drm/i915/audio: move LPE audio regs to intel_audio_regs.h Jani Nikula
2024-04-12 15:15 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 2/6] drm/i915/color: move palette registers to intel_color_regs.h Jani Nikula
2024-04-12 15:19 ` Ville Syrjälä [this message]
2024-04-12 14:52 ` [PATCH 3/6] drm/i915/display: split out intel_fbc_regs.h from i915_reg.h Jani Nikula
2024-04-12 15:14 ` Ville Syrjälä
2024-04-12 15:50 ` Jani Nikula
2024-04-12 16:26 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 4/6] drm/i915/display: split out intel_sprite_regs.h " Jani Nikula
2024-04-12 15:22 ` Ville Syrjälä
2024-04-12 14:52 ` [PATCH 5/6] drm/i915/display: split out intel_dpio_regs.h " Jani Nikula
2024-04-12 15:31 ` Ville Syrjälä
2024-04-12 15:52 ` Jani Nikula
2024-04-12 14:52 ` [PATCH 6/6] drm/i915/display: split out bxt_phy_regs.h " Jani Nikula
2024-04-15 13:16 ` ✓ CI.Patch_applied: success for drm/i915: i915_reg.h cleanups Patchwork
2024-04-15 13:17 ` ✗ CI.checkpatch: warning " Patchwork
2024-04-15 13:18 ` ✓ CI.KUnit: success " Patchwork
2024-04-15 13:31 ` ✓ CI.Build: " Patchwork
2024-04-15 13:34 ` ✓ CI.Hooks: " Patchwork
2024-04-15 13:36 ` ✗ CI.checksparse: warning " Patchwork
2024-04-15 13:59 ` ✓ CI.BAT: success " Patchwork
2024-04-15 17:52 ` ✗ CI.FULL: failure " Patchwork
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