Re: [PATCH] drm/xe/bmg: Apply Wa_22019338487

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Wed, Jun 26, 2024 at 05:27:43PM -0700, Vinay Belgaumkar wrote:
> Extend this WA to BMG GT as well. In this case media GT is
> not affected. The cap frequencies and max allowed ggtt writes
> are different as well.
> 
> Signed-off-by: Vinay Belgaumkar <vinay.belgaumkar@intel.com>
> ---
>  drivers/gpu/drm/xe/xe_ggtt.c       | 11 ++++++++---
>  drivers/gpu/drm/xe/xe_guc_pc.c     | 11 ++++++++---
>  drivers/gpu/drm/xe/xe_wa_oob.rules |  1 +
>  3 files changed, 17 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ggtt.c b/drivers/gpu/drm/xe/xe_ggtt.c
> index 883cfc7f98a8..0cdbc1296e88 100644
> --- a/drivers/gpu/drm/xe/xe_ggtt.c
> +++ b/drivers/gpu/drm/xe/xe_ggtt.c
> @@ -74,6 +74,9 @@ static unsigned int probe_gsm_size(struct pci_dev *pdev)
>  
>  static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
>  {
> +	struct xe_gt *gt = XE_WA(ggtt->tile->primary_gt, 22019338487) ? ggtt->tile->primary_gt :
> +			   ggtt->tile->media_gt;
> +	u32 max_gtt_writes = XE_WA(ggtt->tile->primary_gt, 22019338487) ? 1100 : 63;

please explain this threashold difference in the commit message as well.

>  	/*
>  	 * Wa_22019338487: GMD_ID is a RO register, a dummy write forces gunit
>  	 * to wait for completion of prior GTT writes before letting this through.
> @@ -81,8 +84,8 @@ static void ggtt_update_access_counter(struct xe_ggtt *ggtt)
>  	 */
>  	lockdep_assert_held(&ggtt->lock);
>  
> -	if ((++ggtt->access_count % 63) == 0) {
> -		xe_mmio_write32(ggtt->tile->media_gt, GMD_ID, 0x0);
> +	if ((++ggtt->access_count % max_gtt_writes) == 0) {
> +		xe_mmio_write32(gt, GMD_ID, 0x0);
>  		ggtt->access_count = 0;
>  	}
>  }
> @@ -218,7 +221,9 @@ int xe_ggtt_init_early(struct xe_ggtt *ggtt)
>  		ggtt->size = GUC_GGTT_TOP;
>  
>  	if (GRAPHICS_VERx100(xe) >= 1270)
> -		ggtt->pt_ops = ggtt->tile->media_gt && XE_WA(ggtt->tile->media_gt, 22019338487) ?
> +		ggtt->pt_ops = (ggtt->tile->media_gt &&
> +			       XE_WA(ggtt->tile->media_gt, 22019338487)) ||
> +			       XE_WA(ggtt->tile->primary_gt, 22019338487) ?

it looks that all the decisions of one case or the other is convoluted
but I really don't have a better suggestion, so let's just move on...

with the commit message fixed:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


>  			       &xelpg_pt_wa_ops : &xelpg_pt_ops;
>  	else
>  		ggtt->pt_ops = &xelp_pt_ops;
> diff --git a/drivers/gpu/drm/xe/xe_guc_pc.c b/drivers/gpu/drm/xe/xe_guc_pc.c
> index d88f5e960fbd..16c4b3fadd45 100644
> --- a/drivers/gpu/drm/xe/xe_guc_pc.c
> +++ b/drivers/gpu/drm/xe/xe_guc_pc.c
> @@ -45,6 +45,7 @@
>  #define GT_FREQUENCY_SCALER	3
>  
>  #define LNL_MERT_FREQ_CAP	800
> +#define BMG_MERT_FREQ_CAP	2133
>  
>  /**
>   * DOC: GuC Power Conservation (PC)
> @@ -703,10 +704,14 @@ static u32 pc_max_freq_cap(struct xe_guc_pc *pc)
>  {
>  	struct xe_gt *gt = pc_to_gt(pc);
>  
> -	if (XE_WA(gt, 22019338487))
> -		return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
> -	else
> +	if (XE_WA(gt, 22019338487)) {
> +		if (xe_gt_is_media_type(gt))
> +			return min(LNL_MERT_FREQ_CAP, pc->rp0_freq);
> +		else
> +			return min(BMG_MERT_FREQ_CAP, pc->rp0_freq);
> +	} else {
>  		return pc->rp0_freq;
> +	}
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/xe/xe_wa_oob.rules b/drivers/gpu/drm/xe/xe_wa_oob.rules
> index a6b897030fde..26066beb4f6f 100644
> --- a/drivers/gpu/drm/xe/xe_wa_oob.rules
> +++ b/drivers/gpu/drm/xe/xe_wa_oob.rules
> @@ -28,3 +28,4 @@
>  		GRAPHICS_VERSION(2004)
>  13011645652	GRAPHICS_VERSION(2004)
>  22019338487	MEDIA_VERSION(2000)
> +		GRAPHICS_VERSION(2001)
> -- 
> 2.38.1
>