* [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 14:51 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 02/11] drm/i915/cx0: " Jani Nikula
` (17 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch gmbus code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
.../drm/i915/display/intel_display_driver.c | 4 +-
.../gpu/drm/i915/display/intel_display_irq.c | 11 +-
drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +-
drivers/gpu/drm/i915/display/intel_dvo.c | 8 +-
drivers/gpu/drm/i915/display/intel_gmbus.c | 290 +++++++++---------
drivers/gpu/drm/i915/display/intel_gmbus.h | 15 +-
.../gpu/drm/i915/display/intel_gmbus_regs.h | 16 +-
drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +-
.../gpu/drm/i915/display/intel_hotplug_irq.c | 6 +-
drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
drivers/gpu/drm/i915/i915_suspend.c | 2 +-
14 files changed, 202 insertions(+), 186 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
index 9967b65e3cf6..48c010b5b150 100644
--- a/drivers/gpu/drm/i915/display/intel_bios.c
+++ b/drivers/gpu/drm/i915/display/intel_bios.c
@@ -2796,7 +2796,6 @@ static bool child_device_size_valid(struct intel_display *display, int size)
static void
parse_general_definitions(struct intel_display *display)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct bdb_general_definitions *defs;
struct intel_bios_encoder_data *devdata;
const struct child_device_config *child;
@@ -2821,7 +2820,7 @@ parse_general_definitions(struct intel_display *display)
bus_pin = defs->crt_ddc_gmbus_pin;
drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
- if (intel_gmbus_is_valid_pin(i915, bus_pin))
+ if (intel_gmbus_is_valid_pin(display, bus_pin))
display->vbt.crt_ddc_pin = bus_pin;
if (!child_device_size_valid(display, defs->child_dev_size))
@@ -3338,7 +3337,6 @@ bool intel_bios_is_tv_present(struct intel_display *display)
*/
bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
{
- struct drm_i915_private *i915 = to_i915(display->drm);
const struct intel_bios_encoder_data *devdata;
if (list_empty(&display->vbt.display_devices))
@@ -3355,7 +3353,7 @@ bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
child->device_type != DEVICE_TYPE_LFP)
continue;
- if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))
+ if (intel_gmbus_is_valid_pin(display, child->i2c_pin))
*i2c_pin = child->i2c_pin;
/* However, we cannot trust the BIOS writers to populate
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index fd78adbaadbe..8222b1c251db 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -935,6 +935,7 @@ intel_crt_detect(struct drm_connector *connector,
static int intel_crt_get_modes(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
@@ -954,7 +955,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
goto out;
/* Try to probe digital port for output in DVI-I -> VGA mode. */
- ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
+ ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
ret = intel_crt_ddc_get_modes(connector, ddc);
out:
@@ -1009,6 +1010,7 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
void intel_crt_init(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct drm_connector *connector;
struct intel_crt *crt;
struct intel_connector *intel_connector;
@@ -1057,7 +1059,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
drm_connector_init_with_ddc(&dev_priv->drm, connector,
&intel_crt_connector_funcs,
DRM_MODE_CONNECTOR_VGA,
- intel_gmbus_get_adapter(dev_priv, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC, "CRT");
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index 673f9b965494..ae5470078173 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -432,7 +432,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
intel_pps_setup(display);
- intel_gmbus_setup(i915);
+ intel_gmbus_setup(display);
drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
INTEL_NUM_PIPES(i915),
@@ -608,7 +608,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
intel_overlay_cleanup(i915);
- intel_gmbus_teardown(i915);
+ intel_gmbus_teardown(display);
destroy_workqueue(i915->display.wq.flip);
destroy_workqueue(i915->display.wq.modeset);
diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
index a4f42ed3f21a..0478fe3cdd86 100644
--- a/drivers/gpu/drm/i915/display/intel_display_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
@@ -543,12 +543,13 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
intel_opregion_asle_intr(display);
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
u32 pipe_stats[I915_MAX_PIPES])
{
+ struct intel_display *display = &dev_priv->display;
enum pipe pipe;
for_each_pipe(dev_priv, pipe) {
@@ -566,7 +567,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
}
if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
@@ -588,7 +589,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_dp_aux_irq_handler(display);
if (pch_iir & SDE_GMBUS)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_HDCP_MASK)
drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
@@ -677,7 +678,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_dp_aux_irq_handler(display);
if (pch_iir & SDE_GMBUS_CPT)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
@@ -1109,7 +1110,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
(iir & BXT_DE_PORT_GMBUS)) {
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
found = true;
}
diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
index f0e3be0fe420..e8129a720210 100644
--- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
@@ -323,6 +323,7 @@ enum {
static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
int gpio, bool value)
{
+ struct intel_display *display = &dev_priv->display;
int index;
if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
@@ -367,7 +368,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
case MIPI_AVEE_EN_2:
index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
- intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+ intel_de_rmw(display, GPIO(display, index),
GPIO_CLOCK_VAL_OUT,
GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
@@ -376,7 +377,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
case MIPI_VIO_EN_2:
index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
- intel_de_rmw(dev_priv, GPIO(dev_priv, index),
+ intel_de_rmw(display, GPIO(display, index),
GPIO_DATA_VAL_OUT,
GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
index 9508ceae0d84..2d5ffb37eac9 100644
--- a/drivers/gpu/drm/i915/display/intel_dvo.c
+++ b/drivers/gpu/drm/i915/display/intel_dvo.c
@@ -417,6 +417,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
struct intel_dvo *intel_dvo,
const struct intel_dvo_device *dvo)
{
+ struct intel_display *display = &dev_priv->display;
struct i2c_adapter *i2c;
u32 dpll[I915_MAX_PIPES];
enum pipe pipe;
@@ -428,7 +429,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
* special cases, but otherwise default to what's defined
* in the spec.
*/
- if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
+ if (intel_gmbus_is_valid_pin(display, dvo->gpio))
gpio = dvo->gpio;
else if (dvo->type == INTEL_DVO_CHIP_LVDS)
gpio = GMBUS_PIN_SSC;
@@ -440,7 +441,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
* It appears that everything is on GPIOE except for panels
* on i830 laptops, which are on GPIOB (DVOA).
*/
- i2c = intel_gmbus_get_adapter(dev_priv, gpio);
+ i2c = intel_gmbus_get_adapter(display, gpio);
intel_dvo->dev = *dvo;
@@ -489,6 +490,7 @@ static bool intel_dvo_probe(struct drm_i915_private *i915,
void intel_dvo_init(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
struct intel_connector *connector;
struct intel_encoder *encoder;
struct intel_dvo *intel_dvo;
@@ -549,7 +551,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
drm_connector_init_with_ddc(&i915->drm, &connector->base,
&intel_dvo_connector_funcs,
intel_dvo_connector_type(&intel_dvo->dev),
- intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
+ intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));
drm_connector_helper_add(&connector->base,
&intel_dvo_connector_helper_funcs);
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
index 6470f75106bd..e3d938c7f83e 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.c
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
@@ -48,7 +48,7 @@ struct intel_gmbus {
u32 reg0;
i915_reg_t gpio_reg;
struct i2c_algo_bit_data bit_algo;
- struct drm_i915_private *i915;
+ struct intel_display *display;
};
enum gmbus_gpio {
@@ -149,9 +149,10 @@ static const struct gmbus_pin gmbus_pins_mtp[] = {
[GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
};
-static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
+static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
unsigned int pin)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
const struct gmbus_pin *pins;
size_t size;
@@ -173,7 +174,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
} else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
pins = gmbus_pins_bxt;
size = ARRAY_SIZE(gmbus_pins_bxt);
- } else if (DISPLAY_VER(i915) == 9) {
+ } else if (DISPLAY_VER(display) == 9) {
pins = gmbus_pins_skl;
size = ARRAY_SIZE(gmbus_pins_skl);
} else if (IS_BROADWELL(i915)) {
@@ -190,9 +191,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
return &pins[pin];
}
-bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
+bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
{
- return get_gmbus_pin(i915, pin);
+ return get_gmbus_pin(display, pin);
}
/* Intel GPIO access functions */
@@ -206,42 +207,45 @@ to_intel_gmbus(struct i2c_adapter *i2c)
}
void
-intel_gmbus_reset(struct drm_i915_private *i915)
+intel_gmbus_reset(struct intel_display *display)
{
- intel_de_write(i915, GMBUS0(i915), 0);
- intel_de_write(i915, GMBUS4(i915), 0);
+ intel_de_write(display, GMBUS0(display), 0);
+ intel_de_write(display, GMBUS4(display), 0);
}
-static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
+static void pnv_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
/* When using bit bashing for I2C, this bit needs to be set to 1 */
- intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
+ intel_de_rmw(display, DSPCLK_GATE_D(display),
+ PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
!enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
}
-static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
+static void pch_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
- intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
+ intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
+ PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
!enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
}
-static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
+static void bxt_gmbus_clock_gating(struct intel_display *display,
bool enable)
{
- intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
+ intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
!enable ? BXT_GMBUS_GATING_DIS : 0);
}
static u32 get_reserved(struct intel_gmbus *bus)
{
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u32 reserved = 0;
/* On most chips, these bits must be preserved in software. */
if (!IS_I830(i915) && !IS_I845G(i915))
- reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
+ reserved = intel_de_read_notrace(display, bus->gpio_reg) &
(GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
return reserved;
@@ -250,31 +254,31 @@ static u32 get_reserved(struct intel_gmbus *bus)
static int get_clock(void *data)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved);
- return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
+ return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
}
static int get_data(void *data)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
- intel_de_write_notrace(i915, bus->gpio_reg, reserved);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved);
- return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
+ return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
}
static void set_clock(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
u32 clock_bits;
@@ -284,14 +288,14 @@ static void set_clock(void *data, int state_high)
clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
GPIO_CLOCK_VAL_MASK;
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
- intel_de_posting_read(i915, bus->gpio_reg);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
+ intel_de_posting_read(display, bus->gpio_reg);
}
static void set_data(void *data, int state_high)
{
struct intel_gmbus *bus = data;
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
u32 reserved = get_reserved(bus);
u32 data_bits;
@@ -301,20 +305,21 @@ static void set_data(void *data, int state_high)
data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
GPIO_DATA_VAL_MASK;
- intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
- intel_de_posting_read(i915, bus->gpio_reg);
+ intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
+ intel_de_posting_read(display, bus->gpio_reg);
}
static int
intel_gpio_pre_xfer(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
- intel_gmbus_reset(i915);
+ intel_gmbus_reset(display);
if (IS_PINEVIEW(i915))
- pnv_gmbus_clock_gating(i915, false);
+ pnv_gmbus_clock_gating(display, false);
set_data(bus, 1);
set_clock(bus, 1);
@@ -326,13 +331,14 @@ static void
intel_gpio_post_xfer(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
set_data(bus, 1);
set_clock(bus, 1);
if (IS_PINEVIEW(i915))
- pnv_gmbus_clock_gating(i915, true);
+ pnv_gmbus_clock_gating(display, true);
}
static void
@@ -355,16 +361,17 @@ intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
algo->data = bus;
}
-static bool has_gmbus_irq(struct drm_i915_private *i915)
+static bool has_gmbus_irq(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
/*
* encoder->shutdown() may want to use GMBUS
* after irqs have already been disabled.
*/
- return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
+ return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
}
-static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
+static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
{
DEFINE_WAIT(wait);
u32 gmbus2;
@@ -374,21 +381,21 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
* we also need to check for NAKs besides the hw ready/idle signal, we
* need to wake up periodically and check that ourselves.
*/
- if (!has_gmbus_irq(i915))
+ if (!has_gmbus_irq(display))
irq_en = 0;
- add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
- intel_de_write_fw(i915, GMBUS4(i915), irq_en);
+ add_wait_queue(&display->gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), irq_en);
status |= GMBUS_SATOER;
- ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
+ ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
2);
if (ret)
- ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
+ ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
50);
- intel_de_write_fw(i915, GMBUS4(i915), 0);
- remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), 0);
+ remove_wait_queue(&display->gmbus.wait_queue, &wait);
if (gmbus2 & GMBUS_SATOER)
return -ENXIO;
@@ -397,7 +404,7 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
}
static int
-gmbus_wait_idle(struct drm_i915_private *i915)
+gmbus_wait_idle(struct intel_display *display)
{
DEFINE_WAIT(wait);
u32 irq_enable;
@@ -405,33 +412,33 @@ gmbus_wait_idle(struct drm_i915_private *i915)
/* Important: The hw handles only the first bit, so set only one! */
irq_enable = 0;
- if (has_gmbus_irq(i915))
+ if (has_gmbus_irq(display))
irq_enable = GMBUS_IDLE_EN;
- add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
- intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
+ add_wait_queue(&display->gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), irq_enable);
- ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
+ ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10);
- intel_de_write_fw(i915, GMBUS4(i915), 0);
- remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
+ intel_de_write_fw(display, GMBUS4(display), 0);
+ remove_wait_queue(&display->gmbus.wait_queue, &wait);
return ret;
}
-static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
+static unsigned int gmbus_max_xfer_size(struct intel_display *display)
{
- return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
+ return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
GMBUS_BYTE_COUNT_MAX;
}
static int
-gmbus_xfer_read_chunk(struct drm_i915_private *i915,
+gmbus_xfer_read_chunk(struct intel_display *display,
unsigned short addr, u8 *buf, unsigned int len,
u32 gmbus0_reg, u32 gmbus1_index)
{
unsigned int size = len;
- bool burst_read = len > gmbus_max_xfer_size(i915);
+ bool burst_read = len > gmbus_max_xfer_size(display);
bool extra_byte_added = false;
if (burst_read) {
@@ -444,21 +451,21 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
len++;
}
size = len % 256 + 256;
- intel_de_write_fw(i915, GMBUS0(i915),
+ intel_de_write_fw(display, GMBUS0(display),
gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
}
- intel_de_write_fw(i915, GMBUS1(i915),
+ intel_de_write_fw(display, GMBUS1(display),
gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
while (len) {
int ret;
u32 val, loop = 0;
- ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
+ ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
if (ret)
return ret;
- val = intel_de_read_fw(i915, GMBUS3(i915));
+ val = intel_de_read_fw(display, GMBUS3(display));
do {
if (extra_byte_added && len == 1)
break;
@@ -469,7 +476,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
if (burst_read && len == size - 4)
/* Reset the override bit */
- intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
+ intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
}
return 0;
@@ -486,9 +493,10 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
#define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
static int
-gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
+gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
u32 gmbus0_reg, u32 gmbus1_index)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
u8 *buf = msg->buf;
unsigned int rx_size = msg->len;
unsigned int len;
@@ -498,9 +506,9 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
if (HAS_GMBUS_BURST_READ(i915))
len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
else
- len = min(rx_size, gmbus_max_xfer_size(i915));
+ len = min(rx_size, gmbus_max_xfer_size(display));
- ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
+ ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
gmbus0_reg, gmbus1_index);
if (ret)
return ret;
@@ -513,7 +521,7 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
}
static int
-gmbus_xfer_write_chunk(struct drm_i915_private *i915,
+gmbus_xfer_write_chunk(struct intel_display *display,
unsigned short addr, u8 *buf, unsigned int len,
u32 gmbus1_index)
{
@@ -526,8 +534,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
len -= 1;
}
- intel_de_write_fw(i915, GMBUS3(i915), val);
- intel_de_write_fw(i915, GMBUS1(i915),
+ intel_de_write_fw(display, GMBUS3(display), val);
+ intel_de_write_fw(display, GMBUS1(display),
gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
while (len) {
int ret;
@@ -537,9 +545,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
val |= *buf++ << (8 * loop);
} while (--len && ++loop < 4);
- intel_de_write_fw(i915, GMBUS3(i915), val);
+ intel_de_write_fw(display, GMBUS3(display), val);
- ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
+ ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
if (ret)
return ret;
}
@@ -548,7 +556,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
}
static int
-gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
+gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
u32 gmbus1_index)
{
u8 *buf = msg->buf;
@@ -557,9 +565,9 @@ gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
int ret;
do {
- len = min(tx_size, gmbus_max_xfer_size(i915));
+ len = min(tx_size, gmbus_max_xfer_size(display));
- ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
+ ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
gmbus1_index);
if (ret)
return ret;
@@ -586,7 +594,7 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
}
static int
-gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
+gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
u32 gmbus0_reg)
{
u32 gmbus1_index = 0;
@@ -602,17 +610,17 @@ gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
/* GMBUS5 holds 16-bit index */
if (gmbus5)
- intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
+ intel_de_write_fw(display, GMBUS5(display), gmbus5);
if (msgs[1].flags & I2C_M_RD)
- ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
+ ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
gmbus1_index);
else
- ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
+ ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
/* Clear GMBUS5 after each index transfer */
if (gmbus5)
- intel_de_write_fw(i915, GMBUS5(i915), 0);
+ intel_de_write_fw(display, GMBUS5(display), 0);
return ret;
}
@@ -622,34 +630,35 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
u32 gmbus0_source)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
int i = 0, inc, try = 0;
int ret = 0;
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- bxt_gmbus_clock_gating(i915, false);
+ bxt_gmbus_clock_gating(display, false);
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
- pch_gmbus_clock_gating(i915, false);
+ pch_gmbus_clock_gating(display, false);
retry:
- intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
+ intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
for (; i < num; i += inc) {
inc = 1;
if (gmbus_is_index_xfer(msgs, i, num)) {
- ret = gmbus_index_xfer(i915, &msgs[i],
+ ret = gmbus_index_xfer(display, &msgs[i],
gmbus0_source | bus->reg0);
inc = 2; /* an index transmission is two msgs */
} else if (msgs[i].flags & I2C_M_RD) {
- ret = gmbus_xfer_read(i915, &msgs[i],
+ ret = gmbus_xfer_read(display, &msgs[i],
gmbus0_source | bus->reg0, 0);
} else {
- ret = gmbus_xfer_write(i915, &msgs[i], 0);
+ ret = gmbus_xfer_write(display, &msgs[i], 0);
}
if (!ret)
- ret = gmbus_wait(i915,
+ ret = gmbus_wait(display,
GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
if (ret == -ETIMEDOUT)
goto timeout;
@@ -661,19 +670,19 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* a STOP on the very first cycle. To simplify the code we
* unconditionally generate the STOP condition with an additional gmbus
* cycle. */
- intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
+ intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
/* Mark the GMBUS interface as disabled after waiting for idle.
* We will re-enable it at the start of the next xfer,
* till then let it sleep.
*/
- if (gmbus_wait_idle(i915)) {
- drm_dbg_kms(&i915->drm,
+ if (gmbus_wait_idle(display)) {
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out waiting for idle\n",
adapter->name);
ret = -ETIMEDOUT;
}
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
ret = ret ?: i;
goto out;
@@ -692,8 +701,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* it's slow responding and only answers on the 2nd retry.
*/
ret = -ENXIO;
- if (gmbus_wait_idle(i915)) {
- drm_dbg_kms(&i915->drm,
+ if (gmbus_wait_idle(display)) {
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out after NAK\n",
adapter->name);
ret = -ETIMEDOUT;
@@ -703,11 +712,11 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* of resetting the GMBUS controller and so clearing the
* BUS_ERROR raised by the target's NAK.
*/
- intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
- intel_de_write_fw(i915, GMBUS1(i915), 0);
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
+ intel_de_write_fw(display, GMBUS1(display), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
- drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
+ drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
adapter->name, msgs[i].addr,
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
@@ -718,7 +727,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
*/
if (ret == -ENXIO && i == 0 && try++ == 0) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"GMBUS [%s] NAK on first message, retry\n",
adapter->name);
goto retry;
@@ -727,10 +736,10 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
goto out;
timeout:
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
bus->adapter.name, bus->reg0 & 0xff);
- intel_de_write_fw(i915, GMBUS0(i915), 0);
+ intel_de_write_fw(display, GMBUS0(display), 0);
/*
* Hardware may not support GMBUS over these pins? Try GPIO bitbanging
@@ -741,9 +750,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
out:
/* Display WA #0868: skl,bxt,kbl,cfl,glk */
if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
- bxt_gmbus_clock_gating(i915, true);
+ bxt_gmbus_clock_gating(display, true);
else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
- pch_gmbus_clock_gating(i915, true);
+ pch_gmbus_clock_gating(display, true);
return ret;
}
@@ -752,7 +761,8 @@ static int
gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
intel_wakeref_t wakeref;
int ret;
@@ -776,7 +786,8 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
+ struct drm_i915_private *i915 = to_i915(display->drm);
u8 cmd = DRM_HDCP_DDC_AKSV;
u8 buf[DRM_HDCP_KSV_LEN] = {};
struct i2c_msg msgs[] = {
@@ -797,7 +808,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
int ret;
wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
/*
* In order to output Aksv to the receiver, use an indexed write to
@@ -806,7 +817,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
*/
ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
return ret;
@@ -830,27 +841,27 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
}
static int gmbus_trylock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- return mutex_trylock(&i915->display.gmbus.mutex);
+ return mutex_trylock(&display->gmbus.mutex);
}
static void gmbus_unlock_bus(struct i2c_adapter *adapter,
unsigned int flags)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
}
static const struct i2c_lock_operations gmbus_lock_ops = {
@@ -861,31 +872,32 @@ static const struct i2c_lock_operations gmbus_lock_ops = {
/**
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
- * @i915: i915 device private
+ * @display: display device
*/
-int intel_gmbus_setup(struct drm_i915_private *i915)
+int intel_gmbus_setup(struct intel_display *display)
{
- struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
+ struct drm_i915_private *i915 = to_i915(display->drm);
+ struct pci_dev *pdev = to_pci_dev(display->drm->dev);
unsigned int pin;
int ret;
if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
- i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
- else if (!HAS_GMCH(i915))
+ display->gmbus.mmio_base = VLV_DISPLAY_BASE;
+ else if (!HAS_GMCH(display))
/*
* Broxton uses the same PCH offsets for South Display Engine,
* even though it doesn't have a PCH.
*/
- i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
+ display->gmbus.mmio_base = PCH_DISPLAY_BASE;
- mutex_init(&i915->display.gmbus.mutex);
- init_waitqueue_head(&i915->display.gmbus.wait_queue);
+ mutex_init(&display->gmbus.mutex);
+ init_waitqueue_head(&display->gmbus.wait_queue);
- for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
const struct gmbus_pin *gmbus_pin;
struct intel_gmbus *bus;
- gmbus_pin = get_gmbus_pin(i915, pin);
+ gmbus_pin = get_gmbus_pin(display, pin);
if (!gmbus_pin)
continue;
@@ -901,7 +913,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
"i915 gmbus %s", gmbus_pin->name);
bus->adapter.dev.parent = &pdev->dev;
- bus->i915 = i915;
+ bus->display = display;
bus->adapter.algo = &gmbus_algorithm;
bus->adapter.lock_ops = &gmbus_lock_ops;
@@ -919,7 +931,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
if (IS_I830(i915))
bus->force_bit = 1;
- intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
+ intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
ret = i2c_add_adapter(&bus->adapter);
if (ret) {
@@ -927,43 +939,43 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
goto err;
}
- i915->display.gmbus.bus[pin] = bus;
+ display->gmbus.bus[pin] = bus;
}
- intel_gmbus_reset(i915);
+ intel_gmbus_reset(display);
return 0;
err:
- intel_gmbus_teardown(i915);
+ intel_gmbus_teardown(display);
return ret;
}
-struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
+struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
unsigned int pin)
{
- if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
- !i915->display.gmbus.bus[pin]))
+ if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
+ !display->gmbus.bus[pin]))
return NULL;
- return &i915->display.gmbus.bus[pin]->adapter;
+ return &display->gmbus.bus[pin]->adapter;
}
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
struct intel_gmbus *bus = to_intel_gmbus(adapter);
- struct drm_i915_private *i915 = bus->i915;
+ struct intel_display *display = bus->display;
- mutex_lock(&i915->display.gmbus.mutex);
+ mutex_lock(&display->gmbus.mutex);
bus->force_bit += force_bit ? 1 : -1;
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"%sabling bit-banging on %s. force bit now %d\n",
force_bit ? "en" : "dis", adapter->name,
bus->force_bit);
- mutex_unlock(&i915->display.gmbus.mutex);
+ mutex_unlock(&display->gmbus.mutex);
}
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
@@ -973,25 +985,25 @@ bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
return bus->force_bit;
}
-void intel_gmbus_teardown(struct drm_i915_private *i915)
+void intel_gmbus_teardown(struct intel_display *display)
{
unsigned int pin;
- for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
+ for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
struct intel_gmbus *bus;
- bus = i915->display.gmbus.bus[pin];
+ bus = display->gmbus.bus[pin];
if (!bus)
continue;
i2c_del_adapter(&bus->adapter);
kfree(bus);
- i915->display.gmbus.bus[pin] = NULL;
+ display->gmbus.bus[pin] = NULL;
}
}
-void intel_gmbus_irq_handler(struct drm_i915_private *i915)
+void intel_gmbus_irq_handler(struct intel_display *display)
{
- wake_up_all(&i915->display.gmbus.wait_queue);
+ wake_up_all(&display->gmbus.wait_queue);
}
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
index 8111eb23e2af..35a200a9efc0 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
@@ -8,8 +8,8 @@
#include <linux/types.h>
-struct drm_i915_private;
struct i2c_adapter;
+struct intel_display;
#define GMBUS_PIN_DISABLED 0
#define GMBUS_PIN_SSC 1
@@ -34,18 +34,17 @@ struct i2c_adapter;
#define GMBUS_NUM_PINS 15 /* including 0 */
-int intel_gmbus_setup(struct drm_i915_private *dev_priv);
-void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
-bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
- unsigned int pin);
+int intel_gmbus_setup(struct intel_display *display);
+void intel_gmbus_teardown(struct intel_display *display);
+bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
struct i2c_adapter *
-intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
+intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
-void intel_gmbus_reset(struct drm_i915_private *dev_priv);
+void intel_gmbus_reset(struct intel_display *display);
-void intel_gmbus_irq_handler(struct drm_i915_private *i915);
+void intel_gmbus_irq_handler(struct intel_display *display);
#endif /* __INTEL_GMBUS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
index 53aacbda983c..59bad1dda6d6 100644
--- a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
@@ -8,9 +8,9 @@
#include "i915_reg_defs.h"
-#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
+#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)
-#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
+#define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
#define GPIO_CLOCK_DIR_MASK (1 << 0)
#define GPIO_CLOCK_DIR_IN (0 << 1)
#define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -27,7 +27,7 @@
#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
/* clock/port select */
-#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
+#define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
#define GMBUS_AKSV_SELECT (1 << 11)
#define GMBUS_RATE_100KHZ (0 << 8)
#define GMBUS_RATE_50KHZ (1 << 8)
@@ -37,7 +37,7 @@
#define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
/* command/status */
-#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
+#define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
#define GMBUS_SW_CLR_INT (1 << 31)
#define GMBUS_SW_RDY (1 << 30)
#define GMBUS_ENT (1 << 29) /* enable timeout */
@@ -54,7 +54,7 @@
#define GMBUS_SLAVE_WRITE (0 << 0)
/* status */
-#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
+#define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
#define GMBUS_INUSE (1 << 15)
#define GMBUS_HW_WAIT_PHASE (1 << 14)
#define GMBUS_STALL_TIMEOUT (1 << 13)
@@ -64,10 +64,10 @@
#define GMBUS_ACTIVE (1 << 9)
/* data buffer bytes 3-0 */
-#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
+#define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
/* interrupt mask (Pineview+) */
-#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
+#define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
#define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
#define GMBUS_NAK_EN (1 << 3)
#define GMBUS_IDLE_EN (1 << 2)
@@ -75,7 +75,7 @@
#define GMBUS_HW_RDY_EN (1 << 0)
/* byte index */
-#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
+#define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
#define GMBUS_2BYTE_INDEX_EN (1 << 31)
#endif /* __INTEL_GMBUS_REGS_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 72ac910bf6ec..022ba3635101 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -2917,7 +2917,6 @@ static struct intel_encoder *
get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_encoder *other;
for_each_intel_encoder(display->drm, other) {
@@ -2931,7 +2930,7 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
connector = enc_to_dig_port(other)->hdmi.attached_connector;
- if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
+ if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
return other;
}
@@ -2941,7 +2940,6 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
{
struct intel_display *display = to_intel_display(encoder);
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_encoder *other;
const char *source;
u8 ddc_pin;
@@ -2954,7 +2952,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
source = "platform default";
}
- if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
+ if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
drm_dbg_kms(display->drm,
"[ENCODER:%d:%s] Invalid DDC pin %d\n",
encoder->base.base.id, encoder->base.name, ddc_pin);
@@ -3052,7 +3050,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
drm_connector_init_with_ddc(dev, connector,
&intel_hdmi_connector_funcs,
DRM_MODE_CONNECTOR_HDMIA,
- intel_gmbus_get_adapter(dev_priv, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
index 5d055dc9366f..cb64c6f0ad1b 100644
--- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
+++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
@@ -556,6 +556,7 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct intel_display *display = &dev_priv->display;
u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
u32 pin_mask = 0, long_mask = 0;
@@ -589,11 +590,12 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_ICP)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct intel_display *display = &dev_priv->display;
u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
~SDE_PORTE_HOTPLUG_SPT;
u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
@@ -625,7 +627,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
if (pch_iir & SDE_GMBUS_CPT)
- intel_gmbus_irq_handler(dev_priv);
+ intel_gmbus_irq_handler(display);
}
void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 5f753ee743c6..96fa238b461d 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -900,7 +900,7 @@ void intel_lvds_init(struct drm_i915_private *i915)
drm_connector_init_with_ddc(&i915->drm, &connector->base,
&intel_lvds_connector_funcs,
DRM_MODE_CONNECTOR_LVDS,
- intel_gmbus_get_adapter(i915, ddc_pin));
+ intel_gmbus_get_adapter(display, ddc_pin));
drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
DRM_MODE_ENCODER_LVDS, "LVDS");
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index b83bf813677d..7a28104f68ad 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -2082,10 +2082,10 @@ intel_sdvo_get_edid(struct drm_connector *connector)
static const struct drm_edid *
intel_sdvo_get_analog_edid(struct drm_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(connector->dev);
+ struct intel_display *display = to_intel_display(connector->dev);
struct i2c_adapter *ddc;
- ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
+ ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);
if (!ddc)
return NULL;
@@ -2638,6 +2638,7 @@ intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
static void
intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
{
+ struct intel_display *display = to_intel_display(&sdvo->base);
struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
const struct sdvo_device_mapping *mapping;
u8 pin;
@@ -2648,7 +2649,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
mapping = &dev_priv->display.vbt.sdvo_mappings[1];
if (mapping->initialized &&
- intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
+ intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
pin = mapping->i2c_pin;
else
pin = GMBUS_PIN_DPB;
@@ -2657,7 +2658,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
sdvo->base.base.base.id, sdvo->base.base.name,
pin, sdvo->target_addr);
- sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
+ sdvo->i2c = intel_gmbus_get_adapter(display, pin);
/*
* With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 9d3d9b983032..f18f1acf2158 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -137,5 +137,5 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
intel_vga_redisable(display);
- intel_gmbus_reset(dev_priv);
+ intel_gmbus_reset(display);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display Jani Nikula
@ 2024-10-23 14:51 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 14:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:18PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch gmbus code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_bios.c | 6 +-
> drivers/gpu/drm/i915/display/intel_crt.c | 6 +-
> .../drm/i915/display/intel_display_driver.c | 4 +-
> .../gpu/drm/i915/display/intel_display_irq.c | 11 +-
> drivers/gpu/drm/i915/display/intel_dsi_vbt.c | 5 +-
> drivers/gpu/drm/i915/display/intel_dvo.c | 8 +-
> drivers/gpu/drm/i915/display/intel_gmbus.c | 290 +++++++++---------
> drivers/gpu/drm/i915/display/intel_gmbus.h | 15 +-
> .../gpu/drm/i915/display/intel_gmbus_regs.h | 16 +-
> drivers/gpu/drm/i915/display/intel_hdmi.c | 8 +-
> .../gpu/drm/i915/display/intel_hotplug_irq.c | 6 +-
> drivers/gpu/drm/i915/display/intel_lvds.c | 2 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
> drivers/gpu/drm/i915/i915_suspend.c | 2 +-
> 14 files changed, 202 insertions(+), 186 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_bios.c b/drivers/gpu/drm/i915/display/intel_bios.c
> index 9967b65e3cf6..48c010b5b150 100644
> --- a/drivers/gpu/drm/i915/display/intel_bios.c
> +++ b/drivers/gpu/drm/i915/display/intel_bios.c
> @@ -2796,7 +2796,6 @@ static bool child_device_size_valid(struct intel_display *display, int size)
> static void
> parse_general_definitions(struct intel_display *display)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> const struct bdb_general_definitions *defs;
> struct intel_bios_encoder_data *devdata;
> const struct child_device_config *child;
> @@ -2821,7 +2820,7 @@ parse_general_definitions(struct intel_display *display)
>
> bus_pin = defs->crt_ddc_gmbus_pin;
> drm_dbg_kms(display->drm, "crt_ddc_bus_pin: %d\n", bus_pin);
> - if (intel_gmbus_is_valid_pin(i915, bus_pin))
> + if (intel_gmbus_is_valid_pin(display, bus_pin))
> display->vbt.crt_ddc_pin = bus_pin;
>
> if (!child_device_size_valid(display, defs->child_dev_size))
> @@ -3338,7 +3337,6 @@ bool intel_bios_is_tv_present(struct intel_display *display)
> */
> bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
> {
> - struct drm_i915_private *i915 = to_i915(display->drm);
> const struct intel_bios_encoder_data *devdata;
>
> if (list_empty(&display->vbt.display_devices))
> @@ -3355,7 +3353,7 @@ bool intel_bios_is_lvds_present(struct intel_display *display, u8 *i2c_pin)
> child->device_type != DEVICE_TYPE_LFP)
> continue;
>
> - if (intel_gmbus_is_valid_pin(i915, child->i2c_pin))
> + if (intel_gmbus_is_valid_pin(display, child->i2c_pin))
> *i2c_pin = child->i2c_pin;
>
> /* However, we cannot trust the BIOS writers to populate
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index fd78adbaadbe..8222b1c251db 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -935,6 +935,7 @@ intel_crt_detect(struct drm_connector *connector,
>
> static int intel_crt_get_modes(struct drm_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
> @@ -954,7 +955,7 @@ static int intel_crt_get_modes(struct drm_connector *connector)
> goto out;
>
> /* Try to probe digital port for output in DVI-I -> VGA mode. */
> - ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
> + ddc = intel_gmbus_get_adapter(display, GMBUS_PIN_DPB);
> ret = intel_crt_ddc_get_modes(connector, ddc);
>
> out:
> @@ -1009,6 +1010,7 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
>
> void intel_crt_init(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct drm_connector *connector;
> struct intel_crt *crt;
> struct intel_connector *intel_connector;
> @@ -1057,7 +1059,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> drm_connector_init_with_ddc(&dev_priv->drm, connector,
> &intel_crt_connector_funcs,
> DRM_MODE_CONNECTOR_VGA,
> - intel_gmbus_get_adapter(dev_priv, ddc_pin));
> + intel_gmbus_get_adapter(display, ddc_pin));
>
> drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
> DRM_MODE_ENCODER_DAC, "CRT");
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index 673f9b965494..ae5470078173 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -432,7 +432,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
>
> intel_pps_setup(display);
>
> - intel_gmbus_setup(i915);
> + intel_gmbus_setup(display);
>
> drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
> INTEL_NUM_PIPES(i915),
> @@ -608,7 +608,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
>
> intel_overlay_cleanup(i915);
>
> - intel_gmbus_teardown(i915);
> + intel_gmbus_teardown(display);
>
> destroy_workqueue(i915->display.wq.flip);
> destroy_workqueue(i915->display.wq.modeset);
> diff --git a/drivers/gpu/drm/i915/display/intel_display_irq.c b/drivers/gpu/drm/i915/display/intel_display_irq.c
> index a4f42ed3f21a..0478fe3cdd86 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_irq.c
> @@ -543,12 +543,13 @@ void i965_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> intel_opregion_asle_intr(display);
>
> if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
> }
>
> void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> u32 pipe_stats[I915_MAX_PIPES])
> {
> + struct intel_display *display = &dev_priv->display;
> enum pipe pipe;
>
> for_each_pipe(dev_priv, pipe) {
> @@ -566,7 +567,7 @@ void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv,
> }
>
> if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
> }
>
> static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> @@ -588,7 +589,7 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_dp_aux_irq_handler(display);
>
> if (pch_iir & SDE_GMBUS)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
>
> if (pch_iir & SDE_AUDIO_HDCP_MASK)
> drm_dbg(&dev_priv->drm, "PCH HDCP audio interrupt\n");
> @@ -677,7 +678,7 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_dp_aux_irq_handler(display);
>
> if (pch_iir & SDE_GMBUS_CPT)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
>
> if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
> drm_dbg(&dev_priv->drm, "Audio CP request interrupt\n");
> @@ -1109,7 +1110,7 @@ void gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
>
> if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
> (iir & BXT_DE_PORT_GMBUS)) {
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
> found = true;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> index f0e3be0fe420..e8129a720210 100644
> --- a/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/display/intel_dsi_vbt.c
> @@ -323,6 +323,7 @@ enum {
> static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
> int gpio, bool value)
> {
> + struct intel_display *display = &dev_priv->display;
> int index;
>
> if (drm_WARN_ON(&dev_priv->drm, DISPLAY_VER(dev_priv) == 11 && gpio >= MIPI_RESET_2))
> @@ -367,7 +368,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
> case MIPI_AVEE_EN_2:
> index = gpio == MIPI_AVEE_EN_1 ? 1 : 2;
>
> - intel_de_rmw(dev_priv, GPIO(dev_priv, index),
> + intel_de_rmw(display, GPIO(display, index),
> GPIO_CLOCK_VAL_OUT,
> GPIO_CLOCK_DIR_MASK | GPIO_CLOCK_DIR_OUT |
> GPIO_CLOCK_VAL_MASK | (value ? GPIO_CLOCK_VAL_OUT : 0));
> @@ -376,7 +377,7 @@ static void icl_native_gpio_set_value(struct drm_i915_private *dev_priv,
> case MIPI_VIO_EN_2:
> index = gpio == MIPI_VIO_EN_1 ? 1 : 2;
>
> - intel_de_rmw(dev_priv, GPIO(dev_priv, index),
> + intel_de_rmw(display, GPIO(display, index),
> GPIO_DATA_VAL_OUT,
> GPIO_DATA_DIR_MASK | GPIO_DATA_DIR_OUT |
> GPIO_DATA_VAL_MASK | (value ? GPIO_DATA_VAL_OUT : 0));
> diff --git a/drivers/gpu/drm/i915/display/intel_dvo.c b/drivers/gpu/drm/i915/display/intel_dvo.c
> index 9508ceae0d84..2d5ffb37eac9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_dvo.c
> @@ -417,6 +417,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
> struct intel_dvo *intel_dvo,
> const struct intel_dvo_device *dvo)
> {
> + struct intel_display *display = &dev_priv->display;
> struct i2c_adapter *i2c;
> u32 dpll[I915_MAX_PIPES];
> enum pipe pipe;
> @@ -428,7 +429,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
> * special cases, but otherwise default to what's defined
> * in the spec.
> */
> - if (intel_gmbus_is_valid_pin(dev_priv, dvo->gpio))
> + if (intel_gmbus_is_valid_pin(display, dvo->gpio))
> gpio = dvo->gpio;
> else if (dvo->type == INTEL_DVO_CHIP_LVDS)
> gpio = GMBUS_PIN_SSC;
> @@ -440,7 +441,7 @@ static bool intel_dvo_init_dev(struct drm_i915_private *dev_priv,
> * It appears that everything is on GPIOE except for panels
> * on i830 laptops, which are on GPIOB (DVOA).
> */
> - i2c = intel_gmbus_get_adapter(dev_priv, gpio);
> + i2c = intel_gmbus_get_adapter(display, gpio);
>
> intel_dvo->dev = *dvo;
>
> @@ -489,6 +490,7 @@ static bool intel_dvo_probe(struct drm_i915_private *i915,
>
> void intel_dvo_init(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> struct intel_connector *connector;
> struct intel_encoder *encoder;
> struct intel_dvo *intel_dvo;
> @@ -549,7 +551,7 @@ void intel_dvo_init(struct drm_i915_private *i915)
> drm_connector_init_with_ddc(&i915->drm, &connector->base,
> &intel_dvo_connector_funcs,
> intel_dvo_connector_type(&intel_dvo->dev),
> - intel_gmbus_get_adapter(i915, GMBUS_PIN_DPC));
> + intel_gmbus_get_adapter(display, GMBUS_PIN_DPC));
>
> drm_connector_helper_add(&connector->base,
> &intel_dvo_connector_helper_funcs);
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.c b/drivers/gpu/drm/i915/display/intel_gmbus.c
> index 6470f75106bd..e3d938c7f83e 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.c
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.c
> @@ -48,7 +48,7 @@ struct intel_gmbus {
> u32 reg0;
> i915_reg_t gpio_reg;
> struct i2c_algo_bit_data bit_algo;
> - struct drm_i915_private *i915;
> + struct intel_display *display;
> };
>
> enum gmbus_gpio {
> @@ -149,9 +149,10 @@ static const struct gmbus_pin gmbus_pins_mtp[] = {
> [GMBUS_PIN_12_TC4_ICP] = { "tc4", GPIOM },
> };
>
> -static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> +static const struct gmbus_pin *get_gmbus_pin(struct intel_display *display,
> unsigned int pin)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
hmmm! Great idea!
So we the other conversion doesn't block this to go in parallel!
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> const struct gmbus_pin *pins;
> size_t size;
>
> @@ -173,7 +174,7 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
> pins = gmbus_pins_bxt;
> size = ARRAY_SIZE(gmbus_pins_bxt);
> - } else if (DISPLAY_VER(i915) == 9) {
> + } else if (DISPLAY_VER(display) == 9) {
> pins = gmbus_pins_skl;
> size = ARRAY_SIZE(gmbus_pins_skl);
> } else if (IS_BROADWELL(i915)) {
> @@ -190,9 +191,9 @@ static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *i915,
> return &pins[pin];
> }
>
> -bool intel_gmbus_is_valid_pin(struct drm_i915_private *i915, unsigned int pin)
> +bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin)
> {
> - return get_gmbus_pin(i915, pin);
> + return get_gmbus_pin(display, pin);
> }
>
> /* Intel GPIO access functions */
> @@ -206,42 +207,45 @@ to_intel_gmbus(struct i2c_adapter *i2c)
> }
>
> void
> -intel_gmbus_reset(struct drm_i915_private *i915)
> +intel_gmbus_reset(struct intel_display *display)
> {
> - intel_de_write(i915, GMBUS0(i915), 0);
> - intel_de_write(i915, GMBUS4(i915), 0);
> + intel_de_write(display, GMBUS0(display), 0);
> + intel_de_write(display, GMBUS4(display), 0);
> }
>
> -static void pnv_gmbus_clock_gating(struct drm_i915_private *i915,
> +static void pnv_gmbus_clock_gating(struct intel_display *display,
> bool enable)
> {
> /* When using bit bashing for I2C, this bit needs to be set to 1 */
> - intel_de_rmw(i915, DSPCLK_GATE_D(i915), PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
> + intel_de_rmw(display, DSPCLK_GATE_D(display),
> + PNV_GMBUSUNIT_CLOCK_GATE_DISABLE,
> !enable ? PNV_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
> }
>
> -static void pch_gmbus_clock_gating(struct drm_i915_private *i915,
> +static void pch_gmbus_clock_gating(struct intel_display *display,
> bool enable)
> {
> - intel_de_rmw(i915, SOUTH_DSPCLK_GATE_D, PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
> + intel_de_rmw(display, SOUTH_DSPCLK_GATE_D,
> + PCH_GMBUSUNIT_CLOCK_GATE_DISABLE,
> !enable ? PCH_GMBUSUNIT_CLOCK_GATE_DISABLE : 0);
> }
>
> -static void bxt_gmbus_clock_gating(struct drm_i915_private *i915,
> +static void bxt_gmbus_clock_gating(struct intel_display *display,
> bool enable)
> {
> - intel_de_rmw(i915, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
> + intel_de_rmw(display, GEN9_CLKGATE_DIS_4, BXT_GMBUS_GATING_DIS,
> !enable ? BXT_GMBUS_GATING_DIS : 0);
> }
>
> static u32 get_reserved(struct intel_gmbus *bus)
> {
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u32 reserved = 0;
>
> /* On most chips, these bits must be preserved in software. */
> if (!IS_I830(i915) && !IS_I845G(i915))
> - reserved = intel_de_read_notrace(i915, bus->gpio_reg) &
> + reserved = intel_de_read_notrace(display, bus->gpio_reg) &
> (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
>
> return reserved;
> @@ -250,31 +254,31 @@ static u32 get_reserved(struct intel_gmbus *bus)
> static int get_clock(void *data)
> {
> struct intel_gmbus *bus = data;
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> u32 reserved = get_reserved(bus);
>
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved);
>
> - return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
> + return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
> }
>
> static int get_data(void *data)
> {
> struct intel_gmbus *bus = data;
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> u32 reserved = get_reserved(bus);
>
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved);
>
> - return (intel_de_read_notrace(i915, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
> + return (intel_de_read_notrace(display, bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
> }
>
> static void set_clock(void *data, int state_high)
> {
> struct intel_gmbus *bus = data;
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> u32 reserved = get_reserved(bus);
> u32 clock_bits;
>
> @@ -284,14 +288,14 @@ static void set_clock(void *data, int state_high)
> clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
> GPIO_CLOCK_VAL_MASK;
>
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved | clock_bits);
> - intel_de_posting_read(i915, bus->gpio_reg);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved | clock_bits);
> + intel_de_posting_read(display, bus->gpio_reg);
> }
>
> static void set_data(void *data, int state_high)
> {
> struct intel_gmbus *bus = data;
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> u32 reserved = get_reserved(bus);
> u32 data_bits;
>
> @@ -301,20 +305,21 @@ static void set_data(void *data, int state_high)
> data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
> GPIO_DATA_VAL_MASK;
>
> - intel_de_write_notrace(i915, bus->gpio_reg, reserved | data_bits);
> - intel_de_posting_read(i915, bus->gpio_reg);
> + intel_de_write_notrace(display, bus->gpio_reg, reserved | data_bits);
> + intel_de_posting_read(display, bus->gpio_reg);
> }
>
> static int
> intel_gpio_pre_xfer(struct i2c_adapter *adapter)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> - intel_gmbus_reset(i915);
> + intel_gmbus_reset(display);
>
> if (IS_PINEVIEW(i915))
> - pnv_gmbus_clock_gating(i915, false);
> + pnv_gmbus_clock_gating(display, false);
>
> set_data(bus, 1);
> set_clock(bus, 1);
> @@ -326,13 +331,14 @@ static void
> intel_gpio_post_xfer(struct i2c_adapter *adapter)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> set_data(bus, 1);
> set_clock(bus, 1);
>
> if (IS_PINEVIEW(i915))
> - pnv_gmbus_clock_gating(i915, true);
> + pnv_gmbus_clock_gating(display, true);
> }
>
> static void
> @@ -355,16 +361,17 @@ intel_gpio_setup(struct intel_gmbus *bus, i915_reg_t gpio_reg)
> algo->data = bus;
> }
>
> -static bool has_gmbus_irq(struct drm_i915_private *i915)
> +static bool has_gmbus_irq(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> /*
> * encoder->shutdown() may want to use GMBUS
> * after irqs have already been disabled.
> */
> - return HAS_GMBUS_IRQ(i915) && intel_irqs_enabled(i915);
> + return HAS_GMBUS_IRQ(display) && intel_irqs_enabled(i915);
> }
>
> -static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
> +static int gmbus_wait(struct intel_display *display, u32 status, u32 irq_en)
> {
> DEFINE_WAIT(wait);
> u32 gmbus2;
> @@ -374,21 +381,21 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
> * we also need to check for NAKs besides the hw ready/idle signal, we
> * need to wake up periodically and check that ourselves.
> */
> - if (!has_gmbus_irq(i915))
> + if (!has_gmbus_irq(display))
> irq_en = 0;
>
> - add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
> - intel_de_write_fw(i915, GMBUS4(i915), irq_en);
> + add_wait_queue(&display->gmbus.wait_queue, &wait);
> + intel_de_write_fw(display, GMBUS4(display), irq_en);
>
> status |= GMBUS_SATOER;
> - ret = wait_for_us((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
> + ret = wait_for_us((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
> 2);
> if (ret)
> - ret = wait_for((gmbus2 = intel_de_read_fw(i915, GMBUS2(i915))) & status,
> + ret = wait_for((gmbus2 = intel_de_read_fw(display, GMBUS2(display))) & status,
> 50);
>
> - intel_de_write_fw(i915, GMBUS4(i915), 0);
> - remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
> + intel_de_write_fw(display, GMBUS4(display), 0);
> + remove_wait_queue(&display->gmbus.wait_queue, &wait);
>
> if (gmbus2 & GMBUS_SATOER)
> return -ENXIO;
> @@ -397,7 +404,7 @@ static int gmbus_wait(struct drm_i915_private *i915, u32 status, u32 irq_en)
> }
>
> static int
> -gmbus_wait_idle(struct drm_i915_private *i915)
> +gmbus_wait_idle(struct intel_display *display)
> {
> DEFINE_WAIT(wait);
> u32 irq_enable;
> @@ -405,33 +412,33 @@ gmbus_wait_idle(struct drm_i915_private *i915)
>
> /* Important: The hw handles only the first bit, so set only one! */
> irq_enable = 0;
> - if (has_gmbus_irq(i915))
> + if (has_gmbus_irq(display))
> irq_enable = GMBUS_IDLE_EN;
>
> - add_wait_queue(&i915->display.gmbus.wait_queue, &wait);
> - intel_de_write_fw(i915, GMBUS4(i915), irq_enable);
> + add_wait_queue(&display->gmbus.wait_queue, &wait);
> + intel_de_write_fw(display, GMBUS4(display), irq_enable);
>
> - ret = intel_de_wait_fw(i915, GMBUS2(i915), GMBUS_ACTIVE, 0, 10);
> + ret = intel_de_wait_fw(display, GMBUS2(display), GMBUS_ACTIVE, 0, 10);
>
> - intel_de_write_fw(i915, GMBUS4(i915), 0);
> - remove_wait_queue(&i915->display.gmbus.wait_queue, &wait);
> + intel_de_write_fw(display, GMBUS4(display), 0);
> + remove_wait_queue(&display->gmbus.wait_queue, &wait);
>
> return ret;
> }
>
> -static unsigned int gmbus_max_xfer_size(struct drm_i915_private *i915)
> +static unsigned int gmbus_max_xfer_size(struct intel_display *display)
> {
> - return DISPLAY_VER(i915) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
> + return DISPLAY_VER(display) >= 9 ? GEN9_GMBUS_BYTE_COUNT_MAX :
> GMBUS_BYTE_COUNT_MAX;
> }
>
> static int
> -gmbus_xfer_read_chunk(struct drm_i915_private *i915,
> +gmbus_xfer_read_chunk(struct intel_display *display,
> unsigned short addr, u8 *buf, unsigned int len,
> u32 gmbus0_reg, u32 gmbus1_index)
> {
> unsigned int size = len;
> - bool burst_read = len > gmbus_max_xfer_size(i915);
> + bool burst_read = len > gmbus_max_xfer_size(display);
> bool extra_byte_added = false;
>
> if (burst_read) {
> @@ -444,21 +451,21 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
> len++;
> }
> size = len % 256 + 256;
> - intel_de_write_fw(i915, GMBUS0(i915),
> + intel_de_write_fw(display, GMBUS0(display),
> gmbus0_reg | GMBUS_BYTE_CNT_OVERRIDE);
> }
>
> - intel_de_write_fw(i915, GMBUS1(i915),
> + intel_de_write_fw(display, GMBUS1(display),
> gmbus1_index | GMBUS_CYCLE_WAIT | (size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_READ | GMBUS_SW_RDY);
> while (len) {
> int ret;
> u32 val, loop = 0;
>
> - ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
> + ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
> if (ret)
> return ret;
>
> - val = intel_de_read_fw(i915, GMBUS3(i915));
> + val = intel_de_read_fw(display, GMBUS3(display));
> do {
> if (extra_byte_added && len == 1)
> break;
> @@ -469,7 +476,7 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
>
> if (burst_read && len == size - 4)
> /* Reset the override bit */
> - intel_de_write_fw(i915, GMBUS0(i915), gmbus0_reg);
> + intel_de_write_fw(display, GMBUS0(display), gmbus0_reg);
> }
>
> return 0;
> @@ -486,9 +493,10 @@ gmbus_xfer_read_chunk(struct drm_i915_private *i915,
> #define INTEL_GMBUS_BURST_READ_MAX_LEN 767U
>
> static int
> -gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
> +gmbus_xfer_read(struct intel_display *display, struct i2c_msg *msg,
> u32 gmbus0_reg, u32 gmbus1_index)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u8 *buf = msg->buf;
> unsigned int rx_size = msg->len;
> unsigned int len;
> @@ -498,9 +506,9 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
> if (HAS_GMBUS_BURST_READ(i915))
> len = min(rx_size, INTEL_GMBUS_BURST_READ_MAX_LEN);
> else
> - len = min(rx_size, gmbus_max_xfer_size(i915));
> + len = min(rx_size, gmbus_max_xfer_size(display));
>
> - ret = gmbus_xfer_read_chunk(i915, msg->addr, buf, len,
> + ret = gmbus_xfer_read_chunk(display, msg->addr, buf, len,
> gmbus0_reg, gmbus1_index);
> if (ret)
> return ret;
> @@ -513,7 +521,7 @@ gmbus_xfer_read(struct drm_i915_private *i915, struct i2c_msg *msg,
> }
>
> static int
> -gmbus_xfer_write_chunk(struct drm_i915_private *i915,
> +gmbus_xfer_write_chunk(struct intel_display *display,
> unsigned short addr, u8 *buf, unsigned int len,
> u32 gmbus1_index)
> {
> @@ -526,8 +534,8 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
> len -= 1;
> }
>
> - intel_de_write_fw(i915, GMBUS3(i915), val);
> - intel_de_write_fw(i915, GMBUS1(i915),
> + intel_de_write_fw(display, GMBUS3(display), val);
> + intel_de_write_fw(display, GMBUS1(display),
> gmbus1_index | GMBUS_CYCLE_WAIT | (chunk_size << GMBUS_BYTE_COUNT_SHIFT) | (addr << GMBUS_SLAVE_ADDR_SHIFT) | GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
> while (len) {
> int ret;
> @@ -537,9 +545,9 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
> val |= *buf++ << (8 * loop);
> } while (--len && ++loop < 4);
>
> - intel_de_write_fw(i915, GMBUS3(i915), val);
> + intel_de_write_fw(display, GMBUS3(display), val);
>
> - ret = gmbus_wait(i915, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
> + ret = gmbus_wait(display, GMBUS_HW_RDY, GMBUS_HW_RDY_EN);
> if (ret)
> return ret;
> }
> @@ -548,7 +556,7 @@ gmbus_xfer_write_chunk(struct drm_i915_private *i915,
> }
>
> static int
> -gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
> +gmbus_xfer_write(struct intel_display *display, struct i2c_msg *msg,
> u32 gmbus1_index)
> {
> u8 *buf = msg->buf;
> @@ -557,9 +565,9 @@ gmbus_xfer_write(struct drm_i915_private *i915, struct i2c_msg *msg,
> int ret;
>
> do {
> - len = min(tx_size, gmbus_max_xfer_size(i915));
> + len = min(tx_size, gmbus_max_xfer_size(display));
>
> - ret = gmbus_xfer_write_chunk(i915, msg->addr, buf, len,
> + ret = gmbus_xfer_write_chunk(display, msg->addr, buf, len,
> gmbus1_index);
> if (ret)
> return ret;
> @@ -586,7 +594,7 @@ gmbus_is_index_xfer(struct i2c_msg *msgs, int i, int num)
> }
>
> static int
> -gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
> +gmbus_index_xfer(struct intel_display *display, struct i2c_msg *msgs,
> u32 gmbus0_reg)
> {
> u32 gmbus1_index = 0;
> @@ -602,17 +610,17 @@ gmbus_index_xfer(struct drm_i915_private *i915, struct i2c_msg *msgs,
>
> /* GMBUS5 holds 16-bit index */
> if (gmbus5)
> - intel_de_write_fw(i915, GMBUS5(i915), gmbus5);
> + intel_de_write_fw(display, GMBUS5(display), gmbus5);
>
> if (msgs[1].flags & I2C_M_RD)
> - ret = gmbus_xfer_read(i915, &msgs[1], gmbus0_reg,
> + ret = gmbus_xfer_read(display, &msgs[1], gmbus0_reg,
> gmbus1_index);
> else
> - ret = gmbus_xfer_write(i915, &msgs[1], gmbus1_index);
> + ret = gmbus_xfer_write(display, &msgs[1], gmbus1_index);
>
> /* Clear GMBUS5 after each index transfer */
> if (gmbus5)
> - intel_de_write_fw(i915, GMBUS5(i915), 0);
> + intel_de_write_fw(display, GMBUS5(display), 0);
>
> return ret;
> }
> @@ -622,34 +630,35 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> u32 gmbus0_source)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> int i = 0, inc, try = 0;
> int ret = 0;
>
> /* Display WA #0868: skl,bxt,kbl,cfl,glk */
> if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> - bxt_gmbus_clock_gating(i915, false);
> + bxt_gmbus_clock_gating(display, false);
> else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
> - pch_gmbus_clock_gating(i915, false);
> + pch_gmbus_clock_gating(display, false);
>
> retry:
> - intel_de_write_fw(i915, GMBUS0(i915), gmbus0_source | bus->reg0);
> + intel_de_write_fw(display, GMBUS0(display), gmbus0_source | bus->reg0);
>
> for (; i < num; i += inc) {
> inc = 1;
> if (gmbus_is_index_xfer(msgs, i, num)) {
> - ret = gmbus_index_xfer(i915, &msgs[i],
> + ret = gmbus_index_xfer(display, &msgs[i],
> gmbus0_source | bus->reg0);
> inc = 2; /* an index transmission is two msgs */
> } else if (msgs[i].flags & I2C_M_RD) {
> - ret = gmbus_xfer_read(i915, &msgs[i],
> + ret = gmbus_xfer_read(display, &msgs[i],
> gmbus0_source | bus->reg0, 0);
> } else {
> - ret = gmbus_xfer_write(i915, &msgs[i], 0);
> + ret = gmbus_xfer_write(display, &msgs[i], 0);
> }
>
> if (!ret)
> - ret = gmbus_wait(i915,
> + ret = gmbus_wait(display,
> GMBUS_HW_WAIT_PHASE, GMBUS_HW_WAIT_EN);
> if (ret == -ETIMEDOUT)
> goto timeout;
> @@ -661,19 +670,19 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * a STOP on the very first cycle. To simplify the code we
> * unconditionally generate the STOP condition with an additional gmbus
> * cycle. */
> - intel_de_write_fw(i915, GMBUS1(i915), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
> + intel_de_write_fw(display, GMBUS1(display), GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
>
> /* Mark the GMBUS interface as disabled after waiting for idle.
> * We will re-enable it at the start of the next xfer,
> * till then let it sleep.
> */
> - if (gmbus_wait_idle(i915)) {
> - drm_dbg_kms(&i915->drm,
> + if (gmbus_wait_idle(display)) {
> + drm_dbg_kms(display->drm,
> "GMBUS [%s] timed out waiting for idle\n",
> adapter->name);
> ret = -ETIMEDOUT;
> }
> - intel_de_write_fw(i915, GMBUS0(i915), 0);
> + intel_de_write_fw(display, GMBUS0(display), 0);
> ret = ret ?: i;
> goto out;
>
> @@ -692,8 +701,8 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * it's slow responding and only answers on the 2nd retry.
> */
> ret = -ENXIO;
> - if (gmbus_wait_idle(i915)) {
> - drm_dbg_kms(&i915->drm,
> + if (gmbus_wait_idle(display)) {
> + drm_dbg_kms(display->drm,
> "GMBUS [%s] timed out after NAK\n",
> adapter->name);
> ret = -ETIMEDOUT;
> @@ -703,11 +712,11 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * of resetting the GMBUS controller and so clearing the
> * BUS_ERROR raised by the target's NAK.
> */
> - intel_de_write_fw(i915, GMBUS1(i915), GMBUS_SW_CLR_INT);
> - intel_de_write_fw(i915, GMBUS1(i915), 0);
> - intel_de_write_fw(i915, GMBUS0(i915), 0);
> + intel_de_write_fw(display, GMBUS1(display), GMBUS_SW_CLR_INT);
> + intel_de_write_fw(display, GMBUS1(display), 0);
> + intel_de_write_fw(display, GMBUS0(display), 0);
>
> - drm_dbg_kms(&i915->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
> + drm_dbg_kms(display->drm, "GMBUS [%s] NAK for addr: %04x %c(%d)\n",
> adapter->name, msgs[i].addr,
> (msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
>
> @@ -718,7 +727,7 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> * drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
> */
> if (ret == -ENXIO && i == 0 && try++ == 0) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "GMBUS [%s] NAK on first message, retry\n",
> adapter->name);
> goto retry;
> @@ -727,10 +736,10 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> goto out;
>
> timeout:
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
> bus->adapter.name, bus->reg0 & 0xff);
> - intel_de_write_fw(i915, GMBUS0(i915), 0);
> + intel_de_write_fw(display, GMBUS0(display), 0);
>
> /*
> * Hardware may not support GMBUS over these pins? Try GPIO bitbanging
> @@ -741,9 +750,9 @@ do_gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num,
> out:
> /* Display WA #0868: skl,bxt,kbl,cfl,glk */
> if (IS_GEMINILAKE(i915) || IS_BROXTON(i915))
> - bxt_gmbus_clock_gating(i915, true);
> + bxt_gmbus_clock_gating(display, true);
> else if (HAS_PCH_SPT(i915) || HAS_PCH_CNP(i915))
> - pch_gmbus_clock_gating(i915, true);
> + pch_gmbus_clock_gating(display, true);
>
> return ret;
> }
> @@ -752,7 +761,8 @@ static int
> gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> intel_wakeref_t wakeref;
> int ret;
>
> @@ -776,7 +786,8 @@ gmbus_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, int num)
> int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
> + struct drm_i915_private *i915 = to_i915(display->drm);
> u8 cmd = DRM_HDCP_DDC_AKSV;
> u8 buf[DRM_HDCP_KSV_LEN] = {};
> struct i2c_msg msgs[] = {
> @@ -797,7 +808,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
> int ret;
>
> wakeref = intel_display_power_get(i915, POWER_DOMAIN_GMBUS);
> - mutex_lock(&i915->display.gmbus.mutex);
> + mutex_lock(&display->gmbus.mutex);
>
> /*
> * In order to output Aksv to the receiver, use an indexed write to
> @@ -806,7 +817,7 @@ int intel_gmbus_output_aksv(struct i2c_adapter *adapter)
> */
> ret = do_gmbus_xfer(adapter, msgs, ARRAY_SIZE(msgs), GMBUS_AKSV_SELECT);
>
> - mutex_unlock(&i915->display.gmbus.mutex);
> + mutex_unlock(&display->gmbus.mutex);
> intel_display_power_put(i915, POWER_DOMAIN_GMBUS, wakeref);
>
> return ret;
> @@ -830,27 +841,27 @@ static void gmbus_lock_bus(struct i2c_adapter *adapter,
> unsigned int flags)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
>
> - mutex_lock(&i915->display.gmbus.mutex);
> + mutex_lock(&display->gmbus.mutex);
> }
>
> static int gmbus_trylock_bus(struct i2c_adapter *adapter,
> unsigned int flags)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
>
> - return mutex_trylock(&i915->display.gmbus.mutex);
> + return mutex_trylock(&display->gmbus.mutex);
> }
>
> static void gmbus_unlock_bus(struct i2c_adapter *adapter,
> unsigned int flags)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
>
> - mutex_unlock(&i915->display.gmbus.mutex);
> + mutex_unlock(&display->gmbus.mutex);
> }
>
> static const struct i2c_lock_operations gmbus_lock_ops = {
> @@ -861,31 +872,32 @@ static const struct i2c_lock_operations gmbus_lock_ops = {
>
> /**
> * intel_gmbus_setup - instantiate all Intel i2c GMBuses
> - * @i915: i915 device private
> + * @display: display device
> */
> -int intel_gmbus_setup(struct drm_i915_private *i915)
> +int intel_gmbus_setup(struct intel_display *display)
> {
> - struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
> + struct drm_i915_private *i915 = to_i915(display->drm);
> + struct pci_dev *pdev = to_pci_dev(display->drm->dev);
> unsigned int pin;
> int ret;
>
> if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
> - i915->display.gmbus.mmio_base = VLV_DISPLAY_BASE;
> - else if (!HAS_GMCH(i915))
> + display->gmbus.mmio_base = VLV_DISPLAY_BASE;
> + else if (!HAS_GMCH(display))
> /*
> * Broxton uses the same PCH offsets for South Display Engine,
> * even though it doesn't have a PCH.
> */
> - i915->display.gmbus.mmio_base = PCH_DISPLAY_BASE;
> + display->gmbus.mmio_base = PCH_DISPLAY_BASE;
>
> - mutex_init(&i915->display.gmbus.mutex);
> - init_waitqueue_head(&i915->display.gmbus.wait_queue);
> + mutex_init(&display->gmbus.mutex);
> + init_waitqueue_head(&display->gmbus.wait_queue);
>
> - for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
> + for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
> const struct gmbus_pin *gmbus_pin;
> struct intel_gmbus *bus;
>
> - gmbus_pin = get_gmbus_pin(i915, pin);
> + gmbus_pin = get_gmbus_pin(display, pin);
> if (!gmbus_pin)
> continue;
>
> @@ -901,7 +913,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
> "i915 gmbus %s", gmbus_pin->name);
>
> bus->adapter.dev.parent = &pdev->dev;
> - bus->i915 = i915;
> + bus->display = display;
>
> bus->adapter.algo = &gmbus_algorithm;
> bus->adapter.lock_ops = &gmbus_lock_ops;
> @@ -919,7 +931,7 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
> if (IS_I830(i915))
> bus->force_bit = 1;
>
> - intel_gpio_setup(bus, GPIO(i915, gmbus_pin->gpio));
> + intel_gpio_setup(bus, GPIO(display, gmbus_pin->gpio));
>
> ret = i2c_add_adapter(&bus->adapter);
> if (ret) {
> @@ -927,43 +939,43 @@ int intel_gmbus_setup(struct drm_i915_private *i915)
> goto err;
> }
>
> - i915->display.gmbus.bus[pin] = bus;
> + display->gmbus.bus[pin] = bus;
> }
>
> - intel_gmbus_reset(i915);
> + intel_gmbus_reset(display);
>
> return 0;
>
> err:
> - intel_gmbus_teardown(i915);
> + intel_gmbus_teardown(display);
>
> return ret;
> }
>
> -struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *i915,
> +struct i2c_adapter *intel_gmbus_get_adapter(struct intel_display *display,
> unsigned int pin)
> {
> - if (drm_WARN_ON(&i915->drm, pin >= ARRAY_SIZE(i915->display.gmbus.bus) ||
> - !i915->display.gmbus.bus[pin]))
> + if (drm_WARN_ON(display->drm, pin >= ARRAY_SIZE(display->gmbus.bus) ||
> + !display->gmbus.bus[pin]))
> return NULL;
>
> - return &i915->display.gmbus.bus[pin]->adapter;
> + return &display->gmbus.bus[pin]->adapter;
> }
>
> void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
> {
> struct intel_gmbus *bus = to_intel_gmbus(adapter);
> - struct drm_i915_private *i915 = bus->i915;
> + struct intel_display *display = bus->display;
>
> - mutex_lock(&i915->display.gmbus.mutex);
> + mutex_lock(&display->gmbus.mutex);
>
> bus->force_bit += force_bit ? 1 : -1;
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "%sabling bit-banging on %s. force bit now %d\n",
> force_bit ? "en" : "dis", adapter->name,
> bus->force_bit);
>
> - mutex_unlock(&i915->display.gmbus.mutex);
> + mutex_unlock(&display->gmbus.mutex);
> }
>
> bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
> @@ -973,25 +985,25 @@ bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter)
> return bus->force_bit;
> }
>
> -void intel_gmbus_teardown(struct drm_i915_private *i915)
> +void intel_gmbus_teardown(struct intel_display *display)
> {
> unsigned int pin;
>
> - for (pin = 0; pin < ARRAY_SIZE(i915->display.gmbus.bus); pin++) {
> + for (pin = 0; pin < ARRAY_SIZE(display->gmbus.bus); pin++) {
> struct intel_gmbus *bus;
>
> - bus = i915->display.gmbus.bus[pin];
> + bus = display->gmbus.bus[pin];
> if (!bus)
> continue;
>
> i2c_del_adapter(&bus->adapter);
>
> kfree(bus);
> - i915->display.gmbus.bus[pin] = NULL;
> + display->gmbus.bus[pin] = NULL;
> }
> }
>
> -void intel_gmbus_irq_handler(struct drm_i915_private *i915)
> +void intel_gmbus_irq_handler(struct intel_display *display)
> {
> - wake_up_all(&i915->display.gmbus.wait_queue);
> + wake_up_all(&display->gmbus.wait_queue);
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus.h b/drivers/gpu/drm/i915/display/intel_gmbus.h
> index 8111eb23e2af..35a200a9efc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus.h
> @@ -8,8 +8,8 @@
>
> #include <linux/types.h>
>
> -struct drm_i915_private;
> struct i2c_adapter;
> +struct intel_display;
>
> #define GMBUS_PIN_DISABLED 0
> #define GMBUS_PIN_SSC 1
> @@ -34,18 +34,17 @@ struct i2c_adapter;
>
> #define GMBUS_NUM_PINS 15 /* including 0 */
>
> -int intel_gmbus_setup(struct drm_i915_private *dev_priv);
> -void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
> -bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> - unsigned int pin);
> +int intel_gmbus_setup(struct intel_display *display);
> +void intel_gmbus_teardown(struct intel_display *display);
> +bool intel_gmbus_is_valid_pin(struct intel_display *display, unsigned int pin);
> int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
>
> struct i2c_adapter *
> -intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
> +intel_gmbus_get_adapter(struct intel_display *display, unsigned int pin);
> void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
> bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
> -void intel_gmbus_reset(struct drm_i915_private *dev_priv);
> +void intel_gmbus_reset(struct intel_display *display);
>
> -void intel_gmbus_irq_handler(struct drm_i915_private *i915);
> +void intel_gmbus_irq_handler(struct intel_display *display);
>
> #endif /* __INTEL_GMBUS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
> index 53aacbda983c..59bad1dda6d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
> +++ b/drivers/gpu/drm/i915/display/intel_gmbus_regs.h
> @@ -8,9 +8,9 @@
>
> #include "i915_reg_defs.h"
>
> -#define GMBUS_MMIO_BASE(__i915) ((__i915)->display.gmbus.mmio_base)
> +#define __GMBUS_MMIO_BASE(__display) ((__display)->gmbus.mmio_base)
>
> -#define GPIO(__i915, gpio) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5010 + 4 * (gpio))
> +#define GPIO(__display, gpio) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5010 + 4 * (gpio))
> #define GPIO_CLOCK_DIR_MASK (1 << 0)
> #define GPIO_CLOCK_DIR_IN (0 << 1)
> #define GPIO_CLOCK_DIR_OUT (1 << 1)
> @@ -27,7 +27,7 @@
> #define GPIO_DATA_PULLUP_DISABLE (1 << 13)
>
> /* clock/port select */
> -#define GMBUS0(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5100)
> +#define GMBUS0(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5100)
> #define GMBUS_AKSV_SELECT (1 << 11)
> #define GMBUS_RATE_100KHZ (0 << 8)
> #define GMBUS_RATE_50KHZ (1 << 8)
> @@ -37,7 +37,7 @@
> #define GMBUS_BYTE_CNT_OVERRIDE (1 << 6)
>
> /* command/status */
> -#define GMBUS1(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5104)
> +#define GMBUS1(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5104)
> #define GMBUS_SW_CLR_INT (1 << 31)
> #define GMBUS_SW_RDY (1 << 30)
> #define GMBUS_ENT (1 << 29) /* enable timeout */
> @@ -54,7 +54,7 @@
> #define GMBUS_SLAVE_WRITE (0 << 0)
>
> /* status */
> -#define GMBUS2(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5108)
> +#define GMBUS2(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5108)
> #define GMBUS_INUSE (1 << 15)
> #define GMBUS_HW_WAIT_PHASE (1 << 14)
> #define GMBUS_STALL_TIMEOUT (1 << 13)
> @@ -64,10 +64,10 @@
> #define GMBUS_ACTIVE (1 << 9)
>
> /* data buffer bytes 3-0 */
> -#define GMBUS3(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x510c)
> +#define GMBUS3(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x510c)
>
> /* interrupt mask (Pineview+) */
> -#define GMBUS4(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5110)
> +#define GMBUS4(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5110)
> #define GMBUS_SLAVE_TIMEOUT_EN (1 << 4)
> #define GMBUS_NAK_EN (1 << 3)
> #define GMBUS_IDLE_EN (1 << 2)
> @@ -75,7 +75,7 @@
> #define GMBUS_HW_RDY_EN (1 << 0)
>
> /* byte index */
> -#define GMBUS5(__i915) _MMIO(GMBUS_MMIO_BASE(__i915) + 0x5120)
> +#define GMBUS5(__display) _MMIO(__GMBUS_MMIO_BASE(__display) + 0x5120)
> #define GMBUS_2BYTE_INDEX_EN (1 << 31)
>
> #endif /* __INTEL_GMBUS_REGS_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 72ac910bf6ec..022ba3635101 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -2917,7 +2917,6 @@ static struct intel_encoder *
> get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
> {
> struct intel_display *display = to_intel_display(encoder);
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_encoder *other;
>
> for_each_intel_encoder(display->drm, other) {
> @@ -2931,7 +2930,7 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
>
> connector = enc_to_dig_port(other)->hdmi.attached_connector;
>
> - if (connector && connector->base.ddc == intel_gmbus_get_adapter(i915, ddc_pin))
> + if (connector && connector->base.ddc == intel_gmbus_get_adapter(display, ddc_pin))
> return other;
> }
>
> @@ -2941,7 +2940,6 @@ get_encoder_by_ddc_pin(struct intel_encoder *encoder, u8 ddc_pin)
> static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> {
> struct intel_display *display = to_intel_display(encoder);
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_encoder *other;
> const char *source;
> u8 ddc_pin;
> @@ -2954,7 +2952,7 @@ static u8 intel_hdmi_ddc_pin(struct intel_encoder *encoder)
> source = "platform default";
> }
>
> - if (!intel_gmbus_is_valid_pin(i915, ddc_pin)) {
> + if (!intel_gmbus_is_valid_pin(display, ddc_pin)) {
> drm_dbg_kms(display->drm,
> "[ENCODER:%d:%s] Invalid DDC pin %d\n",
> encoder->base.base.id, encoder->base.name, ddc_pin);
> @@ -3052,7 +3050,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> drm_connector_init_with_ddc(dev, connector,
> &intel_hdmi_connector_funcs,
> DRM_MODE_CONNECTOR_HDMIA,
> - intel_gmbus_get_adapter(dev_priv, ddc_pin));
> + intel_gmbus_get_adapter(display, ddc_pin));
>
> drm_connector_helper_add(connector, &intel_hdmi_connector_helper_funcs);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> index 5d055dc9366f..cb64c6f0ad1b 100644
> --- a/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> +++ b/drivers/gpu/drm/i915/display/intel_hotplug_irq.c
> @@ -556,6 +556,7 @@ void xelpdp_pica_irq_handler(struct drm_i915_private *i915, u32 iir)
>
> void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_HOTPLUG_MASK_ICP;
> u32 tc_hotplug_trigger = pch_iir & SDE_TC_HOTPLUG_MASK_ICP;
> u32 pin_mask = 0, long_mask = 0;
> @@ -589,11 +590,12 @@ void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>
> if (pch_iir & SDE_GMBUS_ICP)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
> }
>
> void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> {
> + struct intel_display *display = &dev_priv->display;
> u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
> ~SDE_PORTE_HOTPLUG_SPT;
> u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
> @@ -625,7 +627,7 @@ void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
> intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
>
> if (pch_iir & SDE_GMBUS_CPT)
> - intel_gmbus_irq_handler(dev_priv);
> + intel_gmbus_irq_handler(display);
> }
>
> void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 hotplug_trigger)
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 5f753ee743c6..96fa238b461d 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -900,7 +900,7 @@ void intel_lvds_init(struct drm_i915_private *i915)
> drm_connector_init_with_ddc(&i915->drm, &connector->base,
> &intel_lvds_connector_funcs,
> DRM_MODE_CONNECTOR_LVDS,
> - intel_gmbus_get_adapter(i915, ddc_pin));
> + intel_gmbus_get_adapter(display, ddc_pin));
>
> drm_encoder_init(&i915->drm, &encoder->base, &intel_lvds_enc_funcs,
> DRM_MODE_ENCODER_LVDS, "LVDS");
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index b83bf813677d..7a28104f68ad 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -2082,10 +2082,10 @@ intel_sdvo_get_edid(struct drm_connector *connector)
> static const struct drm_edid *
> intel_sdvo_get_analog_edid(struct drm_connector *connector)
> {
> - struct drm_i915_private *i915 = to_i915(connector->dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> struct i2c_adapter *ddc;
>
> - ddc = intel_gmbus_get_adapter(i915, i915->display.vbt.crt_ddc_pin);
> + ddc = intel_gmbus_get_adapter(display, display->vbt.crt_ddc_pin);
> if (!ddc)
> return NULL;
>
> @@ -2638,6 +2638,7 @@ intel_sdvo_select_ddc_bus(struct intel_sdvo *sdvo,
> static void
> intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
> {
> + struct intel_display *display = to_intel_display(&sdvo->base);
> struct drm_i915_private *dev_priv = to_i915(sdvo->base.base.dev);
> const struct sdvo_device_mapping *mapping;
> u8 pin;
> @@ -2648,7 +2649,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
> mapping = &dev_priv->display.vbt.sdvo_mappings[1];
>
> if (mapping->initialized &&
> - intel_gmbus_is_valid_pin(dev_priv, mapping->i2c_pin))
> + intel_gmbus_is_valid_pin(display, mapping->i2c_pin))
> pin = mapping->i2c_pin;
> else
> pin = GMBUS_PIN_DPB;
> @@ -2657,7 +2658,7 @@ intel_sdvo_select_i2c_bus(struct intel_sdvo *sdvo)
> sdvo->base.base.base.id, sdvo->base.base.name,
> pin, sdvo->target_addr);
>
> - sdvo->i2c = intel_gmbus_get_adapter(dev_priv, pin);
> + sdvo->i2c = intel_gmbus_get_adapter(display, pin);
>
> /*
> * With gmbus we should be able to drive sdvo i2c at 2MHz, but somehow
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 9d3d9b983032..f18f1acf2158 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -137,5 +137,5 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
>
> intel_vga_redisable(display);
>
> - intel_gmbus_reset(dev_priv);
> + intel_gmbus_reset(display);
> }
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 02/11] drm/i915/cx0: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
2024-10-22 15:57 ` [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 14:53 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 03/11] drm/i915/dpio: " Jani Nikula
` (16 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch Cx0 PHY code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_cx0_phy.c | 308 ++++++++++---------
drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
drivers/gpu/drm/i915/display/intel_display.c | 6 +-
3 files changed, 174 insertions(+), 148 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
index f73d576fd99e..814bb17c9379 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
@@ -65,22 +65,23 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
}
static void
-assert_dc_off(struct drm_i915_private *i915)
+assert_dc_off(struct intel_display *display)
{
+ struct drm_i915_private *i915 = to_i915(display->drm);
bool enabled;
enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
- drm_WARN_ON(&i915->drm, !enabled);
+ drm_WARN_ON(display->drm, !enabled);
}
static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
int lane;
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
- intel_de_rmw(i915,
- XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
XELPDP_PORT_MSGBUS_TIMER_VAL);
}
@@ -119,25 +120,29 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
int lane)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
+ intel_de_rmw(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
}
static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_RESET,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
+ drm_err_once(display->drm,
+ "Failed to bring PHY %c to idle.\n",
+ phy_name(phy));
return;
}
@@ -147,22 +152,23 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
int command, int lane, u32 *val)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- if (intel_de_wait_custom(i915,
- XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
+ if (intel_de_wait_custom(display,
+ XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_PORT_P2M_RESPONSE_READY,
XELPDP_MSGBUS_TIMEOUT_FAST_US,
XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
- drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
phy_name(phy), *val);
- if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) &
+ if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Hardware did not detect a timeout\n",
phy_name(phy));
@@ -171,14 +177,18 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
}
if (*val & XELPDP_PORT_P2M_ERROR_SET) {
- drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Error occurred during %s command. Status: 0x%x\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
}
if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
- drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
+ drm_dbg_kms(display->drm,
+ "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n",
+ phy_name(phy),
command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -190,22 +200,22 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
static int __intel_cx0_read_once(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
XELPDP_PORT_M2P_COMMAND_READ |
XELPDP_PORT_M2P_ADDRESS(addr));
@@ -229,11 +239,11 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
static u8 __intel_cx0_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to read successfully */
for (i = 0; i < 3; i++) {
@@ -243,7 +253,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
return status;
}
- drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
+ drm_err_once(display->drm,
+ "PHY %c Read %04x failed after %d retries.\n",
phy_name(phy), addr, i);
return 0;
@@ -260,32 +271,32 @@ static u8 intel_cx0_read(struct intel_encoder *encoder,
static int __intel_cx0_write_once(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
int ack;
u32 val;
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
}
- intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING |
(committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
XELPDP_PORT_M2P_DATA(data) |
XELPDP_PORT_M2P_ADDRESS(addr));
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -ETIMEDOUT;
@@ -295,9 +306,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
if (ack < 0)
return ack;
- } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
+ } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
XELPDP_PORT_P2M_ERROR_SET)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Error occurred during write command.\n", phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
return -EINVAL;
@@ -318,11 +329,11 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
static void __intel_cx0_write(struct intel_encoder *encoder,
int lane, u16 addr, u8 data, bool committed)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
int i, status;
- assert_dc_off(i915);
+ assert_dc_off(display);
/* 3 tries is assumed to be enough to write successfully */
for (i = 0; i < 3; i++) {
@@ -332,7 +343,7 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
return;
}
- drm_err_once(&i915->drm,
+ drm_err_once(display->drm,
"PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
}
@@ -348,9 +359,9 @@ static void intel_cx0_write(struct intel_encoder *encoder,
static void intel_c20_sram_write(struct intel_encoder *encoder,
int lane, u16 addr, u16 data)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
@@ -362,10 +373,10 @@ static void intel_c20_sram_write(struct intel_encoder *encoder,
static u16 intel_c20_sram_read(struct intel_encoder *encoder,
int lane, u16 addr)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u16 val;
- assert_dc_off(i915);
+ assert_dc_off(display);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
@@ -429,7 +440,7 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
const struct intel_ddi_buf_trans *trans;
u8 owned_lane_mask;
intel_wakeref_t wakeref;
@@ -444,7 +455,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
wakeref = intel_cx0_phy_transaction_begin(encoder);
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
+ if (drm_WARN_ON_ONCE(display->drm, !trans)) {
intel_cx0_phy_transaction_end(encoder, wakeref);
return;
}
@@ -2003,6 +2014,7 @@ intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
int i;
@@ -2019,7 +2031,7 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
if (pll_state->ssc_enabled)
return;
- drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
+ drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
for (i = 4; i < 9; i++)
pll_state->c10.pll[i] = 0;
}
@@ -2073,7 +2085,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c10_pll_program(struct drm_i915_private *i915,
+static void intel_c10_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2106,7 +2118,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
MB_WRITE_COMMITTED);
}
-static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c10pll_dump_hw_state(struct intel_display *display,
const struct intel_c10pll_state *hw_state)
{
bool fracen;
@@ -2115,29 +2127,31 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
unsigned int multiplier, tx_clk_div;
fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
- drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ",
+ drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
str_yes_no(fracen));
if (fracen) {
frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
- drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n",
+ drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
frac_quot, frac_rem, frac_den);
}
multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
hw_state->pll[2]) / 2 + 16;
tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
- drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:");
- drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
+ drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
+ drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
+ hw_state->cmn);
BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
- drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
+ drm_dbg_kms(display->drm,
+ "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
}
@@ -2239,13 +2253,13 @@ static const struct intel_c20pll_state * const *
intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
if (intel_crtc_has_dp_encoder(crtc_state)) {
if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
return xe2hpd_c20_edp_tables;
- if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
+ if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
return xe2hpd_c20_dp_tables;
else
return mtl_c20_dp_tables;
@@ -2412,33 +2426,37 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
intel_cx0_phy_transaction_end(encoder, wakeref);
}
-static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
+static void intel_c20pll_dump_hw_state(struct intel_display *display,
const struct intel_c20pll_state *hw_state)
{
int i;
- drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
- drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
+ drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
+ drm_dbg_kms(display->drm,
+ "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
- drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
+ drm_dbg_kms(display->drm,
+ "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
if (intel_c20phy_use_mpllb(hw_state)) {
for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
- drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
+ drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
+ hw_state->mpllb[i]);
} else {
for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
- drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
+ drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
+ hw_state->mplla[i]);
}
}
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state)
{
if (hw_state->use_c10)
- intel_c10pll_dump_hw_state(i915, &hw_state->c10);
+ intel_c10pll_dump_hw_state(display, &hw_state->c10);
else
- intel_c20pll_dump_hw_state(i915, &hw_state->c20);
+ intel_c20pll_dump_hw_state(display, &hw_state->c20);
}
static u8 intel_c20_get_dp_rate(u32 clock)
@@ -2538,7 +2556,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
return 0;
}
-static void intel_c20_pll_program(struct drm_i915_private *i915,
+static void intel_c20_pll_program(struct intel_display *display,
const struct intel_crtc_state *crtc_state,
struct intel_encoder *encoder)
{
@@ -2571,11 +2589,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_TX_CNTX_CFG(i915, i),
+ PHY_C20_A_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_TX_CNTX_CFG(i915, i),
+ PHY_C20_B_TX_CNTX_CFG(display, i),
pll_state->tx[i]);
}
@@ -2583,11 +2601,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_CMN_CNTX_CFG(i915, i),
+ PHY_C20_A_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_CMN_CNTX_CFG(i915, i),
+ PHY_C20_B_CMN_CNTX_CFG(display, i),
pll_state->cmn[i]);
}
@@ -2596,22 +2614,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLB_CNTX_CFG(display, i),
pll_state->mpllb[i]);
}
} else {
for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
if (cntx)
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_A_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
else
intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
- PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
+ PHY_C20_B_MPLLA_CNTX_CFG(display, i),
pll_state->mplla[i]);
}
}
@@ -2678,10 +2696,10 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
u32 val = 0;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
XELPDP_PORT_REVERSAL,
lane_reversal ? XELPDP_PORT_REVERSAL : 0);
@@ -2703,7 +2721,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
else
val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
XELPDP_SSC_ENABLE_PLLB, val);
@@ -2734,48 +2752,49 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
u8 lane_mask, u8 state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
- i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
+ i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
int lane;
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
intel_cx0_get_powerdown_state(lane_mask, state));
/* Wait for pending transactions.*/
for_each_cx0_lane_in_mask(lane_mask, lane)
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
XELPDP_PORT_M2P_TRANSACTION_PENDING,
XELPDP_MSGBUS_TIMEOUT_SLOW)) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
phy_name(phy));
intel_cx0_bus_reset(encoder, lane);
}
- intel_de_rmw(i915, buf_ctl2_reg,
+ intel_de_rmw(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
intel_cx0_get_powerdown_update(lane_mask));
/* Update Timeout Value */
- if (intel_de_wait_custom(i915, buf_ctl2_reg,
+ if (intel_de_wait_custom(display, buf_ctl2_reg,
intel_cx0_get_powerdown_update(lane_mask), 0,
XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
}
static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
XELPDP_POWER_STATE_READY_MASK,
XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
XELPDP_POWER_STATE_ACTIVE_MASK |
XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
@@ -2807,7 +2826,7 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
bool lane_reversal)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum phy phy = intel_encoder_to_phy(encoder);
u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
@@ -2820,48 +2839,51 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
XELPDP_LANE_PHY_CURRENT_STATUS(1))
: XELPDP_LANE_PHY_CURRENT_STATUS(0);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_PHY_READY,
XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of SOC reset after %dus.\n",
phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
lane_pipe_reset);
- if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status, lane_phy_current_status,
XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dus.\n",
phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_request(owned_lane_mask),
intel_cx0_get_pclk_refclk_request(lane_mask));
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
intel_cx0_get_pclk_refclk_ack(lane_mask),
XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to request refclk after %dus.\n",
phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
CX0_P2_STATE_RESET);
intel_cx0_setup_powerdown(encoder);
- intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
+ intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
- if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
lane_phy_current_status,
XELPDP_PORT_RESET_END_TIMEOUT))
- drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
+ drm_warn(display->drm,
+ "PHY %c failed to bring out of Lane reset after %dms.\n",
phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
}
-static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
- struct intel_encoder *encoder, int lane_count,
+static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
bool lane_reversal)
{
int i;
@@ -2930,7 +2952,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
static void intel_cx0pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
@@ -2962,15 +2984,15 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
/* 5. Program PHY internal PLL internal registers. */
if (intel_encoder_is_c10phy(encoder))
- intel_c10_pll_program(i915, crtc_state, encoder);
+ intel_c10_pll_program(display, crtc_state, encoder);
else
- intel_c20_pll_program(i915, crtc_state, encoder);
+ intel_c20_pll_program(display, crtc_state, encoder);
/*
* 6. Program the enabled and disabled owned PHY lane
* transmitters over message bus
*/
- intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
+ intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal);
/*
* 7. Follow the Display Voltage Frequency Switching - Sequence
@@ -2981,23 +3003,23 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
* 8. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
/*
* 9. Set PORT_CLOCK_CTL register PCLK PLL Request
* LN<Lane for maxPCLK> to "1" to enable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_request(maxpclk_lane));
/* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
intel_cx0_get_pclk_pll_ack(maxpclk_lane),
XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
+ drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
/*
@@ -3011,15 +3033,16 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- u32 clock;
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ struct intel_display *display = to_intel_display(encoder);
+ u32 clock, val;
+
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
- drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
- drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
+ drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
+ drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
switch (clock) {
case XELPDP_DDI_CLOCK_SELECT_TBT_162:
@@ -3036,7 +3059,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
}
}
-static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
+static int intel_mtl_tbt_clock_select(int clock)
{
switch (clock) {
case 162000:
@@ -3056,7 +3079,7 @@ static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
u32 val = 0;
@@ -3064,13 +3087,13 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 1. Program PORT_CLOCK_CTL REGISTER to configure
* clock muxes, gating and SSC
*/
- val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
+ val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));
val |= XELPDP_FORWARD_CLOCK_UNGATE;
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
/* 2. Read back PORT_CLOCK_CTL REGISTER */
- val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
/*
* 3. Follow the Display Voltage Frequency Switching - Sequence
@@ -3081,14 +3104,15 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
*/
val |= XELPDP_TBT_CLOCK_REQUEST;
- intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
+ intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
/* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK,
XELPDP_TBT_CLOCK_ACK,
100, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3100,7 +3124,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
* 7. Program DDI_CLK_VALFREQ to match intended DDI
* clock frequency.
*/
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
crtc_state->port_clock);
}
@@ -3130,7 +3154,7 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
static void intel_cx0pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
@@ -3147,21 +3171,22 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
* 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
* to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
/* 4. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
/*
* 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
*/
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
- drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
+ drm_warn(display->drm,
+ "Port %c PLL not unlocked after %dus.\n",
phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
/*
@@ -3170,9 +3195,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
*/
/* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK, 0);
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_FORWARD_CLOCK_UNGATE, 0);
intel_cx0_phy_transaction_end(encoder, wakeref);
@@ -3180,7 +3205,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum phy phy = intel_encoder_to_phy(encoder);
/*
@@ -3191,13 +3216,14 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_REQUEST, 0);
/* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
- if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
- drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
+ drm_warn(display->drm,
+ "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
encoder->base.base.id, encoder->base.name, phy_name(phy));
/*
@@ -3208,12 +3234,12 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
/*
* 5. Program PORT CLOCK CTRL register to disable and gate clocks
*/
- intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
+ intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
XELPDP_DDI_CLOCK_SELECT_MASK |
XELPDP_FORWARD_CLOCK_UNGATE, 0);
/* 6. Program DDI_CLK_VALFREQ to 0. */
- intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
+ intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
}
void intel_mtl_pll_disable(struct intel_encoder *encoder)
@@ -3230,13 +3256,15 @@ enum icl_port_dpll_id
intel_mtl_port_pll_type(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
+ u32 val, clock;
+
/*
* TODO: Determine the PLL type from the SW state, once MTL PLL
* handling is done via the standard shared DPLL framework.
*/
- u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
- u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
+ val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
+ clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
@@ -3408,13 +3436,13 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc)
{
- struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_display *display = to_intel_display(state);
const struct intel_crtc_state *new_crtc_state =
intel_atomic_get_new_crtc_state(state, crtc);
struct intel_encoder *encoder;
struct intel_cx0pll_state mpll_hw_state = {};
- if (DISPLAY_VER(i915) < 14)
+ if (DISPLAY_VER(display) < 14)
return;
if (!new_crtc_state->hw.active)
diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
index 9004b99bb51f..711168882684 100644
--- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
@@ -7,17 +7,15 @@
#define __INTEL_CX0_PHY_H__
#include <linux/types.h>
-#include <linux/bitfield.h>
-#include <linux/bits.h>
enum icl_port_dpll_id;
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_c10pll_state;
struct intel_c20pll_state;
-struct intel_cx0pll_state;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_cx0pll_state;
+struct intel_display;
struct intel_encoder;
struct intel_hdmi;
@@ -35,7 +33,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
const struct intel_cx0pll_state *pll_state);
-void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
+void intel_cx0pll_dump_hw_state(struct intel_display *display,
const struct intel_cx0pll_state *hw_state);
void intel_cx0pll_state_verify(struct intel_atomic_state *state,
struct intel_crtc *crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index ef1436146325..c19f01b63936 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5305,15 +5305,15 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
const struct intel_cx0pll_state *a,
const struct intel_cx0pll_state *b)
{
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
char *chipname = a->use_c10 ? "C10" : "C20";
pipe_config_mismatch(p, fastset, crtc, name, chipname);
drm_printf(p, "expected:\n");
- intel_cx0pll_dump_hw_state(i915, a);
+ intel_cx0pll_dump_hw_state(display, a);
drm_printf(p, "found:\n");
- intel_cx0pll_dump_hw_state(i915, b);
+ intel_cx0pll_dump_hw_state(display, b);
}
bool
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 02/11] drm/i915/cx0: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 02/11] drm/i915/cx0: " Jani Nikula
@ 2024-10-23 14:53 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 14:53 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:19PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch Cx0 PHY code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_cx0_phy.c | 308 ++++++++++---------
> drivers/gpu/drm/i915/display/intel_cx0_phy.h | 8 +-
> drivers/gpu/drm/i915/display/intel_display.c | 6 +-
> 3 files changed, 174 insertions(+), 148 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.c b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> index f73d576fd99e..814bb17c9379 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.c
> @@ -65,22 +65,23 @@ static u8 intel_cx0_get_owned_lane_mask(struct intel_encoder *encoder)
> }
>
> static void
> -assert_dc_off(struct drm_i915_private *i915)
> +assert_dc_off(struct intel_display *display)
> {
> + struct drm_i915_private *i915 = to_i915(display->drm);
> bool enabled;
>
> enabled = intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF);
> - drm_WARN_ON(&i915->drm, !enabled);
> + drm_WARN_ON(display->drm, !enabled);
> }
>
> static void intel_cx0_program_msgbus_timer(struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(encoder);
> int lane;
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> for_each_cx0_lane_in_mask(INTEL_CX0_BOTH_LANES, lane)
> - intel_de_rmw(i915,
> - XELPDP_PORT_MSGBUS_TIMER(i915, encoder->port, lane),
> + intel_de_rmw(display,
> + XELPDP_PORT_MSGBUS_TIMER(display, encoder->port, lane),
> XELPDP_PORT_MSGBUS_TIMER_VAL_MASK,
> XELPDP_PORT_MSGBUS_TIMER_VAL);
> }
> @@ -119,25 +120,29 @@ static void intel_cx0_phy_transaction_end(struct intel_encoder *encoder, intel_w
> static void intel_clear_response_ready_flag(struct intel_encoder *encoder,
> int lane)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> - intel_de_rmw(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
> + intel_de_rmw(display,
> + XELPDP_PORT_P2M_MSGBUS_STATUS(i915, encoder->port, lane),
> 0, XELPDP_PORT_P2M_RESPONSE_READY | XELPDP_PORT_P2M_ERROR_SET);
> }
>
> static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET);
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_RESET,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> - drm_err_once(&i915->drm, "Failed to bring PHY %c to idle.\n", phy_name(phy));
> + drm_err_once(display->drm,
> + "Failed to bring PHY %c to idle.\n",
> + phy_name(phy));
> return;
> }
>
> @@ -147,22 +152,23 @@ static void intel_cx0_bus_reset(struct intel_encoder *encoder, int lane)
> static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> int command, int lane, u32 *val)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
>
> - if (intel_de_wait_custom(i915,
> - XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane),
> + if (intel_de_wait_custom(display,
> + XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane),
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_PORT_P2M_RESPONSE_READY,
> XELPDP_MSGBUS_TIMEOUT_FAST_US,
> XELPDP_MSGBUS_TIMEOUT_SLOW, val)) {
> - drm_dbg_kms(&i915->drm, "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
> + drm_dbg_kms(display->drm,
> + "PHY %c Timeout waiting for message ACK. Status: 0x%x\n",
> phy_name(phy), *val);
>
> - if (!(intel_de_read(i915, XELPDP_PORT_MSGBUS_TIMER(i915, port, lane)) &
> + if (!(intel_de_read(display, XELPDP_PORT_MSGBUS_TIMER(display, port, lane)) &
> XELPDP_PORT_MSGBUS_TIMER_TIMED_OUT))
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Hardware did not detect a timeout\n",
> phy_name(phy));
>
> @@ -171,14 +177,18 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> }
>
> if (*val & XELPDP_PORT_P2M_ERROR_SET) {
> - drm_dbg_kms(&i915->drm, "PHY %c Error occurred during %s command. Status: 0x%x\n", phy_name(phy),
> + drm_dbg_kms(display->drm,
> + "PHY %c Error occurred during %s command. Status: 0x%x\n",
> + phy_name(phy),
> command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
> intel_cx0_bus_reset(encoder, lane);
> return -EINVAL;
> }
>
> if (REG_FIELD_GET(XELPDP_PORT_P2M_COMMAND_TYPE_MASK, *val) != command) {
> - drm_dbg_kms(&i915->drm, "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n", phy_name(phy),
> + drm_dbg_kms(display->drm,
> + "PHY %c Not a %s response. MSGBUS Status: 0x%x.\n",
> + phy_name(phy),
> command == XELPDP_PORT_P2M_COMMAND_READ_ACK ? "read" : "write", *val);
> intel_cx0_bus_reset(encoder, lane);
> return -EINVAL;
> @@ -190,22 +200,22 @@ static int intel_cx0_wait_for_ack(struct intel_encoder *encoder,
> static int __intel_cx0_read_once(struct intel_encoder *encoder,
> int lane, u16 addr)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to complete. Reset the bus and retry.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> XELPDP_PORT_M2P_COMMAND_READ |
> XELPDP_PORT_M2P_ADDRESS(addr));
> @@ -229,11 +239,11 @@ static int __intel_cx0_read_once(struct intel_encoder *encoder,
> static u8 __intel_cx0_read(struct intel_encoder *encoder,
> int lane, u16 addr)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> int i, status;
>
> - assert_dc_off(i915);
> + assert_dc_off(display);
>
> /* 3 tries is assumed to be enough to read successfully */
> for (i = 0; i < 3; i++) {
> @@ -243,7 +253,8 @@ static u8 __intel_cx0_read(struct intel_encoder *encoder,
> return status;
> }
>
> - drm_err_once(&i915->drm, "PHY %c Read %04x failed after %d retries.\n",
> + drm_err_once(display->drm,
> + "PHY %c Read %04x failed after %d retries.\n",
> phy_name(phy), addr, i);
>
> return 0;
> @@ -260,32 +271,32 @@ static u8 intel_cx0_read(struct intel_encoder *encoder,
> static int __intel_cx0_write_once(struct intel_encoder *encoder,
> int lane, u16 addr, u8 data, bool committed)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
> int ack;
> u32 val;
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to complete. Resetting the bus.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> return -ETIMEDOUT;
> }
>
> - intel_de_write(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + intel_de_write(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING |
> (committed ? XELPDP_PORT_M2P_COMMAND_WRITE_COMMITTED :
> XELPDP_PORT_M2P_COMMAND_WRITE_UNCOMMITTED) |
> XELPDP_PORT_M2P_DATA(data) |
> XELPDP_PORT_M2P_ADDRESS(addr));
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for write to complete. Resetting the bus.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> return -ETIMEDOUT;
> @@ -295,9 +306,9 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
> ack = intel_cx0_wait_for_ack(encoder, XELPDP_PORT_P2M_COMMAND_WRITE_ACK, lane, &val);
> if (ack < 0)
> return ack;
> - } else if ((intel_de_read(i915, XELPDP_PORT_P2M_MSGBUS_STATUS(i915, port, lane)) &
> + } else if ((intel_de_read(display, XELPDP_PORT_P2M_MSGBUS_STATUS(display, port, lane)) &
> XELPDP_PORT_P2M_ERROR_SET)) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Error occurred during write command.\n", phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> return -EINVAL;
> @@ -318,11 +329,11 @@ static int __intel_cx0_write_once(struct intel_encoder *encoder,
> static void __intel_cx0_write(struct intel_encoder *encoder,
> int lane, u16 addr, u8 data, bool committed)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> int i, status;
>
> - assert_dc_off(i915);
> + assert_dc_off(display);
>
> /* 3 tries is assumed to be enough to write successfully */
> for (i = 0; i < 3; i++) {
> @@ -332,7 +343,7 @@ static void __intel_cx0_write(struct intel_encoder *encoder,
> return;
> }
>
> - drm_err_once(&i915->drm,
> + drm_err_once(display->drm,
> "PHY %c Write %04x failed after %d retries.\n", phy_name(phy), addr, i);
> }
>
> @@ -348,9 +359,9 @@ static void intel_cx0_write(struct intel_encoder *encoder,
> static void intel_c20_sram_write(struct intel_encoder *encoder,
> int lane, u16 addr, u16 data)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - assert_dc_off(i915);
> + assert_dc_off(display);
>
> intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_H, addr >> 8, 0);
> intel_cx0_write(encoder, lane, PHY_C20_WR_ADDRESS_L, addr & 0xff, 0);
> @@ -362,10 +373,10 @@ static void intel_c20_sram_write(struct intel_encoder *encoder,
> static u16 intel_c20_sram_read(struct intel_encoder *encoder,
> int lane, u16 addr)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> u16 val;
>
> - assert_dc_off(i915);
> + assert_dc_off(display);
>
> intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_H, addr >> 8, 0);
> intel_cx0_write(encoder, lane, PHY_C20_RD_ADDRESS_L, addr & 0xff, 1);
> @@ -429,7 +440,7 @@ static u8 intel_c10_get_tx_term_ctl(const struct intel_crtc_state *crtc_state)
> void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> const struct intel_ddi_buf_trans *trans;
> u8 owned_lane_mask;
> intel_wakeref_t wakeref;
> @@ -444,7 +455,7 @@ void intel_cx0_phy_set_signal_levels(struct intel_encoder *encoder,
> wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> - if (drm_WARN_ON_ONCE(&i915->drm, !trans)) {
> + if (drm_WARN_ON_ONCE(display->drm, !trans)) {
> intel_cx0_phy_transaction_end(encoder, wakeref);
> return;
> }
> @@ -2003,6 +2014,7 @@ intel_c10pll_tables_get(struct intel_crtc_state *crtc_state,
> static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> struct intel_cx0pll_state *pll_state = &crtc_state->dpll_hw_state.cx0pll;
> int i;
> @@ -2019,7 +2031,7 @@ static void intel_c10pll_update_pll(struct intel_crtc_state *crtc_state,
> if (pll_state->ssc_enabled)
> return;
>
> - drm_WARN_ON(&i915->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
> + drm_WARN_ON(display->drm, ARRAY_SIZE(pll_state->c10.pll) < 9);
> for (i = 4; i < 9; i++)
> pll_state->c10.pll[i] = 0;
> }
> @@ -2073,7 +2085,7 @@ static void intel_c10pll_readout_hw_state(struct intel_encoder *encoder,
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> -static void intel_c10_pll_program(struct drm_i915_private *i915,
> +static void intel_c10_pll_program(struct intel_display *display,
> const struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> @@ -2106,7 +2118,7 @@ static void intel_c10_pll_program(struct drm_i915_private *i915,
> MB_WRITE_COMMITTED);
> }
>
> -static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> +static void intel_c10pll_dump_hw_state(struct intel_display *display,
> const struct intel_c10pll_state *hw_state)
> {
> bool fracen;
> @@ -2115,29 +2127,31 @@ static void intel_c10pll_dump_hw_state(struct drm_i915_private *i915,
> unsigned int multiplier, tx_clk_div;
>
> fracen = hw_state->pll[0] & C10_PLL0_FRACEN;
> - drm_dbg_kms(&i915->drm, "c10pll_hw_state: fracen: %s, ",
> + drm_dbg_kms(display->drm, "c10pll_hw_state: fracen: %s, ",
> str_yes_no(fracen));
>
> if (fracen) {
> frac_quot = hw_state->pll[12] << 8 | hw_state->pll[11];
> frac_rem = hw_state->pll[14] << 8 | hw_state->pll[13];
> frac_den = hw_state->pll[10] << 8 | hw_state->pll[9];
> - drm_dbg_kms(&i915->drm, "quot: %u, rem: %u, den: %u,\n",
> + drm_dbg_kms(display->drm, "quot: %u, rem: %u, den: %u,\n",
> frac_quot, frac_rem, frac_den);
> }
>
> multiplier = (REG_FIELD_GET8(C10_PLL3_MULTIPLIERH_MASK, hw_state->pll[3]) << 8 |
> hw_state->pll[2]) / 2 + 16;
> tx_clk_div = REG_FIELD_GET8(C10_PLL15_TXCLKDIV_MASK, hw_state->pll[15]);
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "multiplier: %u, tx_clk_div: %u.\n", multiplier, tx_clk_div);
>
> - drm_dbg_kms(&i915->drm, "c10pll_rawhw_state:");
> - drm_dbg_kms(&i915->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx, hw_state->cmn);
> + drm_dbg_kms(display->drm, "c10pll_rawhw_state:");
> + drm_dbg_kms(display->drm, "tx: 0x%x, cmn: 0x%x\n", hw_state->tx,
> + hw_state->cmn);
>
> BUILD_BUG_ON(ARRAY_SIZE(hw_state->pll) % 4);
> for (i = 0; i < ARRAY_SIZE(hw_state->pll); i = i + 4)
> - drm_dbg_kms(&i915->drm, "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
> + drm_dbg_kms(display->drm,
> + "pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x, pll[%d] = 0x%x\n",
> i, hw_state->pll[i], i + 1, hw_state->pll[i + 1],
> i + 2, hw_state->pll[i + 2], i + 3, hw_state->pll[i + 3]);
> }
> @@ -2239,13 +2253,13 @@ static const struct intel_c20pll_state * const *
> intel_c20_pll_tables_get(struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
>
> if (intel_crtc_has_dp_encoder(crtc_state)) {
> if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
> return xe2hpd_c20_edp_tables;
>
> - if (DISPLAY_VER_FULL(i915) == IP_VER(14, 1))
> + if (DISPLAY_VER_FULL(display) == IP_VER(14, 1))
> return xe2hpd_c20_dp_tables;
> else
> return mtl_c20_dp_tables;
> @@ -2412,33 +2426,37 @@ static void intel_c20pll_readout_hw_state(struct intel_encoder *encoder,
> intel_cx0_phy_transaction_end(encoder, wakeref);
> }
>
> -static void intel_c20pll_dump_hw_state(struct drm_i915_private *i915,
> +static void intel_c20pll_dump_hw_state(struct intel_display *display,
> const struct intel_c20pll_state *hw_state)
> {
> int i;
>
> - drm_dbg_kms(&i915->drm, "c20pll_hw_state:\n");
> - drm_dbg_kms(&i915->drm, "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> + drm_dbg_kms(display->drm, "c20pll_hw_state:\n");
> + drm_dbg_kms(display->drm,
> + "tx[0] = 0x%.4x, tx[1] = 0x%.4x, tx[2] = 0x%.4x\n",
> hw_state->tx[0], hw_state->tx[1], hw_state->tx[2]);
> - drm_dbg_kms(&i915->drm, "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
> + drm_dbg_kms(display->drm,
> + "cmn[0] = 0x%.4x, cmn[1] = 0x%.4x, cmn[2] = 0x%.4x, cmn[3] = 0x%.4x\n",
> hw_state->cmn[0], hw_state->cmn[1], hw_state->cmn[2], hw_state->cmn[3]);
>
> if (intel_c20phy_use_mpllb(hw_state)) {
> for (i = 0; i < ARRAY_SIZE(hw_state->mpllb); i++)
> - drm_dbg_kms(&i915->drm, "mpllb[%d] = 0x%.4x\n", i, hw_state->mpllb[i]);
> + drm_dbg_kms(display->drm, "mpllb[%d] = 0x%.4x\n", i,
> + hw_state->mpllb[i]);
> } else {
> for (i = 0; i < ARRAY_SIZE(hw_state->mplla); i++)
> - drm_dbg_kms(&i915->drm, "mplla[%d] = 0x%.4x\n", i, hw_state->mplla[i]);
> + drm_dbg_kms(display->drm, "mplla[%d] = 0x%.4x\n", i,
> + hw_state->mplla[i]);
> }
> }
>
> -void intel_cx0pll_dump_hw_state(struct drm_i915_private *i915,
> +void intel_cx0pll_dump_hw_state(struct intel_display *display,
> const struct intel_cx0pll_state *hw_state)
> {
> if (hw_state->use_c10)
> - intel_c10pll_dump_hw_state(i915, &hw_state->c10);
> + intel_c10pll_dump_hw_state(display, &hw_state->c10);
> else
> - intel_c20pll_dump_hw_state(i915, &hw_state->c20);
> + intel_c20pll_dump_hw_state(display, &hw_state->c20);
> }
>
> static u8 intel_c20_get_dp_rate(u32 clock)
> @@ -2538,7 +2556,7 @@ static int intel_get_c20_custom_width(u32 clock, bool dp)
> return 0;
> }
>
> -static void intel_c20_pll_program(struct drm_i915_private *i915,
> +static void intel_c20_pll_program(struct intel_display *display,
> const struct intel_crtc_state *crtc_state,
> struct intel_encoder *encoder)
> {
> @@ -2571,11 +2589,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> for (i = 0; i < ARRAY_SIZE(pll_state->tx); i++) {
> if (cntx)
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_A_TX_CNTX_CFG(i915, i),
> + PHY_C20_A_TX_CNTX_CFG(display, i),
> pll_state->tx[i]);
> else
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_B_TX_CNTX_CFG(i915, i),
> + PHY_C20_B_TX_CNTX_CFG(display, i),
> pll_state->tx[i]);
> }
>
> @@ -2583,11 +2601,11 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> for (i = 0; i < ARRAY_SIZE(pll_state->cmn); i++) {
> if (cntx)
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_A_CMN_CNTX_CFG(i915, i),
> + PHY_C20_A_CMN_CNTX_CFG(display, i),
> pll_state->cmn[i]);
> else
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_B_CMN_CNTX_CFG(i915, i),
> + PHY_C20_B_CMN_CNTX_CFG(display, i),
> pll_state->cmn[i]);
> }
>
> @@ -2596,22 +2614,22 @@ static void intel_c20_pll_program(struct drm_i915_private *i915,
> for (i = 0; i < ARRAY_SIZE(pll_state->mpllb); i++) {
> if (cntx)
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_A_MPLLB_CNTX_CFG(i915, i),
> + PHY_C20_A_MPLLB_CNTX_CFG(display, i),
> pll_state->mpllb[i]);
> else
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_B_MPLLB_CNTX_CFG(i915, i),
> + PHY_C20_B_MPLLB_CNTX_CFG(display, i),
> pll_state->mpllb[i]);
> }
> } else {
> for (i = 0; i < ARRAY_SIZE(pll_state->mplla); i++) {
> if (cntx)
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_A_MPLLA_CNTX_CFG(i915, i),
> + PHY_C20_A_MPLLA_CNTX_CFG(display, i),
> pll_state->mplla[i]);
> else
> intel_c20_sram_write(encoder, INTEL_CX0_LANE0,
> - PHY_C20_B_MPLLA_CNTX_CFG(i915, i),
> + PHY_C20_B_MPLLA_CNTX_CFG(display, i),
> pll_state->mplla[i]);
> }
> }
> @@ -2678,10 +2696,10 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> bool lane_reversal)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> u32 val = 0;
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL1(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_BUF_CTL1(display, encoder->port),
> XELPDP_PORT_REVERSAL,
> lane_reversal ? XELPDP_PORT_REVERSAL : 0);
>
> @@ -2703,7 +2721,7 @@ static void intel_program_port_clock_ctl(struct intel_encoder *encoder,
> else
> val |= crtc_state->dpll_hw_state.cx0pll.ssc_enabled ? XELPDP_SSC_ENABLE_PLLB : 0;
>
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_LANE1_PHY_CLOCK_SELECT | XELPDP_FORWARD_CLOCK_UNGATE |
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_SSC_ENABLE_PLLA |
> XELPDP_SSC_ENABLE_PLLB, val);
> @@ -2734,48 +2752,49 @@ static u32 intel_cx0_get_powerdown_state(u8 lane_mask, u8 state)
> static void intel_cx0_powerdown_change_sequence(struct intel_encoder *encoder,
> u8 lane_mask, u8 state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
> - i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(i915, port);
> + i915_reg_t buf_ctl2_reg = XELPDP_PORT_BUF_CTL2(display, port);
> int lane;
>
> - intel_de_rmw(i915, buf_ctl2_reg,
> + intel_de_rmw(display, buf_ctl2_reg,
> intel_cx0_get_powerdown_state(INTEL_CX0_BOTH_LANES, XELPDP_LANE_POWERDOWN_NEW_STATE_MASK),
> intel_cx0_get_powerdown_state(lane_mask, state));
>
> /* Wait for pending transactions.*/
> for_each_cx0_lane_in_mask(lane_mask, lane)
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_M2P_MSGBUS_CTL(i915, port, lane),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
> XELPDP_PORT_M2P_TRANSACTION_PENDING,
> XELPDP_MSGBUS_TIMEOUT_SLOW)) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "PHY %c Timeout waiting for previous transaction to complete. Reset the bus.\n",
> phy_name(phy));
> intel_cx0_bus_reset(encoder, lane);
> }
>
> - intel_de_rmw(i915, buf_ctl2_reg,
> + intel_de_rmw(display, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_powerdown_update(lane_mask));
>
> /* Update Timeout Value */
> - if (intel_de_wait_custom(i915, buf_ctl2_reg,
> + if (intel_de_wait_custom(display, buf_ctl2_reg,
> intel_cx0_get_powerdown_update(lane_mask), 0,
> XELPDP_PORT_POWERDOWN_UPDATE_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + drm_warn(display->drm,
> + "PHY %c failed to bring out of Lane reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
> }
>
> static void intel_cx0_setup_powerdown(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> + intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port),
> XELPDP_POWER_STATE_READY_MASK,
> XELPDP_POWER_STATE_READY(CX0_P2_STATE_READY));
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL3(i915, port),
> + intel_de_rmw(display, XELPDP_PORT_BUF_CTL3(display, port),
> XELPDP_POWER_STATE_ACTIVE_MASK |
> XELPDP_PLL_LANE_STAGGERING_DELAY_MASK,
> XELPDP_POWER_STATE_ACTIVE(CX0_P0_STATE_ACTIVE) |
> @@ -2807,7 +2826,7 @@ static u32 intel_cx0_get_pclk_refclk_ack(u8 lane_mask)
> static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
> bool lane_reversal)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum phy phy = intel_encoder_to_phy(encoder);
> u8 owned_lane_mask = intel_cx0_get_owned_lane_mask(encoder);
> @@ -2820,48 +2839,51 @@ static void intel_cx0_phy_lane_reset(struct intel_encoder *encoder,
> XELPDP_LANE_PHY_CURRENT_STATUS(1))
> : XELPDP_LANE_PHY_CURRENT_STATUS(0);
>
> - if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL1(i915, port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL1(display, port),
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_PHY_READY,
> XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "PHY %c failed to bring out of SOC reset after %dus.\n",
> + drm_warn(display->drm,
> + "PHY %c failed to bring out of SOC reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_BUF_SOC_READY_TIMEOUT_US);
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset,
> + intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset,
> lane_pipe_reset);
>
> - if (intel_de_wait_custom(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_phy_current_status, lane_phy_current_status,
> XELPDP_PORT_RESET_START_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dus.\n",
> + drm_warn(display->drm,
> + "PHY %c failed to bring out of Lane reset after %dus.\n",
> phy_name(phy), XELPDP_PORT_RESET_START_TIMEOUT_US);
>
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, port),
> intel_cx0_get_pclk_refclk_request(owned_lane_mask),
> intel_cx0_get_pclk_refclk_request(lane_mask));
>
> - if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, port),
> intel_cx0_get_pclk_refclk_ack(owned_lane_mask),
> intel_cx0_get_pclk_refclk_ack(lane_mask),
> XELPDP_REFCLK_ENABLE_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "PHY %c failed to request refclk after %dus.\n",
> + drm_warn(display->drm,
> + "PHY %c failed to request refclk after %dus.\n",
> phy_name(phy), XELPDP_REFCLK_ENABLE_TIMEOUT_US);
>
> intel_cx0_powerdown_change_sequence(encoder, INTEL_CX0_BOTH_LANES,
> CX0_P2_STATE_RESET);
> intel_cx0_setup_powerdown(encoder);
>
> - intel_de_rmw(i915, XELPDP_PORT_BUF_CTL2(i915, port), lane_pipe_reset, 0);
> + intel_de_rmw(display, XELPDP_PORT_BUF_CTL2(display, port), lane_pipe_reset, 0);
>
> - if (intel_de_wait_for_clear(i915, XELPDP_PORT_BUF_CTL2(i915, port),
> + if (intel_de_wait_for_clear(display, XELPDP_PORT_BUF_CTL2(display, port),
> lane_phy_current_status,
> XELPDP_PORT_RESET_END_TIMEOUT))
> - drm_warn(&i915->drm, "PHY %c failed to bring out of Lane reset after %dms.\n",
> + drm_warn(display->drm,
> + "PHY %c failed to bring out of Lane reset after %dms.\n",
> phy_name(phy), XELPDP_PORT_RESET_END_TIMEOUT);
> }
>
> -static void intel_cx0_program_phy_lane(struct drm_i915_private *i915,
> - struct intel_encoder *encoder, int lane_count,
> +static void intel_cx0_program_phy_lane(struct intel_encoder *encoder, int lane_count,
> bool lane_reversal)
> {
> int i;
> @@ -2930,7 +2952,7 @@ static u32 intel_cx0_get_pclk_pll_ack(u8 lane_mask)
> static void intel_cx0pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> @@ -2962,15 +2984,15 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>
> /* 5. Program PHY internal PLL internal registers. */
> if (intel_encoder_is_c10phy(encoder))
> - intel_c10_pll_program(i915, crtc_state, encoder);
> + intel_c10_pll_program(display, crtc_state, encoder);
> else
> - intel_c20_pll_program(i915, crtc_state, encoder);
> + intel_c20_pll_program(display, crtc_state, encoder);
>
> /*
> * 6. Program the enabled and disabled owned PHY lane
> * transmitters over message bus
> */
> - intel_cx0_program_phy_lane(i915, encoder, crtc_state->lane_count, lane_reversal);
> + intel_cx0_program_phy_lane(encoder, crtc_state->lane_count, lane_reversal);
>
> /*
> * 7. Follow the Display Voltage Frequency Switching - Sequence
> @@ -2981,23 +3003,23 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
> * 8. Program DDI_CLK_VALFREQ to match intended DDI
> * clock frequency.
> */
> - intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> crtc_state->port_clock);
>
> /*
> * 9. Set PORT_CLOCK_CTL register PCLK PLL Request
> * LN<Lane for maxPCLK> to "1" to enable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_request(maxpclk_lane));
>
> /* 10. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK> == "1". */
> - if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES),
> intel_cx0_get_pclk_pll_ack(maxpclk_lane),
> XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "Port %c PLL not locked after %dus.\n",
> + drm_warn(display->drm, "Port %c PLL not locked after %dus.\n",
> phy_name(phy), XELPDP_PCLK_PLL_ENABLE_TIMEOUT_US);
>
> /*
> @@ -3011,15 +3033,16 @@ static void intel_cx0pll_enable(struct intel_encoder *encoder,
>
> int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - u32 clock;
> - u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
> + struct intel_display *display = to_intel_display(encoder);
> + u32 clock, val;
> +
> + val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
>
> clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
> - drm_WARN_ON(&i915->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
> - drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
> - drm_WARN_ON(&i915->drm, !(val & XELPDP_TBT_CLOCK_ACK));
> + drm_WARN_ON(display->drm, !(val & XELPDP_FORWARD_CLOCK_UNGATE));
> + drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_REQUEST));
> + drm_WARN_ON(display->drm, !(val & XELPDP_TBT_CLOCK_ACK));
>
> switch (clock) {
> case XELPDP_DDI_CLOCK_SELECT_TBT_162:
> @@ -3036,7 +3059,7 @@ int intel_mtl_tbt_calc_port_clock(struct intel_encoder *encoder)
> }
> }
>
> -static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
> +static int intel_mtl_tbt_clock_select(int clock)
> {
> switch (clock) {
> case 162000:
> @@ -3056,7 +3079,7 @@ static int intel_mtl_tbt_clock_select(struct drm_i915_private *i915, int clock)
> static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> u32 val = 0;
>
> @@ -3064,13 +3087,13 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> * 1. Program PORT_CLOCK_CTL REGISTER to configure
> * clock muxes, gating and SSC
> */
> - val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(i915, crtc_state->port_clock));
> + val |= XELPDP_DDI_CLOCK_SELECT(intel_mtl_tbt_clock_select(crtc_state->port_clock));
> val |= XELPDP_FORWARD_CLOCK_UNGATE;
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK | XELPDP_FORWARD_CLOCK_UNGATE, val);
>
> /* 2. Read back PORT_CLOCK_CTL REGISTER */
> - val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
> + val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
>
> /*
> * 3. Follow the Display Voltage Frequency Switching - Sequence
> @@ -3081,14 +3104,15 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> * 4. Set PORT_CLOCK_CTL register TBT CLOCK Request to "1" to enable PLL.
> */
> val |= XELPDP_TBT_CLOCK_REQUEST;
> - intel_de_write(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port), val);
> + intel_de_write(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port), val);
>
> /* 5. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "1". */
> - if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_TBT_CLOCK_ACK,
> XELPDP_TBT_CLOCK_ACK,
> 100, 0, NULL))
> - drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
> + drm_warn(display->drm,
> + "[ENCODER:%d:%s][%c] PHY PLL not locked after 100us.\n",
> encoder->base.base.id, encoder->base.name, phy_name(phy));
>
> /*
> @@ -3100,7 +3124,7 @@ static void intel_mtl_tbt_pll_enable(struct intel_encoder *encoder,
> * 7. Program DDI_CLK_VALFREQ to match intended DDI
> * clock frequency.
> */
> - intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port),
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port),
> crtc_state->port_clock);
> }
>
> @@ -3130,7 +3154,7 @@ static u8 cx0_power_control_disable_val(struct intel_encoder *encoder)
>
> static void intel_cx0pll_disable(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
> intel_wakeref_t wakeref = intel_cx0_phy_transaction_begin(encoder);
>
> @@ -3147,21 +3171,22 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> * 3. Set PORT_CLOCK_CTL register PCLK PLL Request LN<Lane for maxPCLK>
> * to "0" to disable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> intel_cx0_get_pclk_pll_request(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_request(INTEL_CX0_BOTH_LANES), 0);
>
> /* 4. Program DDI_CLK_VALFREQ to 0. */
> - intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
>
> /*
> * 5. Poll on PORT_CLOCK_CTL PCLK PLL Ack LN<Lane for maxPCLK**> == "0".
> */
> - if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> intel_cx0_get_pclk_pll_ack(INTEL_CX0_BOTH_LANES) |
> intel_cx0_get_pclk_refclk_ack(INTEL_CX0_BOTH_LANES), 0,
> XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US, 0, NULL))
> - drm_warn(&i915->drm, "Port %c PLL not unlocked after %dus.\n",
> + drm_warn(display->drm,
> + "Port %c PLL not unlocked after %dus.\n",
> phy_name(phy), XELPDP_PCLK_PLL_DISABLE_TIMEOUT_US);
>
> /*
> @@ -3170,9 +3195,9 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
> */
>
> /* 7. Program PORT_CLOCK_CTL register to disable and gate clocks. */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK, 0);
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
> intel_cx0_phy_transaction_end(encoder, wakeref);
> @@ -3180,7 +3205,7 @@ static void intel_cx0pll_disable(struct intel_encoder *encoder)
>
> static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum phy phy = intel_encoder_to_phy(encoder);
>
> /*
> @@ -3191,13 +3216,14 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 2. Set PORT_CLOCK_CTL register TBT CLOCK Request to "0" to disable PLL.
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_TBT_CLOCK_REQUEST, 0);
>
> /* 3. Poll on PORT_CLOCK_CTL TBT CLOCK Ack == "0". */
> - if (intel_de_wait_custom(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + if (intel_de_wait_custom(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_TBT_CLOCK_ACK, 0, 10, 0, NULL))
> - drm_warn(&i915->drm, "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
> + drm_warn(display->drm,
> + "[ENCODER:%d:%s][%c] PHY PLL not unlocked after 10us.\n",
> encoder->base.base.id, encoder->base.name, phy_name(phy));
>
> /*
> @@ -3208,12 +3234,12 @@ static void intel_mtl_tbt_pll_disable(struct intel_encoder *encoder)
> /*
> * 5. Program PORT CLOCK CTRL register to disable and gate clocks
> */
> - intel_de_rmw(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port),
> + intel_de_rmw(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port),
> XELPDP_DDI_CLOCK_SELECT_MASK |
> XELPDP_FORWARD_CLOCK_UNGATE, 0);
>
> /* 6. Program DDI_CLK_VALFREQ to 0. */
> - intel_de_write(i915, DDI_CLK_VALFREQ(encoder->port), 0);
> + intel_de_write(display, DDI_CLK_VALFREQ(encoder->port), 0);
> }
>
> void intel_mtl_pll_disable(struct intel_encoder *encoder)
> @@ -3230,13 +3256,15 @@ enum icl_port_dpll_id
> intel_mtl_port_pll_type(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> + u32 val, clock;
> +
> /*
> * TODO: Determine the PLL type from the SW state, once MTL PLL
> * handling is done via the standard shared DPLL framework.
> */
> - u32 val = intel_de_read(i915, XELPDP_PORT_CLOCK_CTL(i915, encoder->port));
> - u32 clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
> + val = intel_de_read(display, XELPDP_PORT_CLOCK_CTL(display, encoder->port));
> + clock = REG_FIELD_GET(XELPDP_DDI_CLOCK_SELECT_MASK, val);
>
> if (clock == XELPDP_DDI_CLOCK_SELECT_MAXPCLK ||
> clock == XELPDP_DDI_CLOCK_SELECT_DIV18CLK)
> @@ -3408,13 +3436,13 @@ static void intel_c20pll_state_verify(const struct intel_crtc_state *state,
> void intel_cx0pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc)
> {
> - struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_display *display = to_intel_display(state);
> const struct intel_crtc_state *new_crtc_state =
> intel_atomic_get_new_crtc_state(state, crtc);
> struct intel_encoder *encoder;
> struct intel_cx0pll_state mpll_hw_state = {};
>
> - if (DISPLAY_VER(i915) < 14)
> + if (DISPLAY_VER(display) < 14)
> return;
>
> if (!new_crtc_state->hw.active)
> diff --git a/drivers/gpu/drm/i915/display/intel_cx0_phy.h b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> index 9004b99bb51f..711168882684 100644
> --- a/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_cx0_phy.h
> @@ -7,17 +7,15 @@
> #define __INTEL_CX0_PHY_H__
>
> #include <linux/types.h>
> -#include <linux/bitfield.h>
> -#include <linux/bits.h>
I believe this deserves a separate patch, no?!
>
> enum icl_port_dpll_id;
> -struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_c10pll_state;
> struct intel_c20pll_state;
> -struct intel_cx0pll_state;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_cx0pll_state;
> +struct intel_display;
> struct intel_encoder;
> struct intel_hdmi;
>
> @@ -35,7 +33,7 @@ void intel_cx0pll_readout_hw_state(struct intel_encoder *encoder,
> int intel_cx0pll_calc_port_clock(struct intel_encoder *encoder,
> const struct intel_cx0pll_state *pll_state);
>
> -void intel_cx0pll_dump_hw_state(struct drm_i915_private *dev_priv,
> +void intel_cx0pll_dump_hw_state(struct intel_display *display,
> const struct intel_cx0pll_state *hw_state);
> void intel_cx0pll_state_verify(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index ef1436146325..c19f01b63936 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5305,15 +5305,15 @@ pipe_config_cx0pll_mismatch(struct drm_printer *p, bool fastset,
> const struct intel_cx0pll_state *a,
> const struct intel_cx0pll_state *b)
> {
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> char *chipname = a->use_c10 ? "C10" : "C20";
>
> pipe_config_mismatch(p, fastset, crtc, name, chipname);
>
> drm_printf(p, "expected:\n");
> - intel_cx0pll_dump_hw_state(i915, a);
> + intel_cx0pll_dump_hw_state(display, a);
> drm_printf(p, "found:\n");
> - intel_cx0pll_dump_hw_state(i915, b);
> + intel_cx0pll_dump_hw_state(display, b);
> }
>
> bool
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 03/11] drm/i915/dpio: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
2024-10-22 15:57 ` [PATCH 01/11] drm/i915/gmbus: convert to struct intel_display Jani Nikula
2024-10-22 15:57 ` [PATCH 02/11] drm/i915/cx0: " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 14:54 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 04/11] drm/i915/hdcp: further conversion " Jani Nikula
` (15 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DPIO PHY code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_well.c | 19 ++-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 158 +++++++++---------
drivers/gpu/drm/i915/display/intel_dpio_phy.h | 22 +--
drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +-
4 files changed, 106 insertions(+), 99 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index adaf7cf3a33b..885bc2e563c5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -919,38 +919,45 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ struct intel_display *display = &dev_priv->display;
+
+ return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
{
+ struct intel_display *display = &dev_priv->display;
struct i915_power_well *power_well;
power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
+ bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv,
GLK_DISP_PW_DPIO_CMN_C);
if (intel_power_well_refcount(power_well) > 0)
- bxt_dpio_phy_verify_state(dev_priv,
+ bxt_dpio_phy_verify_state(display,
i915_power_well_instance(power_well)->bxt.phy);
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index d20e4e9cf7f7..0f12f2c3467c 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -219,8 +219,10 @@ static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = {
};
static const struct bxt_dpio_phy_info *
-bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
+bxt_get_phy_list(struct intel_display *display, int *count)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
+
if (IS_GEMINILAKE(dev_priv)) {
*count = ARRAY_SIZE(glk_dpio_phy_info);
return glk_dpio_phy_info;
@@ -231,22 +233,22 @@ bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
}
static const struct bxt_dpio_phy_info *
-bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)
{
int count;
const struct bxt_dpio_phy_info *phy_list =
- bxt_get_phy_list(dev_priv, &count);
+ bxt_get_phy_list(display, &count);
return &phy_list[phy];
}
-void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch)
{
const struct bxt_dpio_phy_info *phy_info, *phys;
int i, count;
- phys = bxt_get_phy_list(dev_priv, &count);
+ phys = bxt_get_phy_list(display, &count);
for (i = 0; i < count; i++) {
phy_info = &phys[i];
@@ -265,7 +267,7 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
}
}
- drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
+ drm_WARN(display->drm, 1, "PHY not found for PORT %c",
port_name(port));
*phy = DPIO_PHY0;
*ch = DPIO_CH0;
@@ -275,16 +277,16 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
* Like intel_de_rmw() but reads from a single per-lane register and
* writes to the group register to write the same value to all the lanes.
*/
-static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
+static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
i915_reg_t reg_single,
i915_reg_t reg_group,
u32 clear, u32 set)
{
u32 old, val;
- old = intel_de_read(i915, reg_single);
+ old = intel_de_read(display, reg_single);
val = (old & ~clear) | set;
- intel_de_write(i915, reg_group, val);
+ intel_de_write(display, reg_group, val);
return old;
}
@@ -292,30 +294,30 @@ static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
const struct intel_ddi_buf_trans *trans;
enum dpio_channel ch;
enum dpio_phy phy;
int lane, n_entries;
trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
- if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
+ if (drm_WARN_ON_ONCE(display->drm, !trans))
return;
- bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
+ bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);
/*
* While we write to the group register to program all lanes at once we
* can read only lane registers and we pick lanes 0/1 for that.
*/
- bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+ bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
BXT_PORT_PCS_DW10_GRP(phy, ch),
TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
for (lane = 0; lane < crtc_state->lane_count; lane++) {
int level = intel_ddi_level(encoder, crtc_state, lane);
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
MARGIN_000(trans->entries[level].bxt.margin) |
UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
@@ -325,50 +327,50 @@ void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
int level = intel_ddi_level(encoder, crtc_state, lane);
u32 val;
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
SCALE_DCOMP_METHOD,
trans->entries[level].bxt.enable ?
SCALE_DCOMP_METHOD : 0);
- val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
+ val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Disabled scaling while ouniqetrangenmethod was set");
}
for (lane = 0; lane < crtc_state->lane_count; lane++) {
int level = intel_ddi_level(encoder, crtc_state, lane);
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
DE_EMPHASIS_MASK,
DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
}
- bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
+ bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
BXT_PORT_PCS_DW10_GRP(phy, ch),
0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
}
-bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
+ if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
return false;
- if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
+ if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
(PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"DDI PHY %d powered, but power hasn't settled\n", phy);
return false;
}
- if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
- drm_dbg(&dev_priv->drm,
+ if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
+ drm_dbg(display->drm,
"DDI PHY %d powered, but still in reset\n", phy);
return false;
@@ -377,47 +379,44 @@ bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
return true;
}
-static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
{
- u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
+ u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
return REG_FIELD_GET(GRC_CODE_MASK, val);
}
-static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
+static void bxt_phy_wait_grc_done(struct intel_display *display,
enum dpio_phy phy)
{
- if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
- GRC_DONE, 10))
- drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
- phy);
+ if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
+ drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
}
-static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
- enum dpio_phy phy)
+static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
u32 val;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
+ if (bxt_dpio_phy_is_enabled(display, phy)) {
/* Still read out the GRC value for state verification */
if (phy_info->rcomp_phy != -1)
- dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
+ display->state.bxt_phy_grc = bxt_get_grc(display, phy);
- if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
- drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
+ if (bxt_dpio_phy_verify_state(display, phy)) {
+ drm_dbg(display->drm, "DDI PHY %d already enabled, "
"won't reprogram it\n", phy);
return;
}
- drm_dbg(&dev_priv->drm,
+ drm_dbg(display->drm,
"DDI PHY %d enabled with invalid state, "
"force reprogramming it\n", phy);
}
- intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
+ intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
/*
* The PHY registers start out inaccessible and respond to reads with
@@ -427,92 +426,91 @@ static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
* The flag should get set in 100us according to the HW team, but
* use 1ms due to occasional timeouts observed with that.
*/
- if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
+ if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1))
- drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
+ drm_err(display->drm, "timeout during PHY%d power on\n",
phy);
/* Program PLL Rcomp code offset */
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),
IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),
IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
/* Program power gating */
- intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
+ intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,
OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
if (phy_info->dual_channel)
- intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
+ intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,
DW6_OLDO_DYN_PWR_DOWN_EN);
if (phy_info->rcomp_phy != -1) {
u32 grc_code;
- bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
+ bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);
/*
* PHY0 isn't connected to an RCOMP resistor so copy over
* the corresponding calibrated value from PHY1, and disable
* the automatic calibration on PHY0.
*/
- val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
- dev_priv->display.state.bxt_phy_grc = val;
+ val = bxt_get_grc(display, phy_info->rcomp_phy);
+ display->state.bxt_phy_grc = val;
grc_code = GRC_CODE_FAST(val) |
GRC_CODE_SLOW(val) |
GRC_CODE_NOM(val);
- intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
- intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
+ intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);
+ intel_de_rmw(display, BXT_PORT_REF_DW8(phy),
0, GRC_DIS | GRC_RDY_OVRD);
}
if (phy_info->reset_delay)
udelay(phy_info->reset_delay);
- intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
+ intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
}
-void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
- intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
+ intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
- intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
+ intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
}
-void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
- const struct bxt_dpio_phy_info *phy_info =
- bxt_get_phy_info(dev_priv, phy);
+ const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);
enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
bool was_enabled;
- lockdep_assert_held(&dev_priv->display.power.domains.lock);
+ lockdep_assert_held(&display->power.domains.lock);
was_enabled = true;
if (rcomp_phy != -1)
- was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);
+ was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);
/*
* We need to copy the GRC calibration value from rcomp_phy,
* so make sure it's powered up.
*/
if (!was_enabled)
- _bxt_dpio_phy_init(dev_priv, rcomp_phy);
+ _bxt_dpio_phy_init(display, rcomp_phy);
- _bxt_dpio_phy_init(dev_priv, phy);
+ _bxt_dpio_phy_init(display, phy);
if (!was_enabled)
- bxt_dpio_phy_uninit(dev_priv, rcomp_phy);
+ bxt_dpio_phy_uninit(display, rcomp_phy);
}
static bool __printf(6, 7)
-__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
i915_reg_t reg, u32 mask, u32 expected,
const char *reg_fmt, ...)
{
@@ -520,7 +518,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
va_list args;
u32 val;
- val = intel_de_read(dev_priv, reg);
+ val = intel_de_read(display, reg);
if ((val & mask) == expected)
return true;
@@ -528,7 +526,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
vaf.fmt = reg_fmt;
vaf.va = &args;
- drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
+ drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
"current %08x, expected %08x (mask %08x)\n",
phy, &vaf, reg.reg, val, (val & ~mask) | expected,
mask);
@@ -538,20 +536,20 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
return false;
}
-bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy)
{
const struct bxt_dpio_phy_info *phy_info;
u32 mask;
bool ok;
- phy_info = bxt_get_phy_info(dev_priv, phy);
+ phy_info = bxt_get_phy_info(display, phy);
#define _CHK(reg, mask, exp, fmt, ...) \
- __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
+ __phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
## __VA_ARGS__)
- if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
+ if (!bxt_dpio_phy_is_enabled(display, phy))
return false;
ok = true;
@@ -575,7 +573,7 @@ bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
"BXT_PORT_CL2CM_DW6(%d)", phy);
if (phy_info->rcomp_phy != -1) {
- u32 grc_code = dev_priv->display.state.bxt_phy_grc;
+ u32 grc_code = display->state.bxt_phy_grc;
grc_code = GRC_CODE_FAST(grc_code) |
GRC_CODE_SLOW(grc_code) |
@@ -614,20 +612,20 @@ bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8 lane_lat_optim_mask)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum dpio_phy phy;
enum dpio_channel ch;
int lane;
- bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
for (lane = 0; lane < 4; lane++) {
/*
* Note that on CHV this flag is called UPAR, but has
* the same function.
*/
- intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
+ intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
LATENCY_OPTIM,
lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
}
@@ -636,18 +634,18 @@ void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
u8
bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
enum port port = encoder->port;
enum dpio_phy phy;
enum dpio_channel ch;
int lane;
u8 mask;
- bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
mask = 0;
for (lane = 0; lane < 4; lane++) {
- u32 val = intel_de_read(dev_priv,
+ u32 val = intel_de_read(display,
BXT_PORT_TX_DW14_LN(phy, ch, lane));
if (val & LATENCY_OPTIM)
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
index 226994dcb89b..a82939165546 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
@@ -10,9 +10,9 @@
enum pipe;
enum port;
-struct drm_i915_private;
struct intel_crtc_state;
struct intel_digital_port;
+struct intel_display;
struct intel_encoder;
enum dpio_channel {
@@ -27,15 +27,15 @@ enum dpio_phy {
};
#ifdef I915
-void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state);
-void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
-bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
+void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
+bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy);
-bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy);
u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
@@ -73,7 +73,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
const struct intel_crtc_state *old_crtc_state);
#else
-static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
+static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch)
{
}
@@ -81,18 +81,18 @@ static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
}
-static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
{
}
-static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
+static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
{
}
-static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
+static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
enum dpio_phy phy)
{
return false;
}
-static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
+static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
enum dpio_phy phy)
{
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
index f490b2157828..99962d8cc6b5 100644
--- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
@@ -2035,13 +2035,14 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
const struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct intel_display *display = &i915->display;
const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
enum dpio_phy phy;
enum dpio_channel ch;
u32 temp;
- bxt_port_to_phy_channel(i915, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
/* Non-SSC reference */
intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
@@ -2157,6 +2158,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
struct intel_shared_dpll *pll,
struct intel_dpll_hw_state *dpll_hw_state)
{
+ struct intel_display *display = &i915->display;
struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
intel_wakeref_t wakeref;
@@ -2165,7 +2167,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
u32 val;
bool ret;
- bxt_port_to_phy_channel(i915, port, &phy, &ch);
+ bxt_port_to_phy_channel(display, port, &phy, &ch);
wakeref = intel_display_power_get_if_enabled(i915,
POWER_DOMAIN_DISPLAY_CORE);
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 03/11] drm/i915/dpio: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 03/11] drm/i915/dpio: " Jani Nikula
@ 2024-10-23 14:54 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 14:54 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:20PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch DPIO PHY code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../i915/display/intel_display_power_well.c | 19 ++-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 158 +++++++++---------
> drivers/gpu/drm/i915/display/intel_dpio_phy.h | 22 +--
> drivers/gpu/drm/i915/display/intel_dpll_mgr.c | 6 +-
> 4 files changed, 106 insertions(+), 99 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index adaf7cf3a33b..885bc2e563c5 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -919,38 +919,45 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
> static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - bxt_dpio_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
> + struct intel_display *display = &dev_priv->display;
> +
> + bxt_dpio_phy_init(display, i915_power_well_instance(power_well)->bxt.phy);
> }
>
> static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - bxt_dpio_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
> + struct intel_display *display = &dev_priv->display;
> +
> + bxt_dpio_phy_uninit(display, i915_power_well_instance(power_well)->bxt.phy);
> }
>
> static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> - return bxt_dpio_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
> + struct intel_display *display = &dev_priv->display;
> +
> + return bxt_dpio_phy_is_enabled(display, i915_power_well_instance(power_well)->bxt.phy);
> }
>
> static void bxt_verify_dpio_phy_power_wells(struct drm_i915_private *dev_priv)
> {
> + struct intel_display *display = &dev_priv->display;
> struct i915_power_well *power_well;
>
> power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
> if (intel_power_well_refcount(power_well) > 0)
> - bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
> + bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
>
> power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
> if (intel_power_well_refcount(power_well) > 0)
> - bxt_dpio_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
> + bxt_dpio_phy_verify_state(display, i915_power_well_instance(power_well)->bxt.phy);
>
> if (IS_GEMINILAKE(dev_priv)) {
> power_well = lookup_power_well(dev_priv,
> GLK_DISP_PW_DPIO_CMN_C);
> if (intel_power_well_refcount(power_well) > 0)
> - bxt_dpio_phy_verify_state(dev_priv,
> + bxt_dpio_phy_verify_state(display,
> i915_power_well_instance(power_well)->bxt.phy);
> }
> }
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index d20e4e9cf7f7..0f12f2c3467c 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -219,8 +219,10 @@ static const struct bxt_dpio_phy_info glk_dpio_phy_info[] = {
> };
>
> static const struct bxt_dpio_phy_info *
> -bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
> +bxt_get_phy_list(struct intel_display *display, int *count)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> +
> if (IS_GEMINILAKE(dev_priv)) {
> *count = ARRAY_SIZE(glk_dpio_phy_info);
> return glk_dpio_phy_info;
> @@ -231,22 +233,22 @@ bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
> }
>
> static const struct bxt_dpio_phy_info *
> -bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +bxt_get_phy_info(struct intel_display *display, enum dpio_phy phy)
> {
> int count;
> const struct bxt_dpio_phy_info *phy_list =
> - bxt_get_phy_list(dev_priv, &count);
> + bxt_get_phy_list(display, &count);
>
> return &phy_list[phy];
> }
>
> -void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> +void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch)
> {
> const struct bxt_dpio_phy_info *phy_info, *phys;
> int i, count;
>
> - phys = bxt_get_phy_list(dev_priv, &count);
> + phys = bxt_get_phy_list(display, &count);
>
> for (i = 0; i < count; i++) {
> phy_info = &phys[i];
> @@ -265,7 +267,7 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> }
> }
>
> - drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
> + drm_WARN(display->drm, 1, "PHY not found for PORT %c",
> port_name(port));
> *phy = DPIO_PHY0;
> *ch = DPIO_CH0;
> @@ -275,16 +277,16 @@ void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> * Like intel_de_rmw() but reads from a single per-lane register and
> * writes to the group register to write the same value to all the lanes.
> */
> -static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
> +static u32 bxt_dpio_phy_rmw_grp(struct intel_display *display,
> i915_reg_t reg_single,
> i915_reg_t reg_group,
> u32 clear, u32 set)
> {
> u32 old, val;
>
> - old = intel_de_read(i915, reg_single);
> + old = intel_de_read(display, reg_single);
> val = (old & ~clear) | set;
> - intel_de_write(i915, reg_group, val);
> + intel_de_write(display, reg_group, val);
>
> return old;
> }
> @@ -292,30 +294,30 @@ static u32 bxt_dpio_phy_rmw_grp(struct drm_i915_private *i915,
> void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> const struct intel_ddi_buf_trans *trans;
> enum dpio_channel ch;
> enum dpio_phy phy;
> int lane, n_entries;
>
> trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
> - if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
> + if (drm_WARN_ON_ONCE(display->drm, !trans))
> return;
>
> - bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
> + bxt_port_to_phy_channel(display, encoder->port, &phy, &ch);
>
> /*
> * While we write to the group register to program all lanes at once we
> * can read only lane registers and we pick lanes 0/1 for that.
> */
> - bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
> + bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
> BXT_PORT_PCS_DW10_GRP(phy, ch),
> TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT, 0);
>
> for (lane = 0; lane < crtc_state->lane_count; lane++) {
> int level = intel_ddi_level(encoder, crtc_state, lane);
>
> - intel_de_rmw(dev_priv, BXT_PORT_TX_DW2_LN(phy, ch, lane),
> + intel_de_rmw(display, BXT_PORT_TX_DW2_LN(phy, ch, lane),
> MARGIN_000_MASK | UNIQ_TRANS_SCALE_MASK,
> MARGIN_000(trans->entries[level].bxt.margin) |
> UNIQ_TRANS_SCALE(trans->entries[level].bxt.scale));
> @@ -325,50 +327,50 @@ void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
> int level = intel_ddi_level(encoder, crtc_state, lane);
> u32 val;
>
> - intel_de_rmw(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane),
> + intel_de_rmw(display, BXT_PORT_TX_DW3_LN(phy, ch, lane),
> SCALE_DCOMP_METHOD,
> trans->entries[level].bxt.enable ?
> SCALE_DCOMP_METHOD : 0);
>
> - val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN(phy, ch, lane));
> + val = intel_de_read(display, BXT_PORT_TX_DW3_LN(phy, ch, lane));
> if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Disabled scaling while ouniqetrangenmethod was set");
> }
>
> for (lane = 0; lane < crtc_state->lane_count; lane++) {
> int level = intel_ddi_level(encoder, crtc_state, lane);
>
> - intel_de_rmw(dev_priv, BXT_PORT_TX_DW4_LN(phy, ch, lane),
> + intel_de_rmw(display, BXT_PORT_TX_DW4_LN(phy, ch, lane),
> DE_EMPHASIS_MASK,
> DE_EMPHASIS(trans->entries[level].bxt.deemphasis));
> }
>
> - bxt_dpio_phy_rmw_grp(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch),
> + bxt_dpio_phy_rmw_grp(display, BXT_PORT_PCS_DW10_LN01(phy, ch),
> BXT_PORT_PCS_DW10_GRP(phy, ch),
> 0, TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
> }
>
> -bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
> +bool bxt_dpio_phy_is_enabled(struct intel_display *display,
> enum dpio_phy phy)
> {
> const struct bxt_dpio_phy_info *phy_info;
>
> - phy_info = bxt_get_phy_info(dev_priv, phy);
> + phy_info = bxt_get_phy_info(display, phy);
>
> - if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
> + if (!(intel_de_read(display, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
> return false;
>
> - if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
> + if ((intel_de_read(display, BXT_PORT_CL1CM_DW0(phy)) &
> (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "DDI PHY %d powered, but power hasn't settled\n", phy);
>
> return false;
> }
>
> - if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
> - drm_dbg(&dev_priv->drm,
> + if (!(intel_de_read(display, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
> + drm_dbg(display->drm,
> "DDI PHY %d powered, but still in reset\n", phy);
>
> return false;
> @@ -377,47 +379,44 @@ bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
> return true;
> }
>
> -static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +static u32 bxt_get_grc(struct intel_display *display, enum dpio_phy phy)
> {
> - u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
> + u32 val = intel_de_read(display, BXT_PORT_REF_DW6(phy));
>
> return REG_FIELD_GET(GRC_CODE_MASK, val);
> }
>
> -static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
> +static void bxt_phy_wait_grc_done(struct intel_display *display,
> enum dpio_phy phy)
> {
> - if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
> - GRC_DONE, 10))
> - drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
> - phy);
> + if (intel_de_wait_for_set(display, BXT_PORT_REF_DW3(phy), GRC_DONE, 10))
> + drm_err(display->drm, "timeout waiting for PHY%d GRC\n", phy);
> }
>
> -static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
> - enum dpio_phy phy)
> +static void _bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
> {
> const struct bxt_dpio_phy_info *phy_info;
> u32 val;
>
> - phy_info = bxt_get_phy_info(dev_priv, phy);
> + phy_info = bxt_get_phy_info(display, phy);
>
> - if (bxt_dpio_phy_is_enabled(dev_priv, phy)) {
> + if (bxt_dpio_phy_is_enabled(display, phy)) {
> /* Still read out the GRC value for state verification */
> if (phy_info->rcomp_phy != -1)
> - dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
> + display->state.bxt_phy_grc = bxt_get_grc(display, phy);
>
> - if (bxt_dpio_phy_verify_state(dev_priv, phy)) {
> - drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
> + if (bxt_dpio_phy_verify_state(display, phy)) {
> + drm_dbg(display->drm, "DDI PHY %d already enabled, "
> "won't reprogram it\n", phy);
> return;
> }
>
> - drm_dbg(&dev_priv->drm,
> + drm_dbg(display->drm,
> "DDI PHY %d enabled with invalid state, "
> "force reprogramming it\n", phy);
> }
>
> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
>
> /*
> * The PHY registers start out inaccessible and respond to reads with
> @@ -427,92 +426,91 @@ static void _bxt_dpio_phy_init(struct drm_i915_private *dev_priv,
> * The flag should get set in 100us according to the HW team, but
> * use 1ms due to occasional timeouts observed with that.
> */
> - if (intel_de_wait_fw(dev_priv, BXT_PORT_CL1CM_DW0(phy),
> + if (intel_de_wait_fw(display, BXT_PORT_CL1CM_DW0(phy),
> PHY_RESERVED | PHY_POWER_GOOD, PHY_POWER_GOOD, 1))
> - drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
> + drm_err(display->drm, "timeout during PHY%d power on\n",
> phy);
>
> /* Program PLL Rcomp code offset */
> - intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy),
> + intel_de_rmw(display, BXT_PORT_CL1CM_DW9(phy),
> IREF0RC_OFFSET_MASK, IREF0RC_OFFSET(0xE4));
>
> - intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy),
> + intel_de_rmw(display, BXT_PORT_CL1CM_DW10(phy),
> IREF1RC_OFFSET_MASK, IREF1RC_OFFSET(0xE4));
>
> /* Program power gating */
> - intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
> + intel_de_rmw(display, BXT_PORT_CL1CM_DW28(phy), 0,
> OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
>
> if (phy_info->dual_channel)
> - intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
> + intel_de_rmw(display, BXT_PORT_CL2CM_DW6(phy), 0,
> DW6_OLDO_DYN_PWR_DOWN_EN);
>
> if (phy_info->rcomp_phy != -1) {
> u32 grc_code;
>
> - bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
> + bxt_phy_wait_grc_done(display, phy_info->rcomp_phy);
>
> /*
> * PHY0 isn't connected to an RCOMP resistor so copy over
> * the corresponding calibrated value from PHY1, and disable
> * the automatic calibration on PHY0.
> */
> - val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
> - dev_priv->display.state.bxt_phy_grc = val;
> + val = bxt_get_grc(display, phy_info->rcomp_phy);
> + display->state.bxt_phy_grc = val;
>
> grc_code = GRC_CODE_FAST(val) |
> GRC_CODE_SLOW(val) |
> GRC_CODE_NOM(val);
> - intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
> - intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
> + intel_de_write(display, BXT_PORT_REF_DW6(phy), grc_code);
> + intel_de_rmw(display, BXT_PORT_REF_DW8(phy),
> 0, GRC_DIS | GRC_RDY_OVRD);
> }
>
> if (phy_info->reset_delay)
> udelay(phy_info->reset_delay);
>
> - intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
> + intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
> }
>
> -void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
> {
> const struct bxt_dpio_phy_info *phy_info;
>
> - phy_info = bxt_get_phy_info(dev_priv, phy);
> + phy_info = bxt_get_phy_info(display, phy);
>
> - intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
> + intel_de_rmw(display, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
>
> - intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
> + intel_de_rmw(display, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
> }
>
> -void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
> {
> - const struct bxt_dpio_phy_info *phy_info =
> - bxt_get_phy_info(dev_priv, phy);
> + const struct bxt_dpio_phy_info *phy_info = bxt_get_phy_info(display, phy);
> enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
> bool was_enabled;
>
> - lockdep_assert_held(&dev_priv->display.power.domains.lock);
> + lockdep_assert_held(&display->power.domains.lock);
>
> was_enabled = true;
> if (rcomp_phy != -1)
> - was_enabled = bxt_dpio_phy_is_enabled(dev_priv, rcomp_phy);
> + was_enabled = bxt_dpio_phy_is_enabled(display, rcomp_phy);
>
> /*
> * We need to copy the GRC calibration value from rcomp_phy,
> * so make sure it's powered up.
> */
> if (!was_enabled)
> - _bxt_dpio_phy_init(dev_priv, rcomp_phy);
> + _bxt_dpio_phy_init(display, rcomp_phy);
>
> - _bxt_dpio_phy_init(dev_priv, phy);
> + _bxt_dpio_phy_init(display, phy);
>
> if (!was_enabled)
> - bxt_dpio_phy_uninit(dev_priv, rcomp_phy);
> + bxt_dpio_phy_uninit(display, rcomp_phy);
> }
>
> static bool __printf(6, 7)
> -__phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> +__phy_reg_verify_state(struct intel_display *display, enum dpio_phy phy,
> i915_reg_t reg, u32 mask, u32 expected,
> const char *reg_fmt, ...)
> {
> @@ -520,7 +518,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> va_list args;
> u32 val;
>
> - val = intel_de_read(dev_priv, reg);
> + val = intel_de_read(display, reg);
> if ((val & mask) == expected)
> return true;
>
> @@ -528,7 +526,7 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> vaf.fmt = reg_fmt;
> vaf.va = &args;
>
> - drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
> + drm_dbg(display->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
> "current %08x, expected %08x (mask %08x)\n",
> phy, &vaf, reg.reg, val, (val & ~mask) | expected,
> mask);
> @@ -538,20 +536,20 @@ __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> return false;
> }
>
> -bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
> +bool bxt_dpio_phy_verify_state(struct intel_display *display,
> enum dpio_phy phy)
> {
> const struct bxt_dpio_phy_info *phy_info;
> u32 mask;
> bool ok;
>
> - phy_info = bxt_get_phy_info(dev_priv, phy);
> + phy_info = bxt_get_phy_info(display, phy);
>
> #define _CHK(reg, mask, exp, fmt, ...) \
> - __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \
> + __phy_reg_verify_state(display, phy, reg, mask, exp, fmt, \
> ## __VA_ARGS__)
>
> - if (!bxt_dpio_phy_is_enabled(dev_priv, phy))
> + if (!bxt_dpio_phy_is_enabled(display, phy))
> return false;
>
> ok = true;
> @@ -575,7 +573,7 @@ bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
> "BXT_PORT_CL2CM_DW6(%d)", phy);
>
> if (phy_info->rcomp_phy != -1) {
> - u32 grc_code = dev_priv->display.state.bxt_phy_grc;
> + u32 grc_code = display->state.bxt_phy_grc;
>
> grc_code = GRC_CODE_FAST(grc_code) |
> GRC_CODE_SLOW(grc_code) |
> @@ -614,20 +612,20 @@ bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count)
> void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> u8 lane_lat_optim_mask)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum dpio_phy phy;
> enum dpio_channel ch;
> int lane;
>
> - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
> + bxt_port_to_phy_channel(display, port, &phy, &ch);
>
> for (lane = 0; lane < 4; lane++) {
> /*
> * Note that on CHV this flag is called UPAR, but has
> * the same function.
> */
> - intel_de_rmw(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
> + intel_de_rmw(display, BXT_PORT_TX_DW14_LN(phy, ch, lane),
> LATENCY_OPTIM,
> lane_lat_optim_mask & BIT(lane) ? LATENCY_OPTIM : 0);
> }
> @@ -636,18 +634,18 @@ void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> u8
> bxt_dpio_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> enum port port = encoder->port;
> enum dpio_phy phy;
> enum dpio_channel ch;
> int lane;
> u8 mask;
>
> - bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
> + bxt_port_to_phy_channel(display, port, &phy, &ch);
>
> mask = 0;
> for (lane = 0; lane < 4; lane++) {
> - u32 val = intel_de_read(dev_priv,
> + u32 val = intel_de_read(display,
> BXT_PORT_TX_DW14_LN(phy, ch, lane));
>
> if (val & LATENCY_OPTIM)
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.h b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> index 226994dcb89b..a82939165546 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.h
> @@ -10,9 +10,9 @@
>
> enum pipe;
> enum port;
> -struct drm_i915_private;
> struct intel_crtc_state;
> struct intel_digital_port;
> +struct intel_display;
> struct intel_encoder;
>
> enum dpio_channel {
> @@ -27,15 +27,15 @@ enum dpio_phy {
> };
>
> #ifdef I915
> -void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> +void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch);
> void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state);
> -void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy);
> -void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy);
> -bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
> +void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy);
> +void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy);
> +bool bxt_dpio_phy_is_enabled(struct intel_display *display,
> enum dpio_phy phy);
> -bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
> +bool bxt_dpio_phy_verify_state(struct intel_display *display,
> enum dpio_phy phy);
> u8 bxt_dpio_phy_calc_lane_lat_optim_mask(u8 lane_count);
> void bxt_dpio_phy_set_lane_optim_mask(struct intel_encoder *encoder,
> @@ -73,7 +73,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> const struct intel_crtc_state *old_crtc_state);
> #else
> -static inline void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> +static inline void bxt_port_to_phy_channel(struct intel_display *display, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch)
> {
> }
> @@ -81,18 +81,18 @@ static inline void bxt_dpio_phy_set_signal_levels(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> }
> -static inline void bxt_dpio_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
> {
> }
> -static inline void bxt_dpio_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
> +static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
> {
> }
> -static inline bool bxt_dpio_phy_is_enabled(struct drm_i915_private *dev_priv,
> +static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
> enum dpio_phy phy)
> {
> return false;
> }
> -static inline bool bxt_dpio_phy_verify_state(struct drm_i915_private *dev_priv,
> +static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
> enum dpio_phy phy)
> {
> return true;
> diff --git a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> index f490b2157828..99962d8cc6b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpll_mgr.c
> @@ -2035,13 +2035,14 @@ static void bxt_ddi_pll_enable(struct drm_i915_private *i915,
> struct intel_shared_dpll *pll,
> const struct intel_dpll_hw_state *dpll_hw_state)
> {
> + struct intel_display *display = &i915->display;
> const struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> enum dpio_phy phy;
> enum dpio_channel ch;
> u32 temp;
>
> - bxt_port_to_phy_channel(i915, port, &phy, &ch);
> + bxt_port_to_phy_channel(display, port, &phy, &ch);
>
> /* Non-SSC reference */
> intel_de_rmw(i915, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
> @@ -2157,6 +2158,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
> struct intel_shared_dpll *pll,
> struct intel_dpll_hw_state *dpll_hw_state)
> {
> + struct intel_display *display = &i915->display;
> struct bxt_dpll_hw_state *hw_state = &dpll_hw_state->bxt;
> enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
> intel_wakeref_t wakeref;
> @@ -2165,7 +2167,7 @@ static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *i915,
> u32 val;
> bool ret;
>
> - bxt_port_to_phy_channel(i915, port, &phy, &ch);
> + bxt_port_to_phy_channel(display, port, &phy, &ch);
>
> wakeref = intel_display_power_get_if_enabled(i915,
> POWER_DOMAIN_DISPLAY_CORE);
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 04/11] drm/i915/hdcp: further conversion to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (2 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 03/11] drm/i915/dpio: " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 14:55 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 05/11] drm/i915/dp/hdcp: convert " Jani Nikula
` (14 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
There are some unconverted stragglers left in the HDCP API still using
struct drm_i915_private. Convert to struct intel_display.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../drm/i915/display/intel_display_driver.c | 7 +++--
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 5 ++--
drivers/gpu/drm/i915/display/intel_hdcp.c | 30 ++++++++-----------
drivers/gpu/drm/i915/display/intel_hdcp.h | 10 +++----
drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +-
drivers/gpu/drm/xe/display/xe_display.c | 4 ++-
7 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ae5470078173..3b37a8a69201 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -485,7 +485,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
return 0;
err_hdcp:
- intel_hdcp_component_fini(i915);
+ intel_hdcp_component_fini(display);
err_mode_config:
intel_mode_config_cleanup(i915);
@@ -495,6 +495,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
/* part #3: call after gem init */
int intel_display_driver_probe(struct drm_i915_private *i915)
{
+ struct intel_display *display = &i915->display;
int ret;
if (!HAS_DISPLAY(i915))
@@ -505,7 +506,7 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
* the BIOS fb takeover and whatever else magic ggtt reservations
* happen during gem/ggtt init.
*/
- intel_hdcp_component_init(i915);
+ intel_hdcp_component_init(display);
/*
* Force all active planes to recompute their states. So that on
@@ -600,7 +601,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
/* flush any delayed tasks or pending work */
flush_workqueue(i915->unordered_wq);
- intel_hdcp_component_fini(i915);
+ intel_hdcp_component_fini(display);
intel_mode_config_cleanup(i915);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6aba1d03a9d2..df3aa5fe3441 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -6415,6 +6415,7 @@ bool
intel_dp_init_connector(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector)
{
+ struct intel_display *display = to_intel_display(dig_port);
struct drm_connector *connector = &intel_connector->base;
struct intel_dp *intel_dp = &dig_port->dp;
struct intel_encoder *intel_encoder = &dig_port->base;
@@ -6504,7 +6505,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
intel_dp_add_properties(intel_dp, connector);
- if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
+ if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
int ret = intel_dp_hdcp_init(dig_port, intel_connector);
if (ret)
drm_dbg_kms(&dev_priv->drm,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index dce645a07cdb..5d77adaaf566 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -873,13 +873,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
struct intel_connector *intel_connector)
{
- struct drm_device *dev = intel_connector->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(dig_port);
struct intel_encoder *intel_encoder = &dig_port->base;
enum port port = intel_encoder->port;
struct intel_dp *intel_dp = &dig_port->dp;
- if (!is_hdcp_supported(dev_priv, port))
+ if (!is_hdcp_supported(display, port))
return 0;
if (intel_connector->mst_port)
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
index ed6aa87403e2..870084af92d0 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
@@ -1192,10 +1192,10 @@ static void intel_hdcp_prop_work(struct work_struct *work)
drm_connector_put(&connector->base);
}
-bool is_hdcp_supported(struct drm_i915_private *i915, enum port port)
+bool is_hdcp_supported(struct intel_display *display, enum port port)
{
- return DISPLAY_RUNTIME_INFO(i915)->has_hdcp &&
- (DISPLAY_VER(i915) >= 12 || port < PORT_E);
+ return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&
+ (DISPLAY_VER(display) >= 12 || port < PORT_E);
}
static int
@@ -2301,9 +2301,9 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
return 0;
}
-static bool is_hdcp2_supported(struct drm_i915_private *i915)
+static bool is_hdcp2_supported(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
+ struct drm_i915_private *i915 = to_i915(display->drm);
if (intel_hdcp_gsc_cs_required(display))
return true;
@@ -2317,12 +2317,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *i915)
IS_COMETLAKE(i915));
}
-void intel_hdcp_component_init(struct drm_i915_private *i915)
+void intel_hdcp_component_init(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
int ret;
- if (!is_hdcp2_supported(i915))
+ if (!is_hdcp2_supported(display))
return;
mutex_lock(&display->hdcp.hdcp_mutex);
@@ -2367,19 +2366,18 @@ int intel_hdcp_init(struct intel_connector *connector,
struct intel_digital_port *dig_port,
const struct intel_hdcp_shim *shim)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
if (!shim)
return -EINVAL;
- if (is_hdcp2_supported(i915))
+ if (is_hdcp2_supported(display))
intel_hdcp2_init(connector, dig_port, shim);
- ret =
- drm_connector_attach_content_protection_property(&connector->base,
- hdcp->hdcp2_supported);
+ ret = drm_connector_attach_content_protection_property(&connector->base,
+ hdcp->hdcp2_supported);
if (ret) {
hdcp->hdcp2_supported = false;
kfree(dig_port->hdcp_port_data.streams);
@@ -2432,7 +2430,7 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state,
hdcp->stream_transcoder = INVALID_TRANSCODER;
}
- if (DISPLAY_VER(i915) >= 12)
+ if (DISPLAY_VER(display) >= 12)
dig_port->hdcp_port_data.hdcp_transcoder =
intel_get_hdcp_transcoder(hdcp->cpu_transcoder);
@@ -2583,10 +2581,8 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
_intel_hdcp_enable(state, encoder, crtc_state, conn_state);
}
-void intel_hdcp_component_fini(struct drm_i915_private *i915)
+void intel_hdcp_component_fini(struct intel_display *display)
{
- struct intel_display *display = to_intel_display(&i915->drm);
-
mutex_lock(&display->hdcp.hdcp_mutex);
if (!display->hdcp.comp_added) {
mutex_unlock(&display->hdcp.hdcp_mutex);
diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
index 477f2d2bb120..d99830cfb798 100644
--- a/drivers/gpu/drm/i915/display/intel_hdcp.h
+++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
@@ -12,13 +12,13 @@
struct drm_connector;
struct drm_connector_state;
-struct drm_i915_private;
struct intel_atomic_state;
struct intel_connector;
struct intel_crtc_state;
+struct intel_digital_port;
+struct intel_display;
struct intel_encoder;
struct intel_hdcp_shim;
-struct intel_digital_port;
enum port;
enum transcoder;
@@ -37,14 +37,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state);
-bool is_hdcp_supported(struct drm_i915_private *i915, enum port port);
+bool is_hdcp_supported(struct intel_display *display, enum port port);
bool intel_hdcp_get_capability(struct intel_connector *connector);
bool intel_hdcp2_get_capability(struct intel_connector *connector);
void intel_hdcp_get_remote_capability(struct intel_connector *connector,
bool *hdcp_capable,
bool *hdcp2_capable);
-void intel_hdcp_component_init(struct drm_i915_private *i915);
-void intel_hdcp_component_fini(struct drm_i915_private *i915);
+void intel_hdcp_component_init(struct intel_display *display);
+void intel_hdcp_component_fini(struct intel_display *display);
void intel_hdcp_cleanup(struct intel_connector *connector);
void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 022ba3635101..665b980cc74d 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -3025,7 +3025,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
struct intel_encoder *intel_encoder = &dig_port->base;
struct drm_device *dev = intel_encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
enum port port = intel_encoder->port;
struct cec_connector_info conn_info;
u8 ddc_pin;
@@ -3075,7 +3074,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
intel_connector_attach_encoder(intel_connector, intel_encoder);
intel_hdmi->attached_connector = intel_connector;
- if (is_hdcp_supported(dev_priv, port)) {
+ if (is_hdcp_supported(display, port)) {
int ret = intel_hdcp_init(intel_connector, dig_port,
&intel_hdmi_hdcp_shim);
if (ret)
diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
index 695c27ac6b0f..b5502f335f53 100644
--- a/drivers/gpu/drm/xe/display/xe_display.c
+++ b/drivers/gpu/drm/xe/display/xe_display.c
@@ -202,12 +202,14 @@ int xe_display_init(struct xe_device *xe)
void xe_display_fini(struct xe_device *xe)
{
+ struct intel_display *display = &xe->display;
+
if (!xe->info.probe_display)
return;
intel_hpd_poll_fini(xe);
- intel_hdcp_component_fini(xe);
+ intel_hdcp_component_fini(display);
intel_audio_deinit(xe);
}
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 04/11] drm/i915/hdcp: further conversion to struct intel_display
2024-10-22 15:57 ` [PATCH 04/11] drm/i915/hdcp: further conversion " Jani Nikula
@ 2024-10-23 14:55 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 14:55 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:21PM +0300, Jani Nikula wrote:
> There are some unconverted stragglers left in the HDCP API still using
> struct drm_i915_private. Convert to struct intel_display.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../drm/i915/display/intel_display_driver.c | 7 +++--
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 5 ++--
> drivers/gpu/drm/i915/display/intel_hdcp.c | 30 ++++++++-----------
> drivers/gpu/drm/i915/display/intel_hdcp.h | 10 +++----
> drivers/gpu/drm/i915/display/intel_hdmi.c | 3 +-
> drivers/gpu/drm/xe/display/xe_display.c | 4 ++-
> 7 files changed, 30 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
> index ae5470078173..3b37a8a69201 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_driver.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
> @@ -485,7 +485,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> return 0;
>
> err_hdcp:
> - intel_hdcp_component_fini(i915);
> + intel_hdcp_component_fini(display);
> err_mode_config:
> intel_mode_config_cleanup(i915);
>
> @@ -495,6 +495,7 @@ int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
> /* part #3: call after gem init */
> int intel_display_driver_probe(struct drm_i915_private *i915)
> {
> + struct intel_display *display = &i915->display;
> int ret;
>
> if (!HAS_DISPLAY(i915))
> @@ -505,7 +506,7 @@ int intel_display_driver_probe(struct drm_i915_private *i915)
> * the BIOS fb takeover and whatever else magic ggtt reservations
> * happen during gem/ggtt init.
> */
> - intel_hdcp_component_init(i915);
> + intel_hdcp_component_init(display);
>
> /*
> * Force all active planes to recompute their states. So that on
> @@ -600,7 +601,7 @@ void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
> /* flush any delayed tasks or pending work */
> flush_workqueue(i915->unordered_wq);
>
> - intel_hdcp_component_fini(i915);
> + intel_hdcp_component_fini(display);
>
> intel_mode_config_cleanup(i915);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6aba1d03a9d2..df3aa5fe3441 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -6415,6 +6415,7 @@ bool
> intel_dp_init_connector(struct intel_digital_port *dig_port,
> struct intel_connector *intel_connector)
> {
> + struct intel_display *display = to_intel_display(dig_port);
> struct drm_connector *connector = &intel_connector->base;
> struct intel_dp *intel_dp = &dig_port->dp;
> struct intel_encoder *intel_encoder = &dig_port->base;
> @@ -6504,7 +6505,7 @@ intel_dp_init_connector(struct intel_digital_port *dig_port,
>
> intel_dp_add_properties(intel_dp, connector);
>
> - if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) {
> + if (is_hdcp_supported(display, port) && !intel_dp_is_edp(intel_dp)) {
> int ret = intel_dp_hdcp_init(dig_port, intel_connector);
> if (ret)
> drm_dbg_kms(&dev_priv->drm,
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index dce645a07cdb..5d77adaaf566 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -873,13 +873,12 @@ static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
> int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
> struct intel_connector *intel_connector)
> {
> - struct drm_device *dev = intel_connector->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(dig_port);
> struct intel_encoder *intel_encoder = &dig_port->base;
> enum port port = intel_encoder->port;
> struct intel_dp *intel_dp = &dig_port->dp;
>
> - if (!is_hdcp_supported(dev_priv, port))
> + if (!is_hdcp_supported(display, port))
> return 0;
>
> if (intel_connector->mst_port)
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.c b/drivers/gpu/drm/i915/display/intel_hdcp.c
> index ed6aa87403e2..870084af92d0 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.c
> @@ -1192,10 +1192,10 @@ static void intel_hdcp_prop_work(struct work_struct *work)
> drm_connector_put(&connector->base);
> }
>
> -bool is_hdcp_supported(struct drm_i915_private *i915, enum port port)
> +bool is_hdcp_supported(struct intel_display *display, enum port port)
> {
> - return DISPLAY_RUNTIME_INFO(i915)->has_hdcp &&
> - (DISPLAY_VER(i915) >= 12 || port < PORT_E);
> + return DISPLAY_RUNTIME_INFO(display)->has_hdcp &&
> + (DISPLAY_VER(display) >= 12 || port < PORT_E);
> }
>
> static int
> @@ -2301,9 +2301,9 @@ static int initialize_hdcp_port_data(struct intel_connector *connector,
> return 0;
> }
>
> -static bool is_hdcp2_supported(struct drm_i915_private *i915)
> +static bool is_hdcp2_supported(struct intel_display *display)
> {
> - struct intel_display *display = to_intel_display(&i915->drm);
> + struct drm_i915_private *i915 = to_i915(display->drm);
>
> if (intel_hdcp_gsc_cs_required(display))
> return true;
> @@ -2317,12 +2317,11 @@ static bool is_hdcp2_supported(struct drm_i915_private *i915)
> IS_COMETLAKE(i915));
> }
>
> -void intel_hdcp_component_init(struct drm_i915_private *i915)
> +void intel_hdcp_component_init(struct intel_display *display)
> {
> - struct intel_display *display = to_intel_display(&i915->drm);
> int ret;
>
> - if (!is_hdcp2_supported(i915))
> + if (!is_hdcp2_supported(display))
> return;
>
> mutex_lock(&display->hdcp.hdcp_mutex);
> @@ -2367,19 +2366,18 @@ int intel_hdcp_init(struct intel_connector *connector,
> struct intel_digital_port *dig_port,
> const struct intel_hdcp_shim *shim)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> if (!shim)
> return -EINVAL;
>
> - if (is_hdcp2_supported(i915))
> + if (is_hdcp2_supported(display))
> intel_hdcp2_init(connector, dig_port, shim);
>
> - ret =
> - drm_connector_attach_content_protection_property(&connector->base,
> - hdcp->hdcp2_supported);
> + ret = drm_connector_attach_content_protection_property(&connector->base,
> + hdcp->hdcp2_supported);
> if (ret) {
> hdcp->hdcp2_supported = false;
> kfree(dig_port->hdcp_port_data.streams);
> @@ -2432,7 +2430,7 @@ static int _intel_hdcp_enable(struct intel_atomic_state *state,
> hdcp->stream_transcoder = INVALID_TRANSCODER;
> }
>
> - if (DISPLAY_VER(i915) >= 12)
> + if (DISPLAY_VER(display) >= 12)
> dig_port->hdcp_port_data.hdcp_transcoder =
> intel_get_hdcp_transcoder(hdcp->cpu_transcoder);
>
> @@ -2583,10 +2581,8 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> _intel_hdcp_enable(state, encoder, crtc_state, conn_state);
> }
>
> -void intel_hdcp_component_fini(struct drm_i915_private *i915)
> +void intel_hdcp_component_fini(struct intel_display *display)
> {
> - struct intel_display *display = to_intel_display(&i915->drm);
> -
> mutex_lock(&display->hdcp.hdcp_mutex);
> if (!display->hdcp.comp_added) {
> mutex_unlock(&display->hdcp.hdcp_mutex);
> diff --git a/drivers/gpu/drm/i915/display/intel_hdcp.h b/drivers/gpu/drm/i915/display/intel_hdcp.h
> index 477f2d2bb120..d99830cfb798 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdcp.h
> +++ b/drivers/gpu/drm/i915/display/intel_hdcp.h
> @@ -12,13 +12,13 @@
>
> struct drm_connector;
> struct drm_connector_state;
> -struct drm_i915_private;
> struct intel_atomic_state;
> struct intel_connector;
> struct intel_crtc_state;
> +struct intel_digital_port;
> +struct intel_display;
> struct intel_encoder;
> struct intel_hdcp_shim;
> -struct intel_digital_port;
> enum port;
> enum transcoder;
>
> @@ -37,14 +37,14 @@ void intel_hdcp_update_pipe(struct intel_atomic_state *state,
> struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state);
> -bool is_hdcp_supported(struct drm_i915_private *i915, enum port port);
> +bool is_hdcp_supported(struct intel_display *display, enum port port);
> bool intel_hdcp_get_capability(struct intel_connector *connector);
> bool intel_hdcp2_get_capability(struct intel_connector *connector);
> void intel_hdcp_get_remote_capability(struct intel_connector *connector,
> bool *hdcp_capable,
> bool *hdcp2_capable);
> -void intel_hdcp_component_init(struct drm_i915_private *i915);
> -void intel_hdcp_component_fini(struct drm_i915_private *i915);
> +void intel_hdcp_component_init(struct intel_display *display);
> +void intel_hdcp_component_fini(struct intel_display *display);
> void intel_hdcp_cleanup(struct intel_connector *connector);
> void intel_hdcp_handle_cp_irq(struct intel_connector *connector);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
> index 022ba3635101..665b980cc74d 100644
> --- a/drivers/gpu/drm/i915/display/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
> @@ -3025,7 +3025,6 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> struct intel_hdmi *intel_hdmi = &dig_port->hdmi;
> struct intel_encoder *intel_encoder = &dig_port->base;
> struct drm_device *dev = intel_encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> enum port port = intel_encoder->port;
> struct cec_connector_info conn_info;
> u8 ddc_pin;
> @@ -3075,7 +3074,7 @@ void intel_hdmi_init_connector(struct intel_digital_port *dig_port,
> intel_connector_attach_encoder(intel_connector, intel_encoder);
> intel_hdmi->attached_connector = intel_connector;
>
> - if (is_hdcp_supported(dev_priv, port)) {
> + if (is_hdcp_supported(display, port)) {
> int ret = intel_hdcp_init(intel_connector, dig_port,
> &intel_hdmi_hdcp_shim);
> if (ret)
> diff --git a/drivers/gpu/drm/xe/display/xe_display.c b/drivers/gpu/drm/xe/display/xe_display.c
> index 695c27ac6b0f..b5502f335f53 100644
> --- a/drivers/gpu/drm/xe/display/xe_display.c
> +++ b/drivers/gpu/drm/xe/display/xe_display.c
> @@ -202,12 +202,14 @@ int xe_display_init(struct xe_device *xe)
>
> void xe_display_fini(struct xe_device *xe)
> {
> + struct intel_display *display = &xe->display;
> +
> if (!xe->info.probe_display)
> return;
>
> intel_hpd_poll_fini(xe);
>
> - intel_hdcp_component_fini(xe);
> + intel_hdcp_component_fini(display);
> intel_audio_deinit(xe);
> }
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 05/11] drm/i915/dp/hdcp: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (3 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 04/11] drm/i915/hdcp: further conversion " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 14:57 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 06/11] drm/i915/crt: " Jani Nikula
` (13 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch DP HDCP code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++++++++++----------
1 file changed, 45 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
index 5d77adaaf566..e7f9619bccc0 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
@@ -58,7 +58,7 @@ static
int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
u8 *an)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
u8 aksv[DRM_HDCP_KSV_LEN] = {};
ssize_t dpcd_ret;
@@ -66,7 +66,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
an, DRM_HDCP_AN_LEN);
if (dpcd_ret != DRM_HDCP_AN_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write An over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -82,7 +82,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
aksv, DRM_HDCP_KSV_LEN);
if (dpcd_ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Failed to write Aksv over DP/AUX (%zd)\n",
dpcd_ret);
return dpcd_ret >= 0 ? -EIO : dpcd_ret;
@@ -93,13 +93,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
u8 *bksv)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
DRM_HDCP_KSV_LEN);
if (ret != DRM_HDCP_KSV_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read Bksv from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -109,7 +109,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
u8 *bstatus)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
/*
@@ -120,7 +120,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
bstatus, DRM_HDCP_BSTATUS_LEN);
if (ret != DRM_HDCP_BSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -129,7 +129,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
static
int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
- struct drm_i915_private *i915,
+ struct intel_display *display,
u8 *bcaps)
{
ssize_t ret;
@@ -137,7 +137,7 @@ int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
bcaps, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bcaps from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -149,11 +149,11 @@ static
int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
bool *repeater_present)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -165,13 +165,14 @@ static
int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
u8 *ri_prime)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
ri_prime, DRM_HDCP_RI_LEN);
if (ret != DRM_HDCP_RI_LEN) {
- drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
+ drm_dbg_kms(display->drm,
+ "Read Ri' from DP/AUX failed (%zd)\n",
ret);
return ret >= 0 ? -EIO : ret;
}
@@ -182,14 +183,14 @@ static
int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
bool *ksv_ready)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -201,7 +202,7 @@ static
int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
int num_downstream, u8 *ksv_fifo)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
int i;
@@ -213,7 +214,7 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
ksv_fifo + i * DRM_HDCP_KSV_LEN,
len);
if (ret != len) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read ksv[%d] from DP/AUX failed (%zd)\n",
i, ret);
return ret >= 0 ? -EIO : ret;
@@ -226,7 +227,7 @@ static
int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
int i, u32 *part)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
@@ -236,7 +237,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
DP_AUX_HDCP_V_PRIME(i), part,
DRM_HDCP_V_PRIME_PART_LEN);
if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
return ret >= 0 ? -EIO : ret;
}
@@ -256,14 +257,14 @@ static
bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
struct intel_connector *connector)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bstatus;
ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
&bstatus, 1);
if (ret != 1) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return false;
}
@@ -275,11 +276,11 @@ static
int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
bool *hdcp_capable)
{
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+ struct intel_display *display = to_intel_display(dig_port);
ssize_t ret;
u8 bcaps;
- ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
if (ret)
return ret;
@@ -342,7 +343,7 @@ static int
intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
u8 *rx_status)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct drm_dp_aux *aux = &dig_port->dp.aux;
ssize_t ret;
@@ -351,7 +352,7 @@ intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
HDCP_2_2_DP_RXSTATUS_LEN);
if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"Read bstatus from DP/AUX failed (%zd)\n", ret);
return ret >= 0 ? -EIO : ret;
}
@@ -397,7 +398,7 @@ static ssize_t
intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
const struct hdcp2_dp_msg_data *hdcp2_msg_data)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -430,7 +431,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
}
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"msg_id %d, ret %d, timeout(mSec): %d\n",
hdcp2_msg_data->msg_id, ret, timeout);
@@ -514,8 +515,8 @@ static
int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
u8 msg_id, void *buf, size_t size)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
struct drm_dp_aux *aux = &dig_port->dp.aux;
struct intel_dp *dp = &dig_port->dp;
struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
@@ -568,7 +569,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
ret = drm_dp_dpcd_read(aux, offset,
(void *)byte, len);
if (ret < 0) {
- drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
+ drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
msg_id, ret);
return ret;
}
@@ -581,7 +582,8 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
if (hdcp2_msg_data->msg_read_timeout > 0) {
msg_expired = ktime_after(ktime_get_raw(), msg_end);
if (msg_expired) {
- drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
+ drm_dbg_kms(display->drm,
+ "msg_id %d, entire msg read timeout(mSec): %d\n",
msg_id, hdcp2_msg_data->msg_read_timeout);
return -ETIMEDOUT;
}
@@ -696,7 +698,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
bool *hdcp_capable,
bool *hdcp2_capable)
{
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
+ struct intel_display *display = to_intel_display(connector);
struct drm_dp_aux *aux;
u8 bcaps;
int ret;
@@ -709,10 +711,10 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
aux = &connector->port->aux;
ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
if (ret)
- drm_dbg_kms(&i915->drm,
+ drm_dbg_kms(display->drm,
"HDCP2 DPCD capability read failed err: %d\n", ret);
- ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
+ ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
if (ret)
return ret;
@@ -745,8 +747,8 @@ static int
intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
int ret;
@@ -754,7 +756,7 @@ intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
hdcp->stream_transcoder, enable,
TRANS_DDI_HDCP_SELECT);
if (ret)
- drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
+ drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
enable ? "Enable" : "Disable", ret);
return ret;
}
@@ -763,8 +765,8 @@ static int
intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct intel_hdcp *hdcp = &connector->hdcp;
enum port port = dig_port->base.port;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -780,10 +782,10 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
return -EINVAL;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
+ if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
stream_enc_status, enable ? stream_enc_status : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
return -ETIMEDOUT;
}
@@ -795,8 +797,8 @@ static int
intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
bool enable)
{
+ struct intel_display *display = to_intel_display(connector);
struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
- struct drm_i915_private *i915 = to_i915(connector->base.dev);
struct hdcp_port_data *data = &dig_port->hdcp_port_data;
struct intel_hdcp *hdcp = &connector->hdcp;
enum transcoder cpu_transcoder = hdcp->stream_transcoder;
@@ -804,8 +806,8 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
enum port port = dig_port->base.port;
int ret;
- drm_WARN_ON(&i915->drm, enable &&
- !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
+ drm_WARN_ON(display->drm, enable &&
+ !!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
& AUTH_STREAM_TYPE) != data->streams[0].stream_type);
ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
@@ -813,11 +815,11 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
return ret;
/* Wait for encryption confirmation */
- if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
+ if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
STREAM_ENCRYPTION_STATUS,
enable ? STREAM_ENCRYPTION_STATUS : 0,
HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
- drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
+ drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
return -ETIMEDOUT;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 05/11] drm/i915/dp/hdcp: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 05/11] drm/i915/dp/hdcp: convert " Jani Nikula
@ 2024-10-23 14:57 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 14:57 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:22PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch DP HDCP code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_hdcp.c | 88 ++++++++++----------
> 1 file changed, 45 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> index 5d77adaaf566..e7f9619bccc0 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_hdcp.c
> @@ -58,7 +58,7 @@ static
> int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
> u8 *an)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> u8 aksv[DRM_HDCP_KSV_LEN] = {};
> ssize_t dpcd_ret;
>
> @@ -66,7 +66,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
> dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
> an, DRM_HDCP_AN_LEN);
> if (dpcd_ret != DRM_HDCP_AN_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Failed to write An over DP/AUX (%zd)\n",
> dpcd_ret);
> return dpcd_ret >= 0 ? -EIO : dpcd_ret;
> @@ -82,7 +82,7 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
> dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
> aksv, DRM_HDCP_KSV_LEN);
> if (dpcd_ret != DRM_HDCP_KSV_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Failed to write Aksv over DP/AUX (%zd)\n",
> dpcd_ret);
> return dpcd_ret >= 0 ? -EIO : dpcd_ret;
> @@ -93,13 +93,13 @@ int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
> static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
> u8 *bksv)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
>
> ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
> DRM_HDCP_KSV_LEN);
> if (ret != DRM_HDCP_KSV_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read Bksv from DP/AUX failed (%zd)\n", ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -109,7 +109,7 @@ static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
> static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
> u8 *bstatus)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
>
> /*
> @@ -120,7 +120,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
> ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
> bstatus, DRM_HDCP_BSTATUS_LEN);
> if (ret != DRM_HDCP_BSTATUS_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read bstatus from DP/AUX failed (%zd)\n", ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -129,7 +129,7 @@ static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
>
> static
> int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
> - struct drm_i915_private *i915,
> + struct intel_display *display,
> u8 *bcaps)
> {
> ssize_t ret;
> @@ -137,7 +137,7 @@ int intel_dp_hdcp_read_bcaps(struct drm_dp_aux *aux,
> ret = drm_dp_dpcd_read(aux, DP_AUX_HDCP_BCAPS,
> bcaps, 1);
> if (ret != 1) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read bcaps from DP/AUX failed (%zd)\n", ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -149,11 +149,11 @@ static
> int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
> bool *repeater_present)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
> u8 bcaps;
>
> - ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
> + ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
> if (ret)
> return ret;
>
> @@ -165,13 +165,14 @@ static
> int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
> u8 *ri_prime)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
>
> ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
> ri_prime, DRM_HDCP_RI_LEN);
> if (ret != DRM_HDCP_RI_LEN) {
> - drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
> + drm_dbg_kms(display->drm,
> + "Read Ri' from DP/AUX failed (%zd)\n",
> ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -182,14 +183,14 @@ static
> int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
> bool *ksv_ready)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
> u8 bstatus;
>
> ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
> &bstatus, 1);
> if (ret != 1) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read bstatus from DP/AUX failed (%zd)\n", ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -201,7 +202,7 @@ static
> int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
> int num_downstream, u8 *ksv_fifo)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
> int i;
>
> @@ -213,7 +214,7 @@ int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
> ksv_fifo + i * DRM_HDCP_KSV_LEN,
> len);
> if (ret != len) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read ksv[%d] from DP/AUX failed (%zd)\n",
> i, ret);
> return ret >= 0 ? -EIO : ret;
> @@ -226,7 +227,7 @@ static
> int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
> int i, u32 *part)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
>
> if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
> @@ -236,7 +237,7 @@ int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
> DP_AUX_HDCP_V_PRIME(i), part,
> DRM_HDCP_V_PRIME_PART_LEN);
> if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -256,14 +257,14 @@ static
> bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
> struct intel_connector *connector)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
> u8 bstatus;
>
> ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
> &bstatus, 1);
> if (ret != 1) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read bstatus from DP/AUX failed (%zd)\n", ret);
> return false;
> }
> @@ -275,11 +276,11 @@ static
> int intel_dp_hdcp_get_capability(struct intel_digital_port *dig_port,
> bool *hdcp_capable)
> {
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> + struct intel_display *display = to_intel_display(dig_port);
> ssize_t ret;
> u8 bcaps;
>
> - ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, i915, &bcaps);
> + ret = intel_dp_hdcp_read_bcaps(&dig_port->dp.aux, display, &bcaps);
> if (ret)
> return ret;
>
> @@ -342,7 +343,7 @@ static int
> intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
> u8 *rx_status)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct drm_dp_aux *aux = &dig_port->dp.aux;
> ssize_t ret;
> @@ -351,7 +352,7 @@ intel_dp_hdcp2_read_rx_status(struct intel_connector *connector,
> DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
> HDCP_2_2_DP_RXSTATUS_LEN);
> if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "Read bstatus from DP/AUX failed (%zd)\n", ret);
> return ret >= 0 ? -EIO : ret;
> }
> @@ -397,7 +398,7 @@ static ssize_t
> intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
> const struct hdcp2_dp_msg_data *hdcp2_msg_data)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> struct intel_dp *dp = &dig_port->dp;
> struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> @@ -430,7 +431,7 @@ intel_dp_hdcp2_wait_for_msg(struct intel_connector *connector,
> }
>
> if (ret)
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "msg_id %d, ret %d, timeout(mSec): %d\n",
> hdcp2_msg_data->msg_id, ret, timeout);
>
> @@ -514,8 +515,8 @@ static
> int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
> u8 msg_id, void *buf, size_t size)
> {
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> - struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
> struct drm_dp_aux *aux = &dig_port->dp.aux;
> struct intel_dp *dp = &dig_port->dp;
> struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
> @@ -568,7 +569,7 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
> ret = drm_dp_dpcd_read(aux, offset,
> (void *)byte, len);
> if (ret < 0) {
> - drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
> + drm_dbg_kms(display->drm, "msg_id %d, ret %zd\n",
> msg_id, ret);
> return ret;
> }
> @@ -581,7 +582,8 @@ int intel_dp_hdcp2_read_msg(struct intel_connector *connector,
> if (hdcp2_msg_data->msg_read_timeout > 0) {
> msg_expired = ktime_after(ktime_get_raw(), msg_end);
> if (msg_expired) {
> - drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
> + drm_dbg_kms(display->drm,
> + "msg_id %d, entire msg read timeout(mSec): %d\n",
> msg_id, hdcp2_msg_data->msg_read_timeout);
> return -ETIMEDOUT;
> }
> @@ -696,7 +698,7 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
> bool *hdcp_capable,
> bool *hdcp2_capable)
> {
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> + struct intel_display *display = to_intel_display(connector);
> struct drm_dp_aux *aux;
> u8 bcaps;
> int ret;
> @@ -709,10 +711,10 @@ int intel_dp_hdcp_get_remote_capability(struct intel_connector *connector,
> aux = &connector->port->aux;
> ret = _intel_dp_hdcp2_get_capability(aux, hdcp2_capable);
> if (ret)
> - drm_dbg_kms(&i915->drm,
> + drm_dbg_kms(display->drm,
> "HDCP2 DPCD capability read failed err: %d\n", ret);
>
> - ret = intel_dp_hdcp_read_bcaps(aux, i915, &bcaps);
> + ret = intel_dp_hdcp_read_bcaps(aux, display, &bcaps);
> if (ret)
> return ret;
>
> @@ -745,8 +747,8 @@ static int
> intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
> bool enable)
> {
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> int ret;
>
> @@ -754,7 +756,7 @@ intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
> hdcp->stream_transcoder, enable,
> TRANS_DDI_HDCP_SELECT);
> if (ret)
> - drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
> + drm_err(display->drm, "%s HDCP stream select failed (%d)\n",
> enable ? "Enable" : "Disable", ret);
> return ret;
> }
> @@ -763,8 +765,8 @@ static int
> intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
> bool enable)
> {
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum port port = dig_port->base.port;
> enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> @@ -780,10 +782,10 @@ intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
> return -EINVAL;
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait(i915, HDCP_STATUS(i915, cpu_transcoder, port),
> + if (intel_de_wait(display, HDCP_STATUS(display, cpu_transcoder, port),
> stream_enc_status, enable ? stream_enc_status : 0,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> - drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
> + drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
> transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
> return -ETIMEDOUT;
> }
> @@ -795,8 +797,8 @@ static int
> intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
> bool enable)
> {
> + struct intel_display *display = to_intel_display(connector);
> struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
> - struct drm_i915_private *i915 = to_i915(connector->base.dev);
> struct hdcp_port_data *data = &dig_port->hdcp_port_data;
> struct intel_hdcp *hdcp = &connector->hdcp;
> enum transcoder cpu_transcoder = hdcp->stream_transcoder;
> @@ -804,8 +806,8 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
> enum port port = dig_port->base.port;
> int ret;
>
> - drm_WARN_ON(&i915->drm, enable &&
> - !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
> + drm_WARN_ON(display->drm, enable &&
> + !!(intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port))
> & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
>
> ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
> @@ -813,11 +815,11 @@ intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
> return ret;
>
> /* Wait for encryption confirmation */
> - if (intel_de_wait(i915, HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
> + if (intel_de_wait(display, HDCP2_STREAM_STATUS(display, cpu_transcoder, pipe),
> STREAM_ENCRYPTION_STATUS,
> enable ? STREAM_ENCRYPTION_STATUS : 0,
> HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
> - drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
> + drm_err(display->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
> transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
> return -ETIMEDOUT;
> }
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 06/11] drm/i915/crt: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (4 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 05/11] drm/i915/dp/hdcp: convert " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 15:05 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() " Jani Nikula
` (12 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch CRT code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_crt.c | 207 +++++++++---------
drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
drivers/gpu/drm/i915/display/intel_display.c | 12 +-
.../gpu/drm/i915/display/intel_pch_display.c | 3 +-
4 files changed, 122 insertions(+), 110 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index 8222b1c251db..166501e06046 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -81,12 +81,13 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
return intel_encoder_to_crt(intel_attached_encoder(connector));
}
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
u32 val;
- val = intel_de_read(dev_priv, adpa_reg);
+ val = intel_de_read(display, adpa_reg);
/* asserts want to know the pipe even if the port is disabled */
if (HAS_PCH_CPT(dev_priv))
@@ -100,6 +101,7 @@ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
intel_wakeref_t wakeref;
@@ -110,7 +112,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
if (!wakeref)
return false;
- ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
+ ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
@@ -119,11 +121,11 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
u32 tmp, flags = 0;
- tmp = intel_de_read(dev_priv, crt->adpa_reg);
+ tmp = intel_de_read(display, crt->adpa_reg);
if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
flags |= DRM_MODE_FLAG_PHSYNC;
@@ -168,13 +170,14 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state,
int mode)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crt *crt = intel_encoder_to_crt(encoder);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
u32 adpa;
- if (DISPLAY_VER(dev_priv) >= 5)
+ if (DISPLAY_VER(display) >= 5)
adpa = ADPA_HOTPLUG_BITS;
else
adpa = 0;
@@ -193,7 +196,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
adpa |= ADPA_PIPE_SEL(crtc->pipe);
if (!HAS_PCH_SPLIT(dev_priv))
- intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
+ intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
switch (mode) {
case DRM_MODE_DPMS_ON:
@@ -210,7 +213,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
break;
}
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
}
static void intel_disable_crt(struct intel_atomic_state *state,
@@ -241,9 +244,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -253,6 +257,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *old_crtc_state,
const struct drm_connector_state *old_conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
@@ -272,7 +277,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
hsw_fdi_disable(encoder);
- drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
}
@@ -282,9 +287,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
}
@@ -294,11 +300,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
@@ -312,11 +319,12 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
const struct intel_crtc_state *crtc_state,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(state);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
enum pipe pipe = crtc->pipe;
- drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
+ drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
intel_ddi_enable_transcoder_func(encoder, crtc_state);
@@ -346,9 +354,10 @@ static enum drm_mode_status
intel_crt_mode_valid(struct drm_connector *connector,
struct drm_display_mode *mode)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
+ int max_dotclk = display->cdclk.max_dotclk_freq;
enum drm_mode_status status;
int max_clock;
@@ -367,7 +376,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
* DAC limit supposedly 355 MHz.
*/
max_clock = 270000;
- else if (IS_DISPLAY_VER(dev_priv, 3, 4))
+ else if (IS_DISPLAY_VER(display, 3, 4))
max_clock = 400000;
else
max_clock = 350000;
@@ -428,6 +437,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
@@ -450,7 +460,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
if (HAS_PCH_LPT(dev_priv)) {
/* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"LPT only supports 24bpp\n");
return -EINVAL;
}
@@ -470,6 +480,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -483,36 +494,36 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
crt->force_hotplug_required = false;
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
if (turn_off_dac)
adpa &= ~ADPA_DAC_ENABLE;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv,
+ if (intel_de_wait_for_clear(display,
crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
if (turn_off_dac) {
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
}
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
+ drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
adpa, ret);
return ret;
@@ -520,6 +531,7 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct drm_i915_private *dev_priv = to_i915(dev);
@@ -542,29 +554,29 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
*/
reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
- save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm,
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
+ drm_dbg_kms(display->drm,
"trigger hotplug detect cycle: adpa=0x%x\n", adpa);
adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
+ intel_de_write(display, crt->adpa_reg, adpa);
- if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
+ if (intel_de_wait_for_clear(display, crt->adpa_reg,
ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_TRIGGER");
- intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
+ intel_de_write(display, crt->adpa_reg, save_adpa);
}
/* Check the status to see if both blue and green are on now */
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
ret = true;
else
ret = false;
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
if (reenable_hpd)
@@ -575,6 +587,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
static bool intel_crt_detect_hotplug(struct drm_connector *connector)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_device *dev = connector->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
u32 stat;
@@ -603,18 +616,18 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
CRT_HOTPLUG_FORCE_DETECT,
CRT_HOTPLUG_FORCE_DETECT);
/* wait for FORCE_DETECT to go off */
- if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
+ if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
CRT_HOTPLUG_FORCE_DETECT, 1000))
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"timed out waiting for FORCE_DETECT to go off");
}
- stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
+ stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
ret = true;
/* clear the interrupt we just generated, if any */
- intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
+ intel_de_write(display, PORT_HOTPLUG_STAT(display),
CRT_HOTPLUG_INT_STATUS);
i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
@@ -660,8 +673,7 @@ static int intel_crt_ddc_get_modes(struct drm_connector *connector,
static bool intel_crt_detect_ddc(struct drm_connector *connector)
{
- struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
- struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
+ struct intel_display *display = to_intel_display(connector->dev);
const struct drm_edid *drm_edid;
bool ret = false;
@@ -674,15 +686,15 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
* have to check the EDID input spec of the attached device.
*/
if (drm_edid_is_digital(drm_edid)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via DDC:0x50 [EDID]\n");
ret = true;
}
} else {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via DDC:0x50 [no valid EDID found]\n");
}
@@ -695,8 +707,6 @@ static enum drm_connector_status
intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
{
struct intel_display *display = to_intel_display(&crt->base);
- struct drm_device *dev = crt->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
enum transcoder cpu_transcoder = (enum transcoder)pipe;
u32 save_bclrpat;
u32 save_vtotal;
@@ -707,14 +717,14 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
u8 st00;
enum drm_connector_status status;
- drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
+ drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
- save_bclrpat = intel_de_read(dev_priv,
- BCLRPAT(dev_priv, cpu_transcoder));
- save_vtotal = intel_de_read(dev_priv,
- TRANS_VTOTAL(dev_priv, cpu_transcoder));
- vblank = intel_de_read(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder));
+ save_bclrpat = intel_de_read(display,
+ BCLRPAT(display, cpu_transcoder));
+ save_vtotal = intel_de_read(display,
+ TRANS_VTOTAL(display, cpu_transcoder));
+ vblank = intel_de_read(display,
+ TRANS_VBLANK(display, cpu_transcoder));
vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
@@ -723,25 +733,25 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
/* Set the border color to purple. */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
- if (DISPLAY_VER(dev_priv) != 2) {
- u32 transconf = intel_de_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ if (DISPLAY_VER(display) != 2) {
+ u32 transconf = intel_de_read(display,
+ TRANSCONF(display, cpu_transcoder));
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf | TRANSCONF_FORCE_BORDER);
- intel_de_posting_read(dev_priv,
- TRANSCONF(dev_priv, cpu_transcoder));
+ intel_de_posting_read(display,
+ TRANSCONF(display, cpu_transcoder));
/* Wait for next Vblank to substitue
* border color for Color info */
intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
status = ((st00 & (1 << 4)) != 0) ?
connector_status_connected :
connector_status_disconnected;
- intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
+ intel_de_write(display, TRANSCONF(display, cpu_transcoder),
transconf);
} else {
bool restore_vblank = false;
@@ -752,13 +762,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
* Yes, this will flicker
*/
if (vblank_start <= vactive && vblank_end >= vtotal) {
- u32 vsync = intel_de_read(dev_priv,
- TRANS_VSYNC(dev_priv, cpu_transcoder));
+ u32 vsync = intel_de_read(display,
+ TRANS_VSYNC(display, cpu_transcoder));
u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
vblank_start = vsync_start;
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
VBLANK_START(vblank_start - 1) |
VBLANK_END(vblank_end - 1));
restore_vblank = true;
@@ -772,9 +782,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
/*
* Wait for the border to be displayed
*/
- while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
+ while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
;
- while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
+ while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
;
/*
* Watch ST00 for an entire scanline
@@ -784,15 +794,15 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
do {
count++;
/* Read the ST00 VGA status register */
- st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
+ st00 = intel_de_read8(display, _VGA_MSR_WRITE);
if (st00 & (1 << 4))
detect++;
- } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
+ } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
/* restore vblank if necessary */
if (restore_vblank)
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, cpu_transcoder),
+ intel_de_write(display,
+ TRANS_VBLANK(display, cpu_transcoder),
vblank);
/*
* If more than 3/4 of the scanline detected a monitor,
@@ -806,7 +816,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
}
/* Restore previous settings */
- intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
+ intel_de_write(display, BCLRPAT(display, cpu_transcoder),
save_bclrpat);
return status;
@@ -843,6 +853,7 @@ intel_crt_detect(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx,
bool force)
{
+ struct intel_display *display = to_intel_display(connector->dev);
struct drm_i915_private *dev_priv = to_i915(connector->dev);
struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
struct intel_encoder *intel_encoder = &crt->base;
@@ -850,7 +861,7 @@ intel_crt_detect(struct drm_connector *connector,
intel_wakeref_t wakeref;
int status;
- drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
+ drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
connector->base.id, connector->name,
force);
@@ -860,7 +871,7 @@ intel_crt_detect(struct drm_connector *connector,
if (!intel_display_driver_check_access(dev_priv))
return connector->status;
- if (dev_priv->display.params.load_detect_test) {
+ if (display->params.load_detect_test) {
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
goto load_detect;
@@ -873,18 +884,18 @@ intel_crt_detect(struct drm_connector *connector,
wakeref = intel_display_power_get(dev_priv,
intel_encoder->power_domain);
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
/* We can not rely on the HPD pin always being correctly wired
* up, for example many KVM do not pass it through, and so
* only trust an assertion that the monitor is connected.
*/
if (intel_crt_detect_hotplug(connector)) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT detected via hotplug\n");
status = connector_status_connected;
goto out;
} else
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"CRT not detected via hotplug\n");
}
@@ -897,7 +908,7 @@ intel_crt_detect(struct drm_connector *connector,
* broken monitor (without edid) to work behind a broken kvm (that fails
* to have the right resistors for HP detection) needs to fix this up.
* For now just bail out. */
- if (I915_HAS_HOTPLUG(dev_priv)) {
+ if (I915_HAS_HOTPLUG(display)) {
status = connector_status_disconnected;
goto out;
}
@@ -917,10 +928,10 @@ intel_crt_detect(struct drm_connector *connector,
} else {
if (intel_crt_detect_ddc(connector))
status = connector_status_connected;
- else if (DISPLAY_VER(dev_priv) < 4)
+ else if (DISPLAY_VER(display) < 4)
status = intel_crt_load_detect(crt,
to_intel_crtc(connector->state->crtc)->pipe);
- else if (dev_priv->display.params.load_detect_test)
+ else if (display->params.load_detect_test)
status = connector_status_disconnected;
else
status = connector_status_unknown;
@@ -966,19 +977,19 @@ static int intel_crt_get_modes(struct drm_connector *connector)
void intel_crt_reset(struct drm_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->dev);
+ struct intel_display *display = to_intel_display(encoder->dev);
struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
- if (DISPLAY_VER(dev_priv) >= 5) {
+ if (DISPLAY_VER(display) >= 5) {
u32 adpa;
- adpa = intel_de_read(dev_priv, crt->adpa_reg);
+ adpa = intel_de_read(display, crt->adpa_reg);
adpa &= ~ADPA_CRT_HOTPLUG_MASK;
adpa |= ADPA_HOTPLUG_BITS;
- intel_de_write(dev_priv, crt->adpa_reg, adpa);
- intel_de_posting_read(dev_priv, crt->adpa_reg);
+ intel_de_write(display, crt->adpa_reg, adpa);
+ intel_de_posting_read(display, crt->adpa_reg);
- drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
+ drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
crt->force_hotplug_required = true;
}
@@ -1008,9 +1019,9 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
.destroy = intel_encoder_destroy,
};
-void intel_crt_init(struct drm_i915_private *dev_priv)
+void intel_crt_init(struct intel_display *display)
{
- struct intel_display *display = &dev_priv->display;
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct drm_connector *connector;
struct intel_crt *crt;
struct intel_connector *intel_connector;
@@ -1025,7 +1036,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
adpa_reg = ADPA;
- adpa = intel_de_read(dev_priv, adpa_reg);
+ adpa = intel_de_read(display, adpa_reg);
if ((adpa & ADPA_DAC_ENABLE) == 0) {
/*
* On some machines (some IVB at least) CRT can be
@@ -1035,11 +1046,11 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
* take. So the only way to tell is attempt to enable
* it and see what happens.
*/
- intel_de_write(dev_priv, adpa_reg,
+ intel_de_write(display, adpa_reg,
adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
- if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
+ if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
return;
- intel_de_write(dev_priv, adpa_reg, adpa);
+ intel_de_write(display, adpa_reg, adpa);
}
crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
@@ -1052,16 +1063,16 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
return;
}
- ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
+ ddc_pin = display->vbt.crt_ddc_pin;
connector = &intel_connector->base;
crt->connector = intel_connector;
- drm_connector_init_with_ddc(&dev_priv->drm, connector,
+ drm_connector_init_with_ddc(display->drm, connector,
&intel_crt_connector_funcs,
DRM_MODE_CONNECTOR_VGA,
intel_gmbus_get_adapter(display, ddc_pin));
- drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
+ drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
DRM_MODE_ENCODER_DAC, "CRT");
intel_connector_attach_encoder(intel_connector, &crt->base);
@@ -1073,14 +1084,14 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
else
crt->base.pipe_mask = ~0;
- if (DISPLAY_VER(dev_priv) != 2)
+ if (DISPLAY_VER(display) != 2)
connector->interlace_allowed = true;
crt->adpa_reg = adpa_reg;
crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
- if (I915_HAS_HOTPLUG(dev_priv) &&
+ if (I915_HAS_HOTPLUG(display) &&
!dmi_check_system(intel_spurious_crt_detect)) {
crt->base.hpd_pin = HPD_CRT;
crt->base.hotplug = intel_encoder_hotplug;
@@ -1090,7 +1101,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
}
intel_connector->base.polled = intel_connector->polled;
- if (HAS_DDI(dev_priv)) {
+ if (HAS_DDI(display)) {
assert_port_valid(dev_priv, PORT_E);
crt->base.port = PORT_E;
@@ -1134,7 +1145,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
FDI_RX_LINK_REVERSAL_OVERRIDE;
- dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
+ display->fdi.rx_config = intel_de_read(display,
FDI_RX_CTL(PIPE_A)) & fdi_config;
}
diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
index fe7690c2b948..e0abfe96a3d2 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.h
+++ b/drivers/gpu/drm/i915/display/intel_crt.h
@@ -10,20 +10,20 @@
enum pipe;
struct drm_encoder;
-struct drm_i915_private;
+struct intel_display;
#ifdef I915
-bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe);
-void intel_crt_init(struct drm_i915_private *dev_priv);
+void intel_crt_init(struct intel_display *display);
void intel_crt_reset(struct drm_encoder *encoder);
#else
-static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
+static inline bool intel_crt_port_enabled(struct intel_display *display,
i915_reg_t adpa_reg, enum pipe *pipe)
{
return false;
}
-static inline void intel_crt_init(struct drm_i915_private *dev_priv)
+static inline void intel_crt_init(struct intel_display *display)
{
}
static inline void intel_crt_reset(struct drm_encoder *encoder)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index c19f01b63936..2479ca0a02d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8147,7 +8147,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (HAS_DDI(dev_priv)) {
if (intel_ddi_crt_present(dev_priv))
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_bios_for_each_encoder(display, intel_ddi_init);
@@ -8162,7 +8162,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
* incorrect sharing of the PPS.
*/
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
@@ -8193,7 +8193,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
bool has_edp, has_port;
if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
/*
* The DP_DETECTED bit is the latched state of the DDC
@@ -8239,14 +8239,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
vlv_dsi_init(dev_priv);
} else if (IS_PINEVIEW(dev_priv)) {
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
} else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
bool found = false;
if (IS_MOBILE(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
@@ -8288,7 +8288,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
if (IS_I85X(dev_priv))
intel_lvds_init(dev_priv);
- intel_crt_init(dev_priv);
+ intel_crt_init(display);
intel_dvo_init(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
index f13ab680c2cf..17739a51fe54 100644
--- a/drivers/gpu/drm/i915/display/intel_pch_display.c
+++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
@@ -76,6 +76,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
enum pipe pipe)
{
+ struct intel_display *display = &dev_priv->display;
enum pipe port_pipe;
assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
@@ -83,7 +84,7 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
I915_STATE_WARN(dev_priv,
- intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
+ intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
"PCH VGA enabled on transcoder %c, should be disabled\n",
pipe_name(pipe));
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 06/11] drm/i915/crt: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 06/11] drm/i915/crt: " Jani Nikula
@ 2024-10-23 15:05 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 15:05 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:23PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch CRT code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_crt.c | 207 +++++++++---------
> drivers/gpu/drm/i915/display/intel_crt.h | 10 +-
> drivers/gpu/drm/i915/display/intel_display.c | 12 +-
> .../gpu/drm/i915/display/intel_pch_display.c | 3 +-
> 4 files changed, 122 insertions(+), 110 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index 8222b1c251db..166501e06046 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -81,12 +81,13 @@ static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
> return intel_encoder_to_crt(intel_attached_encoder(connector));
> }
>
> -bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> +bool intel_crt_port_enabled(struct intel_display *display,
> i915_reg_t adpa_reg, enum pipe *pipe)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> u32 val;
>
> - val = intel_de_read(dev_priv, adpa_reg);
> + val = intel_de_read(display, adpa_reg);
>
> /* asserts want to know the pipe even if the port is disabled */
> if (HAS_PCH_CPT(dev_priv))
> @@ -100,6 +101,7 @@ bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> enum pipe *pipe)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> intel_wakeref_t wakeref;
> @@ -110,7 +112,7 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
> if (!wakeref)
> return false;
>
> - ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
> + ret = intel_crt_port_enabled(display, crt->adpa_reg, pipe);
>
> intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
>
> @@ -119,11 +121,11 @@ static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
>
> static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> u32 tmp, flags = 0;
>
> - tmp = intel_de_read(dev_priv, crt->adpa_reg);
> + tmp = intel_de_read(display, crt->adpa_reg);
>
> if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
> flags |= DRM_MODE_FLAG_PHSYNC;
> @@ -168,13 +170,14 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state,
> int mode)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crt *crt = intel_encoder_to_crt(encoder);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
> u32 adpa;
>
> - if (DISPLAY_VER(dev_priv) >= 5)
> + if (DISPLAY_VER(display) >= 5)
> adpa = ADPA_HOTPLUG_BITS;
> else
> adpa = 0;
> @@ -193,7 +196,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> adpa |= ADPA_PIPE_SEL(crtc->pipe);
>
> if (!HAS_PCH_SPLIT(dev_priv))
> - intel_de_write(dev_priv, BCLRPAT(dev_priv, crtc->pipe), 0);
> + intel_de_write(display, BCLRPAT(display, crtc->pipe), 0);
>
> switch (mode) {
> case DRM_MODE_DPMS_ON:
> @@ -210,7 +213,7 @@ static void intel_crt_set_dpms(struct intel_encoder *encoder,
> break;
> }
>
> - intel_de_write(dev_priv, crt->adpa_reg, adpa);
> + intel_de_write(display, crt->adpa_reg, adpa);
> }
>
> static void intel_disable_crt(struct intel_atomic_state *state,
> @@ -241,9 +244,10 @@ static void hsw_disable_crt(struct intel_atomic_state *state,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state *old_conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
> + drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
>
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> }
> @@ -253,6 +257,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
> const struct intel_crtc_state *old_crtc_state,
> const struct drm_connector_state *old_conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> @@ -272,7 +277,7 @@ static void hsw_post_disable_crt(struct intel_atomic_state *state,
>
> hsw_fdi_disable(encoder);
>
> - drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
> + drm_WARN_ON(display->drm, !old_crtc_state->has_pch_encoder);
>
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
> }
> @@ -282,9 +287,10 @@ static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> - drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
> + drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
>
> intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
> }
> @@ -294,11 +300,12 @@ static void hsw_pre_enable_crt(struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> - drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
> + drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
>
> intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
>
> @@ -312,11 +319,12 @@ static void hsw_enable_crt(struct intel_atomic_state *state,
> const struct intel_crtc_state *crtc_state,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(state);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> enum pipe pipe = crtc->pipe;
>
> - drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
> + drm_WARN_ON(display->drm, !crtc_state->has_pch_encoder);
>
> intel_ddi_enable_transcoder_func(encoder, crtc_state);
>
> @@ -346,9 +354,10 @@ static enum drm_mode_status
> intel_crt_mode_valid(struct drm_connector *connector,
> struct drm_display_mode *mode)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> - int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
> + int max_dotclk = display->cdclk.max_dotclk_freq;
> enum drm_mode_status status;
> int max_clock;
>
> @@ -367,7 +376,7 @@ intel_crt_mode_valid(struct drm_connector *connector,
> * DAC limit supposedly 355 MHz.
> */
> max_clock = 270000;
> - else if (IS_DISPLAY_VER(dev_priv, 3, 4))
> + else if (IS_DISPLAY_VER(display, 3, 4))
> max_clock = 400000;
> else
> max_clock = 350000;
> @@ -428,6 +437,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> @@ -450,7 +460,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> if (HAS_PCH_LPT(dev_priv)) {
> /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
> if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "LPT only supports 24bpp\n");
> return -EINVAL;
> }
> @@ -470,6 +480,7 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
>
> static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_device *dev = connector->dev;
> struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -483,36 +494,36 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
>
> crt->force_hotplug_required = false;
>
> - save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
> - drm_dbg_kms(&dev_priv->drm,
> + save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
> + drm_dbg_kms(display->drm,
> "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>
> adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
> if (turn_off_dac)
> adpa &= ~ADPA_DAC_ENABLE;
>
> - intel_de_write(dev_priv, crt->adpa_reg, adpa);
> + intel_de_write(display, crt->adpa_reg, adpa);
>
> - if (intel_de_wait_for_clear(dev_priv,
> + if (intel_de_wait_for_clear(display,
> crt->adpa_reg,
> ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
> 1000))
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_TRIGGER");
>
> if (turn_off_dac) {
> - intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
> - intel_de_posting_read(dev_priv, crt->adpa_reg);
> + intel_de_write(display, crt->adpa_reg, save_adpa);
> + intel_de_posting_read(display, crt->adpa_reg);
> }
> }
>
> /* Check the status to see if both blue and green are on now */
> - adpa = intel_de_read(dev_priv, crt->adpa_reg);
> + adpa = intel_de_read(display, crt->adpa_reg);
> if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
> ret = true;
> else
> ret = false;
> - drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
> + drm_dbg_kms(display->drm, "ironlake hotplug adpa=0x%x, result %d\n",
> adpa, ret);
>
> return ret;
> @@ -520,6 +531,7 @@ static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
>
> static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_device *dev = connector->dev;
> struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
> struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -542,29 +554,29 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
> */
> reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
>
> - save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
> - drm_dbg_kms(&dev_priv->drm,
> + save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
> + drm_dbg_kms(display->drm,
> "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
>
> adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
>
> - intel_de_write(dev_priv, crt->adpa_reg, adpa);
> + intel_de_write(display, crt->adpa_reg, adpa);
>
> - if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
> + if (intel_de_wait_for_clear(display, crt->adpa_reg,
> ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_TRIGGER");
> - intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
> + intel_de_write(display, crt->adpa_reg, save_adpa);
> }
>
> /* Check the status to see if both blue and green are on now */
> - adpa = intel_de_read(dev_priv, crt->adpa_reg);
> + adpa = intel_de_read(display, crt->adpa_reg);
> if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
> ret = true;
> else
> ret = false;
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
>
> if (reenable_hpd)
> @@ -575,6 +587,7 @@ static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
>
> static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_device *dev = connector->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> u32 stat;
> @@ -603,18 +616,18 @@ static bool intel_crt_detect_hotplug(struct drm_connector *connector)
> CRT_HOTPLUG_FORCE_DETECT,
> CRT_HOTPLUG_FORCE_DETECT);
> /* wait for FORCE_DETECT to go off */
> - if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN(dev_priv),
> + if (intel_de_wait_for_clear(display, PORT_HOTPLUG_EN(display),
> CRT_HOTPLUG_FORCE_DETECT, 1000))
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "timed out waiting for FORCE_DETECT to go off");
> }
>
> - stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT(dev_priv));
> + stat = intel_de_read(display, PORT_HOTPLUG_STAT(display));
> if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
> ret = true;
>
> /* clear the interrupt we just generated, if any */
> - intel_de_write(dev_priv, PORT_HOTPLUG_STAT(dev_priv),
> + intel_de_write(display, PORT_HOTPLUG_STAT(display),
> CRT_HOTPLUG_INT_STATUS);
>
> i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
> @@ -660,8 +673,7 @@ static int intel_crt_ddc_get_modes(struct drm_connector *connector,
>
> static bool intel_crt_detect_ddc(struct drm_connector *connector)
> {
> - struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
> - struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
> + struct intel_display *display = to_intel_display(connector->dev);
> const struct drm_edid *drm_edid;
> bool ret = false;
>
> @@ -674,15 +686,15 @@ static bool intel_crt_detect_ddc(struct drm_connector *connector)
> * have to check the EDID input spec of the attached device.
> */
> if (drm_edid_is_digital(drm_edid)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
> } else {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "CRT detected via DDC:0x50 [EDID]\n");
> ret = true;
> }
> } else {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "CRT not detected via DDC:0x50 [no valid EDID found]\n");
> }
>
> @@ -695,8 +707,6 @@ static enum drm_connector_status
> intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> {
> struct intel_display *display = to_intel_display(&crt->base);
> - struct drm_device *dev = crt->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> enum transcoder cpu_transcoder = (enum transcoder)pipe;
> u32 save_bclrpat;
> u32 save_vtotal;
> @@ -707,14 +717,14 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> u8 st00;
> enum drm_connector_status status;
>
> - drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
> + drm_dbg_kms(display->drm, "starting load-detect on CRT\n");
>
> - save_bclrpat = intel_de_read(dev_priv,
> - BCLRPAT(dev_priv, cpu_transcoder));
> - save_vtotal = intel_de_read(dev_priv,
> - TRANS_VTOTAL(dev_priv, cpu_transcoder));
> - vblank = intel_de_read(dev_priv,
> - TRANS_VBLANK(dev_priv, cpu_transcoder));
> + save_bclrpat = intel_de_read(display,
> + BCLRPAT(display, cpu_transcoder));
> + save_vtotal = intel_de_read(display,
> + TRANS_VTOTAL(display, cpu_transcoder));
> + vblank = intel_de_read(display,
> + TRANS_VBLANK(display, cpu_transcoder));
>
> vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
> vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
> @@ -723,25 +733,25 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
>
> /* Set the border color to purple. */
> - intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder), 0x500050);
> + intel_de_write(display, BCLRPAT(display, cpu_transcoder), 0x500050);
>
> - if (DISPLAY_VER(dev_priv) != 2) {
> - u32 transconf = intel_de_read(dev_priv,
> - TRANSCONF(dev_priv, cpu_transcoder));
> + if (DISPLAY_VER(display) != 2) {
> + u32 transconf = intel_de_read(display,
> + TRANSCONF(display, cpu_transcoder));
>
> - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANSCONF(display, cpu_transcoder),
> transconf | TRANSCONF_FORCE_BORDER);
> - intel_de_posting_read(dev_priv,
> - TRANSCONF(dev_priv, cpu_transcoder));
> + intel_de_posting_read(display,
> + TRANSCONF(display, cpu_transcoder));
> /* Wait for next Vblank to substitue
> * border color for Color info */
> intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(display, pipe));
> - st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
> + st00 = intel_de_read8(display, _VGA_MSR_WRITE);
> status = ((st00 & (1 << 4)) != 0) ?
> connector_status_connected :
> connector_status_disconnected;
>
> - intel_de_write(dev_priv, TRANSCONF(dev_priv, cpu_transcoder),
> + intel_de_write(display, TRANSCONF(display, cpu_transcoder),
> transconf);
> } else {
> bool restore_vblank = false;
> @@ -752,13 +762,13 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> * Yes, this will flicker
> */
> if (vblank_start <= vactive && vblank_end >= vtotal) {
> - u32 vsync = intel_de_read(dev_priv,
> - TRANS_VSYNC(dev_priv, cpu_transcoder));
> + u32 vsync = intel_de_read(display,
> + TRANS_VSYNC(display, cpu_transcoder));
> u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
>
> vblank_start = vsync_start;
> - intel_de_write(dev_priv,
> - TRANS_VBLANK(dev_priv, cpu_transcoder),
> + intel_de_write(display,
> + TRANS_VBLANK(display, cpu_transcoder),
> VBLANK_START(vblank_start - 1) |
> VBLANK_END(vblank_end - 1));
> restore_vblank = true;
> @@ -772,9 +782,9 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> /*
> * Wait for the border to be displayed
> */
> - while (intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) >= vactive)
> + while (intel_de_read(display, PIPEDSL(display, pipe)) >= vactive)
> ;
> - while ((dsl = intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe))) <= vsample)
> + while ((dsl = intel_de_read(display, PIPEDSL(display, pipe))) <= vsample)
> ;
> /*
> * Watch ST00 for an entire scanline
> @@ -784,15 +794,15 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> do {
> count++;
> /* Read the ST00 VGA status register */
> - st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
> + st00 = intel_de_read8(display, _VGA_MSR_WRITE);
> if (st00 & (1 << 4))
> detect++;
> - } while ((intel_de_read(dev_priv, PIPEDSL(dev_priv, pipe)) == dsl));
> + } while ((intel_de_read(display, PIPEDSL(display, pipe)) == dsl));
>
> /* restore vblank if necessary */
> if (restore_vblank)
> - intel_de_write(dev_priv,
> - TRANS_VBLANK(dev_priv, cpu_transcoder),
> + intel_de_write(display,
> + TRANS_VBLANK(display, cpu_transcoder),
> vblank);
> /*
> * If more than 3/4 of the scanline detected a monitor,
> @@ -806,7 +816,7 @@ intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
> }
>
> /* Restore previous settings */
> - intel_de_write(dev_priv, BCLRPAT(dev_priv, cpu_transcoder),
> + intel_de_write(display, BCLRPAT(display, cpu_transcoder),
> save_bclrpat);
>
> return status;
> @@ -843,6 +853,7 @@ intel_crt_detect(struct drm_connector *connector,
> struct drm_modeset_acquire_ctx *ctx,
> bool force)
> {
> + struct intel_display *display = to_intel_display(connector->dev);
> struct drm_i915_private *dev_priv = to_i915(connector->dev);
> struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
> struct intel_encoder *intel_encoder = &crt->base;
> @@ -850,7 +861,7 @@ intel_crt_detect(struct drm_connector *connector,
> intel_wakeref_t wakeref;
> int status;
>
> - drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
> + drm_dbg_kms(display->drm, "[CONNECTOR:%d:%s] force=%d\n",
> connector->base.id, connector->name,
> force);
>
> @@ -860,7 +871,7 @@ intel_crt_detect(struct drm_connector *connector,
> if (!intel_display_driver_check_access(dev_priv))
> return connector->status;
>
> - if (dev_priv->display.params.load_detect_test) {
> + if (display->params.load_detect_test) {
> wakeref = intel_display_power_get(dev_priv,
> intel_encoder->power_domain);
> goto load_detect;
> @@ -873,18 +884,18 @@ intel_crt_detect(struct drm_connector *connector,
> wakeref = intel_display_power_get(dev_priv,
> intel_encoder->power_domain);
>
> - if (I915_HAS_HOTPLUG(dev_priv)) {
> + if (I915_HAS_HOTPLUG(display)) {
> /* We can not rely on the HPD pin always being correctly wired
> * up, for example many KVM do not pass it through, and so
> * only trust an assertion that the monitor is connected.
> */
> if (intel_crt_detect_hotplug(connector)) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "CRT detected via hotplug\n");
> status = connector_status_connected;
> goto out;
> } else
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "CRT not detected via hotplug\n");
> }
>
> @@ -897,7 +908,7 @@ intel_crt_detect(struct drm_connector *connector,
> * broken monitor (without edid) to work behind a broken kvm (that fails
> * to have the right resistors for HP detection) needs to fix this up.
> * For now just bail out. */
> - if (I915_HAS_HOTPLUG(dev_priv)) {
> + if (I915_HAS_HOTPLUG(display)) {
> status = connector_status_disconnected;
> goto out;
> }
> @@ -917,10 +928,10 @@ intel_crt_detect(struct drm_connector *connector,
> } else {
> if (intel_crt_detect_ddc(connector))
> status = connector_status_connected;
> - else if (DISPLAY_VER(dev_priv) < 4)
> + else if (DISPLAY_VER(display) < 4)
> status = intel_crt_load_detect(crt,
> to_intel_crtc(connector->state->crtc)->pipe);
> - else if (dev_priv->display.params.load_detect_test)
> + else if (display->params.load_detect_test)
> status = connector_status_disconnected;
> else
> status = connector_status_unknown;
> @@ -966,19 +977,19 @@ static int intel_crt_get_modes(struct drm_connector *connector)
>
> void intel_crt_reset(struct drm_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->dev);
> + struct intel_display *display = to_intel_display(encoder->dev);
> struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
>
> - if (DISPLAY_VER(dev_priv) >= 5) {
> + if (DISPLAY_VER(display) >= 5) {
> u32 adpa;
>
> - adpa = intel_de_read(dev_priv, crt->adpa_reg);
> + adpa = intel_de_read(display, crt->adpa_reg);
> adpa &= ~ADPA_CRT_HOTPLUG_MASK;
> adpa |= ADPA_HOTPLUG_BITS;
> - intel_de_write(dev_priv, crt->adpa_reg, adpa);
> - intel_de_posting_read(dev_priv, crt->adpa_reg);
> + intel_de_write(display, crt->adpa_reg, adpa);
> + intel_de_posting_read(display, crt->adpa_reg);
>
> - drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
> + drm_dbg_kms(display->drm, "crt adpa set to 0x%x\n", adpa);
> crt->force_hotplug_required = true;
> }
>
> @@ -1008,9 +1019,9 @@ static const struct drm_encoder_funcs intel_crt_enc_funcs = {
> .destroy = intel_encoder_destroy,
> };
>
> -void intel_crt_init(struct drm_i915_private *dev_priv)
> +void intel_crt_init(struct intel_display *display)
> {
> - struct intel_display *display = &dev_priv->display;
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct drm_connector *connector;
> struct intel_crt *crt;
> struct intel_connector *intel_connector;
> @@ -1025,7 +1036,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> else
> adpa_reg = ADPA;
>
> - adpa = intel_de_read(dev_priv, adpa_reg);
> + adpa = intel_de_read(display, adpa_reg);
> if ((adpa & ADPA_DAC_ENABLE) == 0) {
> /*
> * On some machines (some IVB at least) CRT can be
> @@ -1035,11 +1046,11 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> * take. So the only way to tell is attempt to enable
> * it and see what happens.
> */
> - intel_de_write(dev_priv, adpa_reg,
> + intel_de_write(display, adpa_reg,
> adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
> - if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
> + if ((intel_de_read(display, adpa_reg) & ADPA_DAC_ENABLE) == 0)
> return;
> - intel_de_write(dev_priv, adpa_reg, adpa);
> + intel_de_write(display, adpa_reg, adpa);
> }
>
> crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
> @@ -1052,16 +1063,16 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> return;
> }
>
> - ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
> + ddc_pin = display->vbt.crt_ddc_pin;
>
> connector = &intel_connector->base;
> crt->connector = intel_connector;
> - drm_connector_init_with_ddc(&dev_priv->drm, connector,
> + drm_connector_init_with_ddc(display->drm, connector,
> &intel_crt_connector_funcs,
> DRM_MODE_CONNECTOR_VGA,
> intel_gmbus_get_adapter(display, ddc_pin));
>
> - drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
> + drm_encoder_init(display->drm, &crt->base.base, &intel_crt_enc_funcs,
> DRM_MODE_ENCODER_DAC, "CRT");
>
> intel_connector_attach_encoder(intel_connector, &crt->base);
> @@ -1073,14 +1084,14 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> else
> crt->base.pipe_mask = ~0;
>
> - if (DISPLAY_VER(dev_priv) != 2)
> + if (DISPLAY_VER(display) != 2)
> connector->interlace_allowed = true;
>
> crt->adpa_reg = adpa_reg;
>
> crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
>
> - if (I915_HAS_HOTPLUG(dev_priv) &&
> + if (I915_HAS_HOTPLUG(display) &&
> !dmi_check_system(intel_spurious_crt_detect)) {
> crt->base.hpd_pin = HPD_CRT;
> crt->base.hotplug = intel_encoder_hotplug;
> @@ -1090,7 +1101,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> }
> intel_connector->base.polled = intel_connector->polled;
>
> - if (HAS_DDI(dev_priv)) {
> + if (HAS_DDI(display)) {
> assert_port_valid(dev_priv, PORT_E);
>
> crt->base.port = PORT_E;
> @@ -1134,7 +1145,7 @@ void intel_crt_init(struct drm_i915_private *dev_priv)
> u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
> FDI_RX_LINK_REVERSAL_OVERRIDE;
>
> - dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
> + display->fdi.rx_config = intel_de_read(display,
> FDI_RX_CTL(PIPE_A)) & fdi_config;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.h b/drivers/gpu/drm/i915/display/intel_crt.h
> index fe7690c2b948..e0abfe96a3d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.h
> +++ b/drivers/gpu/drm/i915/display/intel_crt.h
> @@ -10,20 +10,20 @@
>
> enum pipe;
> struct drm_encoder;
> -struct drm_i915_private;
> +struct intel_display;
>
> #ifdef I915
> -bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> +bool intel_crt_port_enabled(struct intel_display *display,
> i915_reg_t adpa_reg, enum pipe *pipe);
> -void intel_crt_init(struct drm_i915_private *dev_priv);
> +void intel_crt_init(struct intel_display *display);
> void intel_crt_reset(struct drm_encoder *encoder);
> #else
> -static inline bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
> +static inline bool intel_crt_port_enabled(struct intel_display *display,
> i915_reg_t adpa_reg, enum pipe *pipe)
> {
> return false;
> }
> -static inline void intel_crt_init(struct drm_i915_private *dev_priv)
> +static inline void intel_crt_init(struct intel_display *display)
> {
> }
> static inline void intel_crt_reset(struct drm_encoder *encoder)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index c19f01b63936..2479ca0a02d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8147,7 +8147,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
>
> if (HAS_DDI(dev_priv)) {
> if (intel_ddi_crt_present(dev_priv))
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
>
> intel_bios_for_each_encoder(display, intel_ddi_init);
>
> @@ -8162,7 +8162,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> * incorrect sharing of the PPS.
> */
> intel_lvds_init(dev_priv);
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
>
> dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
>
> @@ -8193,7 +8193,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> bool has_edp, has_port;
>
> if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
>
> /*
> * The DP_DETECTED bit is the latched state of the DDC
> @@ -8239,14 +8239,14 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> vlv_dsi_init(dev_priv);
> } else if (IS_PINEVIEW(dev_priv)) {
> intel_lvds_init(dev_priv);
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
> } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
> bool found = false;
>
> if (IS_MOBILE(dev_priv))
> intel_lvds_init(dev_priv);
>
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
>
> if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
> drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
> @@ -8288,7 +8288,7 @@ void intel_setup_outputs(struct drm_i915_private *dev_priv)
> if (IS_I85X(dev_priv))
> intel_lvds_init(dev_priv);
>
> - intel_crt_init(dev_priv);
> + intel_crt_init(display);
> intel_dvo_init(dev_priv);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_pch_display.c b/drivers/gpu/drm/i915/display/intel_pch_display.c
> index f13ab680c2cf..17739a51fe54 100644
> --- a/drivers/gpu/drm/i915/display/intel_pch_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_pch_display.c
> @@ -76,6 +76,7 @@ static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
> static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> enum pipe pipe)
> {
> + struct intel_display *display = &dev_priv->display;
> enum pipe port_pipe;
>
> assert_pch_dp_disabled(dev_priv, pipe, PORT_B, PCH_DP_B);
> @@ -83,7 +84,7 @@ static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
> assert_pch_dp_disabled(dev_priv, pipe, PORT_D, PCH_DP_D);
>
> I915_STATE_WARN(dev_priv,
> - intel_crt_port_enabled(dev_priv, PCH_ADPA, &port_pipe) && port_pipe == pipe,
> + intel_crt_port_enabled(display, PCH_ADPA, &port_pipe) && port_pipe == pipe,
> "PCH VGA enabled on transcoder %c, should be disabled\n",
> pipe_name(pipe));
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (5 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 06/11] drm/i915/crt: " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 17:18 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() " Jani Nikula
` (11 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch vlv_wait_port_ready() over to
it. The main motivation to do just one function is to stop passing i915
to intel_de_wait(), so its generic wrapper can be removed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3 +--
drivers/gpu/drm/i915/display/g4x_hdmi.c | 9 ++++-----
drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++------
drivers/gpu/drm/i915/display/intel_display.h | 2 +-
4 files changed, 12 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 440fb3002f28..a22781d21110 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -706,8 +706,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
if (IS_CHERRYVIEW(dev_priv))
lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
- vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
- lane_mask);
+ vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
}
intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 46f23bdb4c17..d1a7d0d57c6b 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -480,8 +480,8 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
vlv_phy_pre_encoder_enable(encoder, pipe_config);
@@ -496,7 +496,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
g4x_hdmi_enable_port(encoder, pipe_config);
- vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+ vlv_wait_port_ready(display, dig_port, 0x0);
}
static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
@@ -557,9 +557,8 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
const struct intel_crtc_state *pipe_config,
const struct drm_connector_state *conn_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
- struct drm_device *dev = encoder->base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
chv_phy_pre_encoder_enable(encoder, pipe_config);
@@ -573,7 +572,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
g4x_hdmi_enable_port(encoder, pipe_config);
- vlv_wait_port_ready(dev_priv, dig_port, 0x0);
+ vlv_wait_port_ready(display, dig_port, 0x0);
/* Second common lane will stay alive on its own now */
chv_phy_release_cl2_override(encoder);
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 2479ca0a02d9..53e81b0030d4 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -474,7 +474,7 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
assert_plane_disabled(plane);
}
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
struct intel_digital_port *dig_port,
unsigned int expected_mask)
{
@@ -487,11 +487,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
fallthrough;
case PORT_B:
port_mask = DPLL_PORTB_READY_MASK;
- dpll_reg = DPLL(dev_priv, 0);
+ dpll_reg = DPLL(display, 0);
break;
case PORT_C:
port_mask = DPLL_PORTC_READY_MASK;
- dpll_reg = DPLL(dev_priv, 0);
+ dpll_reg = DPLL(display, 0);
expected_mask <<= 4;
break;
case PORT_D:
@@ -500,11 +500,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
break;
}
- if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
- drm_WARN(&dev_priv->drm, 1,
+ if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
+ drm_WARN(display->drm, 1,
"timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
dig_port->base.base.base.id, dig_port->base.base.name,
- intel_de_read(dev_priv, dpll_reg) & port_mask,
+ intel_de_read(display, dpll_reg) & port_mask,
expected_mask);
}
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 61e1df878de9..51fd8d109f7c 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -492,7 +492,7 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder);
enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
-void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
+void vlv_wait_port_ready(struct intel_display *display,
struct intel_digital_port *dig_port,
unsigned int expected_mask);
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
2024-10-22 15:57 ` [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() " Jani Nikula
@ 2024-10-23 17:18 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 17:18 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:24PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch vlv_wait_port_ready() over to
> it. The main motivation to do just one function is to stop passing i915
> to intel_de_wait(), so its generic wrapper can be removed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_dp.c | 3 +--
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 9 ++++-----
> drivers/gpu/drm/i915/display/intel_display.c | 12 ++++++------
> drivers/gpu/drm/i915/display/intel_display.h | 2 +-
> 4 files changed, 12 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
> index 440fb3002f28..a22781d21110 100644
> --- a/drivers/gpu/drm/i915/display/g4x_dp.c
> +++ b/drivers/gpu/drm/i915/display/g4x_dp.c
> @@ -706,8 +706,7 @@ static void intel_enable_dp(struct intel_atomic_state *state,
> if (IS_CHERRYVIEW(dev_priv))
> lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
>
> - vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
> - lane_mask);
> + vlv_wait_port_ready(display, dp_to_dig_port(intel_dp), lane_mask);
> }
>
> intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 46f23bdb4c17..d1a7d0d57c6b 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -480,8 +480,8 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
>
> vlv_phy_pre_encoder_enable(encoder, pipe_config);
>
> @@ -496,7 +496,7 @@ static void vlv_hdmi_pre_enable(struct intel_atomic_state *state,
>
> g4x_hdmi_enable_port(encoder, pipe_config);
>
> - vlv_wait_port_ready(dev_priv, dig_port, 0x0);
> + vlv_wait_port_ready(display, dig_port, 0x0);
> }
>
> static void vlv_hdmi_pre_pll_enable(struct intel_atomic_state *state,
> @@ -557,9 +557,8 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
> const struct intel_crtc_state *pipe_config,
> const struct drm_connector_state *conn_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
> - struct drm_device *dev = encoder->base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
>
> chv_phy_pre_encoder_enable(encoder, pipe_config);
>
> @@ -573,7 +572,7 @@ static void chv_hdmi_pre_enable(struct intel_atomic_state *state,
>
> g4x_hdmi_enable_port(encoder, pipe_config);
>
> - vlv_wait_port_ready(dev_priv, dig_port, 0x0);
> + vlv_wait_port_ready(display, dig_port, 0x0);
>
> /* Second common lane will stay alive on its own now */
> chv_phy_release_cl2_override(encoder);
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 2479ca0a02d9..53e81b0030d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -474,7 +474,7 @@ static void assert_planes_disabled(struct intel_crtc *crtc)
> assert_plane_disabled(plane);
> }
>
> -void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> +void vlv_wait_port_ready(struct intel_display *display,
> struct intel_digital_port *dig_port,
> unsigned int expected_mask)
> {
> @@ -487,11 +487,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> fallthrough;
> case PORT_B:
> port_mask = DPLL_PORTB_READY_MASK;
> - dpll_reg = DPLL(dev_priv, 0);
> + dpll_reg = DPLL(display, 0);
> break;
> case PORT_C:
> port_mask = DPLL_PORTC_READY_MASK;
> - dpll_reg = DPLL(dev_priv, 0);
> + dpll_reg = DPLL(display, 0);
> expected_mask <<= 4;
> break;
> case PORT_D:
> @@ -500,11 +500,11 @@ void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> break;
> }
>
> - if (intel_de_wait(dev_priv, dpll_reg, port_mask, expected_mask, 1000))
> - drm_WARN(&dev_priv->drm, 1,
> + if (intel_de_wait(display, dpll_reg, port_mask, expected_mask, 1000))
> + drm_WARN(display->drm, 1,
> "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
> dig_port->base.base.base.id, dig_port->base.base.name,
> - intel_de_read(dev_priv, dpll_reg) & port_mask,
> + intel_de_read(display, dpll_reg) & port_mask,
> expected_mask);
> }
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 61e1df878de9..51fd8d109f7c 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -492,7 +492,7 @@ bool intel_encoder_is_tc(struct intel_encoder *encoder);
> enum tc_port intel_encoder_to_tc(struct intel_encoder *encoder);
>
> int ilk_get_lanes_required(int target_clock, int link_bw, int bpp);
> -void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> +void vlv_wait_port_ready(struct intel_display *display,
> struct intel_digital_port *dig_port,
> unsigned int expected_mask);
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (6 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 07/11] drm/i915/display: convert vlv_wait_port_ready() " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 17:19 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 09/11] drm/i915/ips: convert " Jani Nikula
` (10 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch assert_chv_phy_status() and its
callers to it. Main motivation to do just one function is to stop
passing i915 to intel_de_wait(), so its generic wrapper can be removed.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
.../i915/display/intel_display_power_well.c | 95 ++++++++++---------
1 file changed, 50 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 885bc2e563c5..f0131dd853de 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -1337,13 +1337,14 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
-static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
+static void assert_chv_phy_status(struct intel_display *display)
{
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
struct i915_power_well *cmn_bc =
lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
struct i915_power_well *cmn_d =
lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->display.power.chv_phy_control;
+ u32 phy_control = display->power.chv_phy_control;
u32 phy_status = 0;
u32 phy_status_mask = 0xffffffff;
@@ -1354,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* reset (ie. the power well has been disabled at
* least once).
*/
- if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
+ if (!display->power.chv_phy_assert[DPIO_PHY0])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
@@ -1362,7 +1363,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
- if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
+ if (!display->power.chv_phy_assert[DPIO_PHY1])
phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
@@ -1390,7 +1391,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
*/
if (BITS_SET(phy_control,
PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
- (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
+ (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
if (BITS_SET(phy_control,
@@ -1433,12 +1434,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
* The PHY may be busy with some initial calibration and whatnot,
* so the power state can take a while to actually change.
*/
- if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
+ if (intel_de_wait(display, DISPLAY_PHY_STATUS,
phy_status_mask, phy_status, 10))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
- intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->display.power.chv_phy_control);
+ intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
+ phy_status, display->power.chv_phy_control);
}
#undef BITS_SET
@@ -1446,11 +1447,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ struct intel_display *display = &dev_priv->display;
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
u32 tmp;
- drm_WARN_ON_ONCE(&dev_priv->drm,
+ drm_WARN_ON_ONCE(display->drm,
id != VLV_DISP_PW_DPIO_CMN_BC &&
id != CHV_DISP_PW_DPIO_CMN_D);
@@ -1464,9 +1466,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_set_power_well(dev_priv, power_well, true);
/* Poll for phypwrgood signal */
- if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
+ if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
PHY_POWERGOOD(phy), 1))
- drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
+ drm_err(display->drm, "Display PHY %d is not power up\n",
phy);
vlv_dpio_get(dev_priv);
@@ -1494,24 +1496,25 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_put(dev_priv);
- dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->display.power.chv_phy_control);
+ phy, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
}
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ struct intel_display *display = &dev_priv->display;
enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
- drm_WARN_ON_ONCE(&dev_priv->drm,
+ drm_WARN_ON_ONCE(display->drm,
id != VLV_DISP_PW_DPIO_CMN_BC &&
id != CHV_DISP_PW_DPIO_CMN_D);
@@ -1524,20 +1527,20 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
assert_pll_disabled(dev_priv, PIPE_C);
}
- dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
vlv_set_power_well(dev_priv, power_well, false);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->display.power.chv_phy_control);
+ phy, display->power.chv_phy_control);
/* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->display.power.chv_phy_assert[phy] = true;
+ display->power.chv_phy_assert[phy] = true;
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
}
static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
@@ -1607,29 +1610,30 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
enum dpio_channel ch, bool override)
{
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct intel_display *display = &dev_priv->display;
+ struct i915_power_domains *power_domains = &display->power.domains;
bool was_override;
mutex_lock(&power_domains->lock);
- was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
if (override == was_override)
goto out;
if (override)
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->display.power.chv_phy_control);
+ phy, ch, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
out:
mutex_unlock(&power_domains->lock);
@@ -1640,29 +1644,30 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
bool override, unsigned int mask)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
+ struct i915_power_domains *power_domains = &display->power.domains;
enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
mutex_lock(&power_domains->lock);
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
if (override)
- dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
else
- dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->display.power.chv_phy_control);
+ intel_de_write(display, DISPLAY_PHY_CONTROL,
+ display->power.chv_phy_control);
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->display.power.chv_phy_control);
+ phy, ch, mask, display->power.chv_phy_control);
- assert_chv_phy_status(dev_priv);
+ assert_chv_phy_status(display);
assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() to struct intel_display
2024-10-22 15:57 ` [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() " Jani Nikula
@ 2024-10-23 17:19 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 17:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:25PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch assert_chv_phy_status() and its
> callers to it. Main motivation to do just one function is to stop
> passing i915 to intel_de_wait(), so its generic wrapper can be removed.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> .../i915/display/intel_display_power_well.c | 95 ++++++++++---------
> 1 file changed, 50 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 885bc2e563c5..f0131dd853de 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -1337,13 +1337,14 @@ static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
>
> #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
>
> -static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> +static void assert_chv_phy_status(struct intel_display *display)
> {
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> struct i915_power_well *cmn_bc =
> lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
> struct i915_power_well *cmn_d =
> lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
> - u32 phy_control = dev_priv->display.power.chv_phy_control;
> + u32 phy_control = display->power.chv_phy_control;
> u32 phy_status = 0;
> u32 phy_status_mask = 0xffffffff;
>
> @@ -1354,7 +1355,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> * reset (ie. the power well has been disabled at
> * least once).
> */
> - if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY0])
> + if (!display->power.chv_phy_assert[DPIO_PHY0])
> phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
> @@ -1362,7 +1363,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
>
> - if (!dev_priv->display.power.chv_phy_assert[DPIO_PHY1])
> + if (!display->power.chv_phy_assert[DPIO_PHY1])
> phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
> PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
> @@ -1390,7 +1391,7 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> */
> if (BITS_SET(phy_control,
> PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
> - (intel_de_read(dev_priv, DPLL(dev_priv, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
> + (intel_de_read(display, DPLL(display, PIPE_B)) & DPLL_VCO_ENABLE) == 0)
> phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
>
> if (BITS_SET(phy_control,
> @@ -1433,12 +1434,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> * The PHY may be busy with some initial calibration and whatnot,
> * so the power state can take a while to actually change.
> */
> - if (intel_de_wait(dev_priv, DISPLAY_PHY_STATUS,
> + if (intel_de_wait(display, DISPLAY_PHY_STATUS,
> phy_status_mask, phy_status, 10))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
> - intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
> - phy_status, dev_priv->display.power.chv_phy_control);
> + intel_de_read(display, DISPLAY_PHY_STATUS) & phy_status_mask,
> + phy_status, display->power.chv_phy_control);
> }
>
> #undef BITS_SET
> @@ -1446,11 +1447,12 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> + struct intel_display *display = &dev_priv->display;
> enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
> enum dpio_phy phy;
> u32 tmp;
>
> - drm_WARN_ON_ONCE(&dev_priv->drm,
> + drm_WARN_ON_ONCE(display->drm,
> id != VLV_DISP_PW_DPIO_CMN_BC &&
> id != CHV_DISP_PW_DPIO_CMN_D);
>
> @@ -1464,9 +1466,9 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> vlv_set_power_well(dev_priv, power_well, true);
>
> /* Poll for phypwrgood signal */
> - if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
> + if (intel_de_wait_for_set(display, DISPLAY_PHY_STATUS,
> PHY_POWERGOOD(phy), 1))
> - drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
> + drm_err(display->drm, "Display PHY %d is not power up\n",
> phy);
>
> vlv_dpio_get(dev_priv);
> @@ -1494,24 +1496,25 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
>
> vlv_dpio_put(dev_priv);
>
> - dev_priv->display.power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->display.power.chv_phy_control);
> + display->power.chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
> + intel_de_write(display, DISPLAY_PHY_CONTROL,
> + display->power.chv_phy_control);
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> - phy, dev_priv->display.power.chv_phy_control);
> + phy, display->power.chv_phy_control);
>
> - assert_chv_phy_status(dev_priv);
> + assert_chv_phy_status(display);
> }
>
> static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> struct i915_power_well *power_well)
> {
> + struct intel_display *display = &dev_priv->display;
> enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
> enum dpio_phy phy;
>
> - drm_WARN_ON_ONCE(&dev_priv->drm,
> + drm_WARN_ON_ONCE(display->drm,
> id != VLV_DISP_PW_DPIO_CMN_BC &&
> id != CHV_DISP_PW_DPIO_CMN_D);
>
> @@ -1524,20 +1527,20 @@ static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
> assert_pll_disabled(dev_priv, PIPE_C);
> }
>
> - dev_priv->display.power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->display.power.chv_phy_control);
> + display->power.chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> + intel_de_write(display, DISPLAY_PHY_CONTROL,
> + display->power.chv_phy_control);
>
> vlv_set_power_well(dev_priv, power_well, false);
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> - phy, dev_priv->display.power.chv_phy_control);
> + phy, display->power.chv_phy_control);
>
> /* PHY is fully reset now, so we can enable the PHY state asserts */
> - dev_priv->display.power.chv_phy_assert[phy] = true;
> + display->power.chv_phy_assert[phy] = true;
>
> - assert_chv_phy_status(dev_priv);
> + assert_chv_phy_status(display);
> }
>
> static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> @@ -1607,29 +1610,30 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
> bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> enum dpio_channel ch, bool override)
> {
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct intel_display *display = &dev_priv->display;
> + struct i915_power_domains *power_domains = &display->power.domains;
> bool was_override;
>
> mutex_lock(&power_domains->lock);
>
> - was_override = dev_priv->display.power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + was_override = display->power.chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
>
> if (override == was_override)
> goto out;
>
> if (override)
> - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> else
> - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
>
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->display.power.chv_phy_control);
> + intel_de_write(display, DISPLAY_PHY_CONTROL,
> + display->power.chv_phy_control);
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
> - phy, ch, dev_priv->display.power.chv_phy_control);
> + phy, ch, display->power.chv_phy_control);
>
> - assert_chv_phy_status(dev_priv);
> + assert_chv_phy_status(display);
>
> out:
> mutex_unlock(&power_domains->lock);
> @@ -1640,29 +1644,30 @@ bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
> void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> bool override, unsigned int mask)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_power_domains *power_domains = &dev_priv->display.power.domains;
> + struct i915_power_domains *power_domains = &display->power.domains;
> enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
> enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
>
> mutex_lock(&power_domains->lock);
>
> - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
> - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
> + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
> + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
>
> if (override)
> - dev_priv->display.power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + display->power.chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> else
> - dev_priv->display.power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + display->power.chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
>
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->display.power.chv_phy_control);
> + intel_de_write(display, DISPLAY_PHY_CONTROL,
> + display->power.chv_phy_control);
>
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
> - phy, ch, mask, dev_priv->display.power.chv_phy_control);
> + phy, ch, mask, display->power.chv_phy_control);
>
> - assert_chv_phy_status(dev_priv);
> + assert_chv_phy_status(display);
>
> assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 09/11] drm/i915/ips: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (7 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 08/11] drm/i915/power: convert assert_chv_phy_status() " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 17:19 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 10/11] drm/i915/dsi: " Jani Nikula
` (9 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch HSW IPS code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/hsw_ips.c | 47 ++++++++++++++------------
1 file changed, 26 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index c571c6e76d4a..34c5d28fc866 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -15,6 +15,7 @@
static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
u32 val;
@@ -27,16 +28,16 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* This function is called from post_plane_update, which is run after
* a vblank wait.
*/
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
val = IPS_ENABLE;
- if (i915->display.ips.false_color)
+ if (display->ips.false_color)
val |= IPS_FALSE_COLOR;
if (IS_BROADWELL(i915)) {
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
val | IPS_PCODE_CONTROL));
/*
@@ -46,7 +47,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* so we need to just enable it and continue on.
*/
} else {
- intel_de_write(i915, IPS_CTL, val);
+ intel_de_write(display, IPS_CTL, val);
/*
* The bit only becomes 1 in the next vblank, so this wait here
* is essentially intel_wait_for_vblank. If we don't have this
@@ -54,14 +55,15 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
* the HW state readout code will complain that the expected
* IPS_CTL value is not the one we read.
*/
- if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
- drm_err(&i915->drm,
+ if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
+ drm_err(display->drm,
"Timed out waiting for IPS enable\n");
}
}
bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
bool need_vblank_wait = false;
@@ -70,19 +72,19 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
return need_vblank_wait;
if (IS_BROADWELL(i915)) {
- drm_WARN_ON(&i915->drm,
+ drm_WARN_ON(display->drm,
snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
* instead.
*/
- if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
- drm_err(&i915->drm,
+ if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
+ drm_err(display->drm,
"Timed out waiting for IPS disable\n");
} else {
- intel_de_write(i915, IPS_CTL, 0);
- intel_de_posting_read(i915, IPS_CTL);
+ intel_de_write(display, IPS_CTL, 0);
+ intel_de_posting_read(display, IPS_CTL);
}
/* We need to wait for a vblank before we can disable the plane. */
@@ -188,6 +190,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -195,7 +198,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
if (!hsw_crtc_supports_ips(crtc))
return false;
- if (!i915->display.params.enable_ips)
+ if (!display->params.enable_ips)
return false;
if (crtc_state->pipe_bpp > 24)
@@ -209,7 +212,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
* Should measure whether using a lower cdclk w/o IPS
*/
if (IS_BROADWELL(i915) &&
- crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
+ crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
return false;
return true;
@@ -259,6 +262,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(crtc_state);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
@@ -266,7 +270,7 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
return;
if (IS_HASWELL(i915)) {
- crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
+ crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
} else {
/*
* We cannot readout IPS state on broadwell, set to
@@ -280,9 +284,9 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
{
struct intel_crtc *crtc = data;
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
- *val = i915->display.ips.false_color;
+ *val = display->ips.false_color;
return 0;
}
@@ -290,7 +294,7 @@ static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
{
struct intel_crtc *crtc = data;
- struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc);
struct intel_crtc_state *crtc_state;
int ret;
@@ -298,7 +302,7 @@ static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
if (ret)
return ret;
- i915->display.ips.false_color = val;
+ display->ips.false_color = val;
crtc_state = to_intel_crtc_state(crtc->base.state);
@@ -325,18 +329,19 @@ DEFINE_DEBUGFS_ATTRIBUTE(hsw_ips_debugfs_false_color_fops,
static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)
{
struct intel_crtc *crtc = m->private;
+ struct intel_display *display = to_intel_display(crtc);
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
intel_wakeref_t wakeref;
wakeref = intel_runtime_pm_get(&i915->runtime_pm);
seq_printf(m, "Enabled by kernel parameter: %s\n",
- str_yes_no(i915->display.params.enable_ips));
+ str_yes_no(display->params.enable_ips));
- if (DISPLAY_VER(i915) >= 8) {
+ if (DISPLAY_VER(display) >= 8) {
seq_puts(m, "Currently: unknown\n");
} else {
- if (intel_de_read(i915, IPS_CTL) & IPS_ENABLE)
+ if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
seq_puts(m, "Currently: enabled\n");
else
seq_puts(m, "Currently: disabled\n");
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 09/11] drm/i915/ips: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 09/11] drm/i915/ips: convert " Jani Nikula
@ 2024-10-23 17:19 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 17:19 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:26PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch HSW IPS code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/hsw_ips.c | 47 ++++++++++++++------------
> 1 file changed, 26 insertions(+), 21 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
> index c571c6e76d4a..34c5d28fc866 100644
> --- a/drivers/gpu/drm/i915/display/hsw_ips.c
> +++ b/drivers/gpu/drm/i915/display/hsw_ips.c
> @@ -15,6 +15,7 @@
>
> static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> u32 val;
> @@ -27,16 +28,16 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> * This function is called from post_plane_update, which is run after
> * a vblank wait.
> */
> - drm_WARN_ON(&i915->drm,
> + drm_WARN_ON(display->drm,
> !(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
>
> val = IPS_ENABLE;
>
> - if (i915->display.ips.false_color)
> + if (display->ips.false_color)
> val |= IPS_FALSE_COLOR;
>
> if (IS_BROADWELL(i915)) {
> - drm_WARN_ON(&i915->drm,
> + drm_WARN_ON(display->drm,
> snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL,
> val | IPS_PCODE_CONTROL));
> /*
> @@ -46,7 +47,7 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> * so we need to just enable it and continue on.
> */
> } else {
> - intel_de_write(i915, IPS_CTL, val);
> + intel_de_write(display, IPS_CTL, val);
> /*
> * The bit only becomes 1 in the next vblank, so this wait here
> * is essentially intel_wait_for_vblank. If we don't have this
> @@ -54,14 +55,15 @@ static void hsw_ips_enable(const struct intel_crtc_state *crtc_state)
> * the HW state readout code will complain that the expected
> * IPS_CTL value is not the one we read.
> */
> - if (intel_de_wait_for_set(i915, IPS_CTL, IPS_ENABLE, 50))
> - drm_err(&i915->drm,
> + if (intel_de_wait_for_set(display, IPS_CTL, IPS_ENABLE, 50))
> + drm_err(display->drm,
> "Timed out waiting for IPS enable\n");
> }
> }
>
> bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> bool need_vblank_wait = false;
> @@ -70,19 +72,19 @@ bool hsw_ips_disable(const struct intel_crtc_state *crtc_state)
> return need_vblank_wait;
>
> if (IS_BROADWELL(i915)) {
> - drm_WARN_ON(&i915->drm,
> + drm_WARN_ON(display->drm,
> snb_pcode_write(&i915->uncore, DISPLAY_IPS_CONTROL, 0));
> /*
> * Wait for PCODE to finish disabling IPS. The BSpec specified
> * 42ms timeout value leads to occasional timeouts so use 100ms
> * instead.
> */
> - if (intel_de_wait_for_clear(i915, IPS_CTL, IPS_ENABLE, 100))
> - drm_err(&i915->drm,
> + if (intel_de_wait_for_clear(display, IPS_CTL, IPS_ENABLE, 100))
> + drm_err(display->drm,
> "Timed out waiting for IPS disable\n");
> } else {
> - intel_de_write(i915, IPS_CTL, 0);
> - intel_de_posting_read(i915, IPS_CTL);
> + intel_de_write(display, IPS_CTL, 0);
> + intel_de_posting_read(display, IPS_CTL);
> }
>
> /* We need to wait for a vblank before we can disable the plane. */
> @@ -188,6 +190,7 @@ bool hsw_crtc_supports_ips(struct intel_crtc *crtc)
>
> bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> @@ -195,7 +198,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> if (!hsw_crtc_supports_ips(crtc))
> return false;
>
> - if (!i915->display.params.enable_ips)
> + if (!display->params.enable_ips)
> return false;
>
> if (crtc_state->pipe_bpp > 24)
> @@ -209,7 +212,7 @@ bool hsw_crtc_state_ips_capable(const struct intel_crtc_state *crtc_state)
> * Should measure whether using a lower cdclk w/o IPS
> */
> if (IS_BROADWELL(i915) &&
> - crtc_state->pixel_rate > i915->display.cdclk.max_cdclk_freq * 95 / 100)
> + crtc_state->pixel_rate > display->cdclk.max_cdclk_freq * 95 / 100)
> return false;
>
> return true;
> @@ -259,6 +262,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
>
> void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(crtc_state);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>
> @@ -266,7 +270,7 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
> return;
>
> if (IS_HASWELL(i915)) {
> - crtc_state->ips_enabled = intel_de_read(i915, IPS_CTL) & IPS_ENABLE;
> + crtc_state->ips_enabled = intel_de_read(display, IPS_CTL) & IPS_ENABLE;
> } else {
> /*
> * We cannot readout IPS state on broadwell, set to
> @@ -280,9 +284,9 @@ void hsw_ips_get_config(struct intel_crtc_state *crtc_state)
> static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
> {
> struct intel_crtc *crtc = data;
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
>
> - *val = i915->display.ips.false_color;
> + *val = display->ips.false_color;
>
> return 0;
> }
> @@ -290,7 +294,7 @@ static int hsw_ips_debugfs_false_color_get(void *data, u64 *val)
> static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
> {
> struct intel_crtc *crtc = data;
> - struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc);
> struct intel_crtc_state *crtc_state;
> int ret;
>
> @@ -298,7 +302,7 @@ static int hsw_ips_debugfs_false_color_set(void *data, u64 val)
> if (ret)
> return ret;
>
> - i915->display.ips.false_color = val;
> + display->ips.false_color = val;
>
> crtc_state = to_intel_crtc_state(crtc->base.state);
>
> @@ -325,18 +329,19 @@ DEFINE_DEBUGFS_ATTRIBUTE(hsw_ips_debugfs_false_color_fops,
> static int hsw_ips_debugfs_status_show(struct seq_file *m, void *unused)
> {
> struct intel_crtc *crtc = m->private;
> + struct intel_display *display = to_intel_display(crtc);
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> intel_wakeref_t wakeref;
>
> wakeref = intel_runtime_pm_get(&i915->runtime_pm);
>
> seq_printf(m, "Enabled by kernel parameter: %s\n",
> - str_yes_no(i915->display.params.enable_ips));
> + str_yes_no(display->params.enable_ips));
>
> - if (DISPLAY_VER(i915) >= 8) {
> + if (DISPLAY_VER(display) >= 8) {
> seq_puts(m, "Currently: unknown\n");
> } else {
> - if (intel_de_read(i915, IPS_CTL) & IPS_ENABLE)
> + if (intel_de_read(display, IPS_CTL) & IPS_ENABLE)
> seq_puts(m, "Currently: enabled\n");
> else
> seq_puts(m, "Currently: disabled\n");
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 10/11] drm/i915/dsi: convert to struct intel_display
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (8 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 09/11] drm/i915/ips: convert " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 17:26 ` Rodrigo Vivi
2024-10-22 15:57 ` [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers Jani Nikula
` (8 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
struct intel_display will replace struct drm_i915_private as the main
device pointer for display code. Switch ICL DSI code over to it.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 444 ++++++++++++-----------
drivers/gpu/drm/i915/display/icl_dsi.h | 4 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
3 files changed, 227 insertions(+), 223 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 87a27d91d15d..b61f2363d5c2 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -51,38 +51,38 @@
#include "skl_scaler.h"
#include "skl_universal_plane.h"
-static int header_credits_available(struct drm_i915_private *dev_priv,
+static int header_credits_available(struct intel_display *display,
enum transcoder dsi_trans)
{
- return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
+ return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
>> FREE_HEADER_CREDIT_SHIFT;
}
-static int payload_credits_available(struct drm_i915_private *dev_priv,
+static int payload_credits_available(struct intel_display *display,
enum transcoder dsi_trans)
{
- return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
+ return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
>> FREE_PLOAD_CREDIT_SHIFT;
}
-static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
+static bool wait_for_header_credits(struct intel_display *display,
enum transcoder dsi_trans, int hdr_credit)
{
- if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
+ if (wait_for_us(header_credits_available(display, dsi_trans) >=
hdr_credit, 100)) {
- drm_err(&dev_priv->drm, "DSI header credits not released\n");
+ drm_err(display->drm, "DSI header credits not released\n");
return false;
}
return true;
}
-static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
+static bool wait_for_payload_credits(struct intel_display *display,
enum transcoder dsi_trans, int payld_credit)
{
- if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
+ if (wait_for_us(payload_credits_available(display, dsi_trans) >=
payld_credit, 100)) {
- drm_err(&dev_priv->drm, "DSI payload credits not released\n");
+ drm_err(display->drm, "DSI payload credits not released\n");
return false;
}
@@ -99,7 +99,7 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct mipi_dsi_device *dsi;
enum port port;
@@ -109,8 +109,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
/* wait for header/payload credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
- wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
+ wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
+ wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
}
/* send nop DCS command */
@@ -120,22 +120,22 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
dsi->channel = 0;
ret = mipi_dsi_dcs_nop(dsi);
if (ret < 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"error sending DCS NOP command\n");
}
/* wait for header credits to be released */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
+ wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
}
/* wait for LP TX in progress bit to be cleared */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
+ if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
LPTX_IN_PROGRESS), 20))
- drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
+ drm_err(display->drm, "LPTX bit not cleared\n");
}
}
@@ -143,7 +143,7 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
const struct mipi_dsi_packet *packet)
{
struct intel_dsi *intel_dsi = host->intel_dsi;
- struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
const u8 *data = packet->payload;
u32 len = packet->payload_length;
@@ -151,20 +151,20 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
/* payload queue can accept *256 bytes*, check limit */
if (len > MAX_PLOAD_CREDIT * 4) {
- drm_err(&i915->drm, "payload size exceeds max queue limit\n");
+ drm_err(display->drm, "payload size exceeds max queue limit\n");
return -EINVAL;
}
for (i = 0; i < len; i += 4) {
u32 tmp = 0;
- if (!wait_for_payload_credits(i915, dsi_trans, 1))
+ if (!wait_for_payload_credits(display, dsi_trans, 1))
return -EBUSY;
for (j = 0; j < min_t(u32, len - i, 4); j++)
tmp |= *data++ << 8 * j;
- intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
+ intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
}
return 0;
@@ -175,14 +175,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
bool enable_lpdt)
{
struct intel_dsi *intel_dsi = host->intel_dsi;
- struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
u32 tmp;
- if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
+ if (!wait_for_header_credits(display, dsi_trans, 1))
return -EBUSY;
- tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
+ tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
if (packet->payload)
tmp |= PAYLOAD_PRESENT;
@@ -201,15 +201,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
- intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
+ intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
return 0;
}
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
{
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
- struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
+ struct intel_display *display = to_intel_display(crtc_state);
u32 mode_flags;
enum port port;
@@ -227,12 +226,13 @@ void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
else
return;
- intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
+ intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
+ DSI_FRAME_UPDATE_REQUEST);
}
static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum phy phy;
u32 tmp, mask, val;
@@ -246,31 +246,31 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
RTERM_SELECT(0x6);
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp &= ~mask;
tmp |= val;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
RCOMP_SCALAR_MASK;
val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
RCOMP_SCALAR(0x98);
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
tmp &= ~mask;
tmp |= val;
- intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
+ intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
CURSOR_COEFF_MASK;
val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
CURSOR_COEFF(0x3f);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
+ intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
/* Bspec: must not use GRP register for write */
for (lane = 0; lane <= 3; lane++)
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
mask, val);
}
}
@@ -278,13 +278,13 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
static void configure_dual_link_mode(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
u32 dss_ctl1;
/* FIXME: Move all DSS handling to intel_vdsc.c */
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
@@ -294,7 +294,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dss_ctl2_reg = DSS_CTL2;
}
- dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
+ dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
dss_ctl1 |= SPLITTER_ENABLE;
dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
@@ -309,19 +309,19 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DL buffer depth exceed max value\n");
dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
- intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
+ intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
} else {
/* Interleave */
dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
}
- intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
+ intel_de_write(display, dss_ctl1_reg, dss_ctl1);
}
/* aka DSI 8X clock */
@@ -342,6 +342,7 @@ static int afe_clk(struct intel_encoder *encoder,
static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -361,33 +362,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
}
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
+ intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
- intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
+ intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
}
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
+ intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
- intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
+ intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
}
if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
+ intel_de_write(display, ADL_MIPIO_DW(port, 8),
esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
- intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
+ intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
}
}
}
-static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
- struct intel_dsi *intel_dsi)
+static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
{
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
+ struct drm_i915_private *dev_priv = to_i915(display->drm);
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
+ drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
@@ -398,15 +400,15 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
+ intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
0, COMBO_PHY_MODE_DSI);
- get_dsi_io_power_domains(dev_priv, intel_dsi);
+ get_dsi_io_power_domains(intel_dsi);
}
static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
@@ -422,6 +424,7 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum phy phy;
@@ -430,32 +433,33 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
/* Step 4b(i) set loadgen select for transmit and aux lanes */
for_each_dsi_phy(phy, intel_dsi->phys) {
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
+ intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
+ LOADGEN_SELECT, 0);
for (lane = 0; lane <= 3; lane++)
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
}
/* Step 4b(ii) set latency optimization for transmit and aux lanes */
for_each_dsi_phy(phy, intel_dsi->phys) {
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
+ intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
tmp &= ~FRC_LATENCY_OPTIM_MASK;
tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
- intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
+ intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
/* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
- (DISPLAY_VER(dev_priv) >= 12)) {
- intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
+ (DISPLAY_VER(display) >= 12)) {
+ intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
- tmp = intel_de_read(dev_priv,
+ tmp = intel_de_read(display,
ICL_PORT_PCS_DW1_LN(0, phy));
tmp &= ~LATENCY_OPTIM_MASK;
tmp |= LATENCY_OPTIM_VAL(0x1);
- intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
+ intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
tmp);
}
}
@@ -464,17 +468,17 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
/* clear common keeper enable bit */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
tmp &= ~COMMON_KEEPER_EN;
- intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
+ intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
}
/*
@@ -483,14 +487,15 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
* as part of lane phy sequence configuration
*/
for_each_dsi_phy(phy, intel_dsi->phys)
- intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
+ intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
+ SUS_CLOCK_CONFIG);
/* Clear training enable to change swing values */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp &= ~TX_TRAINING_EN;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
}
/* Program swing and de-emphasis */
@@ -498,26 +503,26 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
/* Set training enable to trigger update */
for_each_dsi_phy(phy, intel_dsi->phys) {
- tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
+ tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
tmp |= TX_TRAINING_EN;
- intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
- intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
+ intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
+ intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
}
}
static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
+ intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
- if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
DDI_BUF_IS_IDLE),
500))
- drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
+ drm_err(display->drm, "DDI port:%c buffer idle\n",
port_name(port));
}
}
@@ -526,6 +531,7 @@ static void
gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -533,12 +539,12 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
/* Program DPHY clock lanes timings */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
+ intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
intel_dsi->dphy_reg);
/* Program DPHY data lanes timings */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
+ intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
/*
@@ -547,10 +553,10 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
* a value '0' inside TA_PARAM_REGISTERS otherwise
* leave all fields at HW default values.
*/
- if (DISPLAY_VER(dev_priv) == 11) {
+ if (DISPLAY_VER(display) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
+ intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
TA_SURE_MASK,
TA_SURE_OVERRIDE | TA_SURE(0));
}
@@ -558,7 +564,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
for_each_dsi_phy(phy, intel_dsi->phys)
- intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
+ intel_de_rmw(display, ICL_DPHY_CHKN(phy),
0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
}
}
@@ -567,30 +573,30 @@ static void
gen11_dsi_setup_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
/* Program T-INIT master registers */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
+ intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
/* shadow register inside display core */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
+ intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
intel_dsi->dphy_reg);
/* shadow register inside display core */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
+ intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
intel_dsi->dphy_data_lane_reg);
/* shadow register inside display core */
- if (DISPLAY_VER(dev_priv) == 11) {
+ if (DISPLAY_VER(display) == 11) {
if (afe_clk(encoder, crtc_state) <= 800000) {
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
+ intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
TA_SURE_MASK,
TA_SURE_OVERRIDE | TA_SURE(0));
}
@@ -600,45 +606,45 @@ gen11_dsi_setup_timings(struct intel_encoder *encoder,
static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->display.dpll.lock);
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ mutex_lock(&display->dpll.lock);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
+ mutex_unlock(&display->dpll.lock);
}
static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
enum phy phy;
- mutex_lock(&dev_priv->display.dpll.lock);
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ mutex_lock(&display->dpll.lock);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys)
tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
+ mutex_unlock(&display->dpll.lock);
}
static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
bool clock_enabled = false;
enum phy phy;
u32 tmp;
- tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
@@ -651,36 +657,36 @@ static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
static void gen11_dsi_map_pll(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_shared_dpll *pll = crtc_state->shared_dpll;
enum phy phy;
u32 val;
- mutex_lock(&dev_priv->display.dpll.lock);
+ mutex_lock(&display->dpll.lock);
- val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
}
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
for_each_dsi_phy(phy, intel_dsi->phys) {
val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
}
- intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
+ intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
- intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
+ intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
- mutex_unlock(&dev_priv->display.dpll.lock);
+ mutex_unlock(&display->dpll.lock);
}
static void
gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
const struct intel_crtc_state *pipe_config)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
enum pipe pipe = crtc->pipe;
@@ -690,7 +696,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
+ tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
if (intel_dsi->eotp_pkt)
tmp &= ~EOTP_DISABLED;
@@ -746,7 +752,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
}
}
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
if (is_vid_mode(intel_dsi))
tmp |= BLANKING_PACKET_ENABLE;
}
@@ -779,15 +785,15 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
tmp |= TE_SOURCE_GPIO;
}
- intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
+ intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
}
/* enable port sync mode if dual link */
if (intel_dsi->dual_link) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL2(display, dsi_trans),
0, PORT_SYNC_MODE_ENABLE);
}
@@ -799,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
/* select data lane width */
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
+ tmp = intel_de_read(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans));
tmp &= ~DDI_PORT_WIDTH_MASK;
tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
@@ -826,16 +832,16 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
/* enable DDI buffer */
tmp |= TRANS_DDI_FUNC_ENABLE;
- intel_de_write(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
+ intel_de_write(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
}
/* wait for link ready */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
+ if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
LINK_READY), 2500))
- drm_err(&dev_priv->drm, "DSI link not ready\n");
+ drm_err(display->drm, "DSI link not ready\n");
}
}
@@ -843,7 +849,7 @@ static void
gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
const struct drm_display_mode *adjusted_mode =
&crtc_state->hw.adjusted_mode;
@@ -910,17 +916,17 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
/* minimum hactive as per bspec: 256 pixels */
if (adjusted_mode->crtc_hdisplay < 256)
- drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
+ drm_err(display->drm, "hactive is less then 256 pixels\n");
/* if RGB666 format, then hactive must be multiple of 4 pixels */
if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"hactive pixels are not multiple of 4\n");
/* program TRANS_HTOTAL register */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
+ intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
}
@@ -929,12 +935,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
/* BSPEC: hsync size should be atleast 16 pixels */
if (hsync_size < 16)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"hsync size < 16 pixels\n");
}
if (hback_porch < 16)
- drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
+ drm_err(display->drm, "hback porch < 16 pixels\n");
if (intel_dsi->dual_link) {
hsync_start /= 2;
@@ -943,8 +949,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_HSYNC(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_HSYNC(display, dsi_trans),
HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
}
}
@@ -958,22 +964,22 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* struct drm_display_mode.
* For interlace mode: program required pixel minus 2
*/
- intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
+ intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
}
if (vsync_end < vsync_start || vsync_end > vtotal)
- drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
+ drm_err(display->drm, "Invalid vsync_end value\n");
if (vsync_start < vactive)
- drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
+ drm_err(display->drm, "vsync_start less than vactive\n");
/* program TRANS_VSYNC register for video mode only */
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VSYNC(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VSYNC(display, dsi_trans),
VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
}
}
@@ -987,8 +993,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VSYNCSHIFT(display, dsi_trans),
vsync_shift);
}
}
@@ -999,11 +1005,11 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
* FIXME get rid of these local hacks and do it right,
* this will not handle eg. delayed vblank correctly.
*/
- if (DISPLAY_VER(dev_priv) >= 12) {
+ if (DISPLAY_VER(display) >= 12) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_write(dev_priv,
- TRANS_VBLANK(dev_priv, dsi_trans),
+ intel_de_write(display,
+ TRANS_VBLANK(display, dsi_trans),
VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
}
}
@@ -1011,20 +1017,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
+ intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
TRANSCONF_ENABLE);
/* wait for transcoder to be enabled */
- if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
TRANSCONF_STATE_ENABLE, 10))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DSI transcoder not enabled\n");
}
}
@@ -1032,7 +1038,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1056,21 +1062,21 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
dsi_trans = dsi_port_to_transcoder(port);
/* program hst_tx_timeout */
- intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
+ intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
HSTX_TIMEOUT_VALUE_MASK,
HSTX_TIMEOUT_VALUE(hs_tx_timeout));
/* FIXME: DSI_CALIB_TO */
/* program lp_rx_host timeout */
- intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
+ intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
LPRX_TIMEOUT_VALUE_MASK,
LPRX_TIMEOUT_VALUE(lp_rx_timeout));
/* FIXME: DSI_PWAIT_TO */
/* program turn around timeout */
- intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
+ intel_de_rmw(display, DSI_TA_TO(dsi_trans),
TA_TIMEOUT_VALUE_MASK,
TA_TIMEOUT_VALUE(ta_timeout));
}
@@ -1079,7 +1085,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
u32 tmp;
@@ -1091,7 +1097,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
return;
- tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
+ tmp = intel_de_read(display, UTIL_PIN_CTL);
if (enable) {
tmp |= UTIL_PIN_DIRECTION_INPUT;
@@ -1099,7 +1105,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
} else {
tmp &= ~UTIL_PIN_ENABLE;
}
- intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
+ intel_de_write(display, UTIL_PIN_CTL, tmp);
}
static void
@@ -1137,7 +1143,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct mipi_dsi_device *dsi;
enum port port;
@@ -1153,14 +1159,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
* FIXME: This uses the number of DW's currently in the payload
* receive queue. This is probably not what we want here.
*/
- tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
+ tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
tmp &= NUMBER_RX_PLOAD_DW_MASK;
/* multiply "Number Rx Payload DW" by 4 to get max value */
tmp = tmp * 4;
dsi = intel_dsi->dsi_hosts[port]->device;
ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
if (ret < 0)
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"error setting max return pkt size%d\n", tmp);
}
@@ -1220,10 +1226,10 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
enum pipe pipe, bool enable)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
- if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
- intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
+ if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
+ intel_de_rmw(display, CHICKEN_PAR1_1,
IGNORE_KVMR_PIPE_A,
enable ? IGNORE_KVMR_PIPE_A : 0);
}
@@ -1236,13 +1242,13 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
*/
static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
- if (DISPLAY_VER(i915) == 13) {
+ if (DISPLAY_VER(display) == 13) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
+ intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
TGL_DSI_CHKN_LSHS_GB_MASK,
TGL_DSI_CHKN_LSHS_GB(4));
}
@@ -1276,7 +1282,7 @@ static void gen11_dsi_enable(struct intel_atomic_state *state,
static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1285,13 +1291,13 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
dsi_trans = dsi_port_to_transcoder(port);
/* disable transcoder */
- intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ intel_de_rmw(display, TRANSCONF(display, dsi_trans),
TRANSCONF_ENABLE, 0);
/* wait for transcoder to be disabled */
- if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
+ if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
TRANSCONF_STATE_ENABLE, 50))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DSI trancoder not disabled\n");
}
}
@@ -1308,7 +1314,7 @@ static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
enum transcoder dsi_trans;
@@ -1317,29 +1323,29 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
/* disable periodic update mode */
if (is_cmd_mode(intel_dsi)) {
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
+ intel_de_rmw(display, DSI_CMD_FRMCTL(port),
DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
}
/* put dsi link in ULPS */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
+ tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
tmp |= LINK_ENTER_ULPS;
tmp &= ~LINK_ULPS_TYPE_LP11;
- intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
+ intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
- if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
+ if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
LINK_IN_ULPS),
10))
- drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
+ drm_err(display->drm, "DSI link not in ULPS\n");
}
/* disable ddi function */
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans),
TRANS_DDI_FUNC_ENABLE, 0);
}
@@ -1347,8 +1353,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
if (intel_dsi->dual_link) {
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- intel_de_rmw(dev_priv,
- TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
+ intel_de_rmw(display,
+ TRANS_DDI_FUNC_CTL2(display, dsi_trans),
PORT_SYNC_MODE_ENABLE, 0);
}
}
@@ -1356,18 +1362,18 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
static void gen11_dsi_disable_port(struct intel_encoder *encoder)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
gen11_dsi_ungate_clocks(encoder);
for_each_dsi_port(port, intel_dsi->ports) {
- intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
+ intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
- if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
+ if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
DDI_BUF_IS_IDLE),
8))
- drm_err(&dev_priv->drm,
+ drm_err(display->drm,
"DDI port:%c buffer not idle\n",
port_name(port));
}
@@ -1376,6 +1382,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum port port;
@@ -1393,7 +1400,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
/* set mode to DDI */
for_each_dsi_port(port, intel_dsi->ports)
- intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
+ intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
COMBO_PHY_MODE_DSI, 0);
}
@@ -1505,8 +1512,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
{
- struct drm_device *dev = intel_dsi->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
enum transcoder dsi_trans;
u32 val;
@@ -1515,7 +1521,7 @@ static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
else
dsi_trans = TRANSCODER_DSI_0;
- val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
+ val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
}
@@ -1558,7 +1564,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
static void gen11_dsi_sync_state(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_crtc *intel_crtc;
enum pipe pipe;
@@ -1569,9 +1575,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
pipe = intel_crtc->pipe;
/* wa verify 1409054076:icl,jsl,ehl */
- if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
- !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
- drm_dbg_kms(&dev_priv->drm,
+ if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
+ !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
+ drm_dbg_kms(display->drm,
"[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
encoder->base.base.id,
encoder->base.name);
@@ -1580,9 +1586,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
- int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
+ int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
bool use_dsc;
int ret;
@@ -1607,12 +1613,12 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
return ret;
/* DSI specific sanity checks on the common code */
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
+ drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
+ drm_WARN_ON(display->drm,
vdsc_cfg->pic_width % vdsc_cfg->slice_width);
- drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
- drm_WARN_ON(&dev_priv->drm,
+ drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
+ drm_WARN_ON(display->drm,
vdsc_cfg->pic_height % vdsc_cfg->slice_height);
ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
@@ -1628,7 +1634,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_display *display = to_intel_display(encoder);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
struct intel_connector *intel_connector = intel_dsi->attached_connector;
struct drm_display_mode *adjusted_mode =
@@ -1662,7 +1668,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
pipe_config->clock_set = true;
if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
- drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
+ drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
@@ -1680,15 +1686,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
-
- get_dsi_io_power_domains(i915,
- enc_to_intel_dsi(encoder));
+ get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
}
static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
enum pipe *pipe)
{
+ struct intel_display *display = to_intel_display(encoder);
struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
enum transcoder dsi_trans;
@@ -1704,8 +1708,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
for_each_dsi_port(port, intel_dsi->ports) {
dsi_trans = dsi_port_to_transcoder(port);
- tmp = intel_de_read(dev_priv,
- TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
+ tmp = intel_de_read(display,
+ TRANS_DDI_FUNC_CTL(display, dsi_trans));
switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
case TRANS_DDI_EDP_INPUT_A_ON:
*pipe = PIPE_A;
@@ -1720,11 +1724,11 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
*pipe = PIPE_D;
break;
default:
- drm_err(&dev_priv->drm, "Invalid PIPE input\n");
+ drm_err(display->drm, "Invalid PIPE input\n");
goto out;
}
- tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
+ tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
ret = tmp & TRANSCONF_ENABLE;
}
out:
@@ -1834,8 +1838,7 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
{
- struct drm_device *dev = intel_dsi->base.base.dev;
- struct drm_i915_private *dev_priv = to_i915(dev);
+ struct intel_display *display = to_intel_display(&intel_dsi->base);
struct intel_connector *connector = intel_dsi->attached_connector;
struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
u32 tlpx_ns;
@@ -1859,7 +1862,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
*/
prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",
prepare_cnt);
prepare_cnt = ICL_PREPARE_CNT_MAX;
}
@@ -1868,7 +1871,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
ths_prepare_ns, tlpx_ns);
if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
}
@@ -1876,7 +1879,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* trail cnt in escape clocks*/
trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
if (trail_cnt > ICL_TRAIL_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",
trail_cnt);
trail_cnt = ICL_TRAIL_CNT_MAX;
}
@@ -1884,7 +1887,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* tclk pre count in escape clocks */
tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
}
@@ -1893,7 +1896,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
ths_prepare_ns, tlpx_ns);
if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
+ drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",
hs_zero_cnt);
hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
}
@@ -1901,7 +1904,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
/* hs exit zero cnt in escape clocks */
exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
- drm_dbg_kms(&dev_priv->drm,
+ drm_dbg_kms(display->drm,
"exit_zero_cnt out of range (%d)\n",
exit_zero_cnt);
exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
@@ -1943,10 +1946,9 @@ static void icl_dsi_add_properties(struct intel_connector *connector)
fixed_mode->vdisplay);
}
-void icl_dsi_init(struct drm_i915_private *dev_priv,
+void icl_dsi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata)
{
- struct intel_display *display = &dev_priv->display;
struct intel_dsi *intel_dsi;
struct intel_encoder *encoder;
struct intel_connector *intel_connector;
@@ -1974,7 +1976,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
encoder->devdata = devdata;
/* register DSI encoder with DRM subsystem */
- drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
+ drm_encoder_init(display->drm, &encoder->base,
+ &gen11_dsi_encoder_funcs,
DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
@@ -1999,7 +2002,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
encoder->shutdown = intel_dsi_shutdown;
/* register DSI connector with DRM subsystem */
- drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
+ drm_connector_init(display->drm, connector,
+ &gen11_dsi_connector_funcs,
DRM_MODE_CONNECTOR_DSI);
drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
connector->display_info.subpixel_order = SubPixelHorizontalRGB;
@@ -2012,12 +2016,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
- mutex_lock(&dev_priv->drm.mode_config.mutex);
+ mutex_lock(&display->drm->mode_config.mutex);
intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
- mutex_unlock(&dev_priv->drm.mode_config.mutex);
+ mutex_unlock(&display->drm->mode_config.mutex);
if (!intel_panel_preferred_fixed_mode(intel_connector)) {
- drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
+ drm_err(display->drm, "DSI fixed mode info missing\n");
goto err;
}
@@ -2030,10 +2034,10 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
else
intel_dsi->ports = BIT(port);
- if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
- if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
for_each_dsi_port(port, intel_dsi->ports) {
@@ -2047,7 +2051,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
}
if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
- drm_dbg_kms(&dev_priv->drm, "no device found\n");
+ drm_dbg_kms(display->drm, "no device found\n");
goto err;
}
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.h b/drivers/gpu/drm/i915/display/icl_dsi.h
index 43fa7d72eeb1..099fc50e35b4 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.h
+++ b/drivers/gpu/drm/i915/display/icl_dsi.h
@@ -6,11 +6,11 @@
#ifndef __ICL_DSI_H__
#define __ICL_DSI_H__
-struct drm_i915_private;
struct intel_bios_encoder_data;
struct intel_crtc_state;
+struct intel_display;
-void icl_dsi_init(struct drm_i915_private *dev_priv,
+void icl_dsi_init(struct intel_display *display,
const struct intel_bios_encoder_data *devdata);
void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index ff4c633c8546..2bd14e2134be 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4885,7 +4885,7 @@ void intel_ddi_init(struct intel_display *display,
if (!assert_has_icl_dsi(dev_priv))
return;
- icl_dsi_init(dev_priv, devdata);
+ icl_dsi_init(display, devdata);
return;
}
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 10/11] drm/i915/dsi: convert to struct intel_display
2024-10-22 15:57 ` [PATCH 10/11] drm/i915/dsi: " Jani Nikula
@ 2024-10-23 17:26 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 17:26 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:27PM +0300, Jani Nikula wrote:
> struct intel_display will replace struct drm_i915_private as the main
> device pointer for display code. Switch ICL DSI code over to it.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/display/icl_dsi.c | 444 ++++++++++++-----------
> drivers/gpu/drm/i915/display/icl_dsi.h | 4 +-
> drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
> 3 files changed, 227 insertions(+), 223 deletions(-)
I think I need more coffee after this one :)
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
> index 87a27d91d15d..b61f2363d5c2 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.c
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.c
> @@ -51,38 +51,38 @@
> #include "skl_scaler.h"
> #include "skl_universal_plane.h"
>
> -static int header_credits_available(struct drm_i915_private *dev_priv,
> +static int header_credits_available(struct intel_display *display,
> enum transcoder dsi_trans)
> {
> - return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
> + return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
> >> FREE_HEADER_CREDIT_SHIFT;
> }
>
> -static int payload_credits_available(struct drm_i915_private *dev_priv,
> +static int payload_credits_available(struct intel_display *display,
> enum transcoder dsi_trans)
> {
> - return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
> + return (intel_de_read(display, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
> >> FREE_PLOAD_CREDIT_SHIFT;
> }
>
> -static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
> +static bool wait_for_header_credits(struct intel_display *display,
> enum transcoder dsi_trans, int hdr_credit)
> {
> - if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
> + if (wait_for_us(header_credits_available(display, dsi_trans) >=
> hdr_credit, 100)) {
> - drm_err(&dev_priv->drm, "DSI header credits not released\n");
> + drm_err(display->drm, "DSI header credits not released\n");
> return false;
> }
>
> return true;
> }
>
> -static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
> +static bool wait_for_payload_credits(struct intel_display *display,
> enum transcoder dsi_trans, int payld_credit)
> {
> - if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
> + if (wait_for_us(payload_credits_available(display, dsi_trans) >=
> payld_credit, 100)) {
> - drm_err(&dev_priv->drm, "DSI payload credits not released\n");
> + drm_err(display->drm, "DSI payload credits not released\n");
> return false;
> }
>
> @@ -99,7 +99,7 @@ static enum transcoder dsi_port_to_transcoder(enum port port)
>
> static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct mipi_dsi_device *dsi;
> enum port port;
> @@ -109,8 +109,8 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> /* wait for header/payload credits to be released */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
> - wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
> + wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
> + wait_for_payload_credits(display, dsi_trans, MAX_PLOAD_CREDIT);
> }
>
> /* send nop DCS command */
> @@ -120,22 +120,22 @@ static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
> dsi->channel = 0;
> ret = mipi_dsi_dcs_nop(dsi);
> if (ret < 0)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "error sending DCS NOP command\n");
> }
>
> /* wait for header credits to be released */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
> + wait_for_header_credits(display, dsi_trans, MAX_HEADER_CREDIT);
> }
>
> /* wait for LP TX in progress bit to be cleared */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
> + if (wait_for_us(!(intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
> LPTX_IN_PROGRESS), 20))
> - drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
> + drm_err(display->drm, "LPTX bit not cleared\n");
> }
> }
>
> @@ -143,7 +143,7 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
> const struct mipi_dsi_packet *packet)
> {
> struct intel_dsi *intel_dsi = host->intel_dsi;
> - struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
> enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> const u8 *data = packet->payload;
> u32 len = packet->payload_length;
> @@ -151,20 +151,20 @@ static int dsi_send_pkt_payld(struct intel_dsi_host *host,
>
> /* payload queue can accept *256 bytes*, check limit */
> if (len > MAX_PLOAD_CREDIT * 4) {
> - drm_err(&i915->drm, "payload size exceeds max queue limit\n");
> + drm_err(display->drm, "payload size exceeds max queue limit\n");
> return -EINVAL;
> }
>
> for (i = 0; i < len; i += 4) {
> u32 tmp = 0;
>
> - if (!wait_for_payload_credits(i915, dsi_trans, 1))
> + if (!wait_for_payload_credits(display, dsi_trans, 1))
> return -EBUSY;
>
> for (j = 0; j < min_t(u32, len - i, 4); j++)
> tmp |= *data++ << 8 * j;
>
> - intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
> + intel_de_write(display, DSI_CMD_TXPYLD(dsi_trans), tmp);
> }
>
> return 0;
> @@ -175,14 +175,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
> bool enable_lpdt)
> {
> struct intel_dsi *intel_dsi = host->intel_dsi;
> - struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
> enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
> u32 tmp;
>
> - if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
> + if (!wait_for_header_credits(display, dsi_trans, 1))
> return -EBUSY;
>
> - tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
> + tmp = intel_de_read(display, DSI_CMD_TXHDR(dsi_trans));
>
> if (packet->payload)
> tmp |= PAYLOAD_PRESENT;
> @@ -201,15 +201,14 @@ static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
> tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
> tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
> tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
> - intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
> + intel_de_write(display, DSI_CMD_TXHDR(dsi_trans), tmp);
>
> return 0;
> }
>
> void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
> {
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> - struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> + struct intel_display *display = to_intel_display(crtc_state);
> u32 mode_flags;
> enum port port;
>
> @@ -227,12 +226,13 @@ void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
> else
> return;
>
> - intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
> + intel_de_rmw(display, DSI_CMD_FRMCTL(port), 0,
> + DSI_FRAME_UPDATE_REQUEST);
> }
>
> static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum phy phy;
> u32 tmp, mask, val;
> @@ -246,31 +246,31 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
> val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
> RTERM_SELECT(0x6);
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
> tmp &= ~mask;
> tmp |= val;
> - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
> + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
> + intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), mask, val);
>
> mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
> RCOMP_SCALAR_MASK;
> val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
> RCOMP_SCALAR(0x98);
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
> tmp &= ~mask;
> tmp |= val;
> - intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
> + intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
> + intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy), mask, val);
>
> mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
> CURSOR_COEFF_MASK;
> val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
> CURSOR_COEFF(0x3f);
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
> + intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy), mask, val);
>
> /* Bspec: must not use GRP register for write */
> for (lane = 0; lane <= 3; lane++)
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
> + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
> mask, val);
> }
> }
> @@ -278,13 +278,13 @@ static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
> static void configure_dual_link_mode(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
> u32 dss_ctl1;
>
> /* FIXME: Move all DSS handling to intel_vdsc.c */
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
>
> dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
> @@ -294,7 +294,7 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
> dss_ctl2_reg = DSS_CTL2;
> }
>
> - dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
> + dss_ctl1 = intel_de_read(display, dss_ctl1_reg);
> dss_ctl1 |= SPLITTER_ENABLE;
> dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
> dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
> @@ -309,19 +309,19 @@ static void configure_dual_link_mode(struct intel_encoder *encoder,
> dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
>
> if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "DL buffer depth exceed max value\n");
>
> dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
> dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
> - intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
> + intel_de_rmw(display, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
> RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
> } else {
> /* Interleave */
> dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
> }
>
> - intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
> + intel_de_write(display, dss_ctl1_reg, dss_ctl1);
> }
>
> /* aka DSI 8X clock */
> @@ -342,6 +342,7 @@ static int afe_clk(struct intel_encoder *encoder,
> static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> @@ -361,33 +362,34 @@ static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
> + intel_de_write(display, ICL_DSI_ESC_CLK_DIV(port),
> esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
> - intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
> + intel_de_posting_read(display, ICL_DSI_ESC_CLK_DIV(port));
> }
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
> + intel_de_write(display, ICL_DPHY_ESC_CLK_DIV(port),
> esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
> - intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
> + intel_de_posting_read(display, ICL_DPHY_ESC_CLK_DIV(port));
> }
>
> if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
> + intel_de_write(display, ADL_MIPIO_DW(port, 8),
> esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
> - intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
> + intel_de_posting_read(display, ADL_MIPIO_DW(port, 8));
> }
> }
> }
>
> -static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
> - struct intel_dsi *intel_dsi)
> +static void get_dsi_io_power_domains(struct intel_dsi *intel_dsi)
> {
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
> + struct drm_i915_private *dev_priv = to_i915(display->drm);
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
> + drm_WARN_ON(display->drm, intel_dsi->io_wakeref[port]);
> intel_dsi->io_wakeref[port] =
> intel_display_power_get(dev_priv,
> port == PORT_A ?
> @@ -398,15 +400,15 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
>
> static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
> + intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
> 0, COMBO_PHY_MODE_DSI);
>
> - get_dsi_io_power_domains(dev_priv, intel_dsi);
> + get_dsi_io_power_domains(intel_dsi);
> }
>
> static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
> @@ -422,6 +424,7 @@ static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
>
> static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum phy phy;
> @@ -430,32 +433,33 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>
> /* Step 4b(i) set loadgen select for transmit and aux lanes */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
> + intel_de_rmw(display, ICL_PORT_TX_DW4_AUX(phy),
> + LOADGEN_SELECT, 0);
> for (lane = 0; lane <= 3; lane++)
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
> + intel_de_rmw(display, ICL_PORT_TX_DW4_LN(lane, phy),
> LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
> }
>
> /* Step 4b(ii) set latency optimization for transmit and aux lanes */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
> + intel_de_rmw(display, ICL_PORT_TX_DW2_AUX(phy),
> FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_TX_DW2_LN(0, phy));
> tmp &= ~FRC_LATENCY_OPTIM_MASK;
> tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
> - intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
> + intel_de_write(display, ICL_PORT_TX_DW2_GRP(phy), tmp);
>
> /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
> if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv) ||
> - (DISPLAY_VER(dev_priv) >= 12)) {
> - intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
> + (DISPLAY_VER(display) >= 12)) {
> + intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy),
> LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
>
> - tmp = intel_de_read(dev_priv,
> + tmp = intel_de_read(display,
> ICL_PORT_PCS_DW1_LN(0, phy));
> tmp &= ~LATENCY_OPTIM_MASK;
> tmp |= LATENCY_OPTIM_VAL(0x1);
> - intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
> + intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy),
> tmp);
> }
> }
> @@ -464,17 +468,17 @@ static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
>
> static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> u32 tmp;
> enum phy phy;
>
> /* clear common keeper enable bit */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_PCS_DW1_LN(0, phy));
> tmp &= ~COMMON_KEEPER_EN;
> - intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
> - intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
> + intel_de_write(display, ICL_PORT_PCS_DW1_GRP(phy), tmp);
> + intel_de_rmw(display, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
> }
>
> /*
> @@ -483,14 +487,15 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
> * as part of lane phy sequence configuration
> */
> for_each_dsi_phy(phy, intel_dsi->phys)
> - intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
> + intel_de_rmw(display, ICL_PORT_CL_DW5(phy), 0,
> + SUS_CLOCK_CONFIG);
>
> /* Clear training enable to change swing values */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
> tmp &= ~TX_TRAINING_EN;
> - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
> + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
> + intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
> }
>
> /* Program swing and de-emphasis */
> @@ -498,26 +503,26 @@ static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
>
> /* Set training enable to trigger update */
> for_each_dsi_phy(phy, intel_dsi->phys) {
> - tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
> + tmp = intel_de_read(display, ICL_PORT_TX_DW5_LN(0, phy));
> tmp |= TX_TRAINING_EN;
> - intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
> - intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
> + intel_de_write(display, ICL_PORT_TX_DW5_GRP(phy), tmp);
> + intel_de_rmw(display, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
> }
> }
>
> static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
> + intel_de_rmw(display, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
>
> - if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> + if (wait_for_us(!(intel_de_read(display, DDI_BUF_CTL(port)) &
> DDI_BUF_IS_IDLE),
> 500))
> - drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
> + drm_err(display->drm, "DDI port:%c buffer idle\n",
> port_name(port));
> }
> }
> @@ -526,6 +531,7 @@ static void
> gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> @@ -533,12 +539,12 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
>
> /* Program DPHY clock lanes timings */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
> + intel_de_write(display, DPHY_CLK_TIMING_PARAM(port),
> intel_dsi->dphy_reg);
>
> /* Program DPHY data lanes timings */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
> + intel_de_write(display, DPHY_DATA_TIMING_PARAM(port),
> intel_dsi->dphy_data_lane_reg);
>
> /*
> @@ -547,10 +553,10 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
> * a value '0' inside TA_PARAM_REGISTERS otherwise
> * leave all fields at HW default values.
> */
> - if (DISPLAY_VER(dev_priv) == 11) {
> + if (DISPLAY_VER(display) == 11) {
> if (afe_clk(encoder, crtc_state) <= 800000) {
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
> + intel_de_rmw(display, DPHY_TA_TIMING_PARAM(port),
> TA_SURE_MASK,
> TA_SURE_OVERRIDE | TA_SURE(0));
> }
> @@ -558,7 +564,7 @@ gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
>
> if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) {
> for_each_dsi_phy(phy, intel_dsi->phys)
> - intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
> + intel_de_rmw(display, ICL_DPHY_CHKN(phy),
> 0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
> }
> }
> @@ -567,30 +573,30 @@ static void
> gen11_dsi_setup_timings(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
>
> /* Program T-INIT master registers */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
> + intel_de_rmw(display, ICL_DSI_T_INIT_MASTER(port),
> DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
>
> /* shadow register inside display core */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
> + intel_de_write(display, DSI_CLK_TIMING_PARAM(port),
> intel_dsi->dphy_reg);
>
> /* shadow register inside display core */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
> + intel_de_write(display, DSI_DATA_TIMING_PARAM(port),
> intel_dsi->dphy_data_lane_reg);
>
> /* shadow register inside display core */
> - if (DISPLAY_VER(dev_priv) == 11) {
> + if (DISPLAY_VER(display) == 11) {
> if (afe_clk(encoder, crtc_state) <= 800000) {
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
> + intel_de_rmw(display, DSI_TA_TIMING_PARAM(port),
> TA_SURE_MASK,
> TA_SURE_OVERRIDE | TA_SURE(0));
> }
> @@ -600,45 +606,45 @@ gen11_dsi_setup_timings(struct intel_encoder *encoder,
>
> static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> u32 tmp;
> enum phy phy;
>
> - mutex_lock(&dev_priv->display.dpll.lock);
> - tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + mutex_lock(&display->dpll.lock);
> + tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys)
> tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
> - mutex_unlock(&dev_priv->display.dpll.lock);
> + intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
> + mutex_unlock(&display->dpll.lock);
> }
>
> static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> u32 tmp;
> enum phy phy;
>
> - mutex_lock(&dev_priv->display.dpll.lock);
> - tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + mutex_lock(&display->dpll.lock);
> + tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys)
> tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
>
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
> - mutex_unlock(&dev_priv->display.dpll.lock);
> + intel_de_write(display, ICL_DPCLKA_CFGCR0, tmp);
> + mutex_unlock(&display->dpll.lock);
> }
>
> static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> bool clock_enabled = false;
> enum phy phy;
> u32 tmp;
>
> - tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + tmp = intel_de_read(display, ICL_DPCLKA_CFGCR0);
>
> for_each_dsi_phy(phy, intel_dsi->phys) {
> if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
> @@ -651,36 +657,36 @@ static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
> static void gen11_dsi_map_pll(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct intel_shared_dpll *pll = crtc_state->shared_dpll;
> enum phy phy;
> u32 val;
>
> - mutex_lock(&dev_priv->display.dpll.lock);
> + mutex_lock(&display->dpll.lock);
>
> - val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + val = intel_de_read(display, ICL_DPCLKA_CFGCR0);
> for_each_dsi_phy(phy, intel_dsi->phys) {
> val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
> val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
> }
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> + intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
>
> for_each_dsi_phy(phy, intel_dsi->phys) {
> val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
> }
> - intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
> + intel_de_write(display, ICL_DPCLKA_CFGCR0, val);
>
> - intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
> + intel_de_posting_read(display, ICL_DPCLKA_CFGCR0);
>
> - mutex_unlock(&dev_priv->display.dpll.lock);
> + mutex_unlock(&display->dpll.lock);
> }
>
> static void
> gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> const struct intel_crtc_state *pipe_config)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> enum pipe pipe = crtc->pipe;
> @@ -690,7 +696,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
> + tmp = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
>
> if (intel_dsi->eotp_pkt)
> tmp &= ~EOTP_DISABLED;
> @@ -746,7 +752,7 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> }
> }
>
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> if (is_vid_mode(intel_dsi))
> tmp |= BLANKING_PACKET_ENABLE;
> }
> @@ -779,15 +785,15 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> tmp |= TE_SOURCE_GPIO;
> }
>
> - intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> + intel_de_write(display, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
> }
>
> /* enable port sync mode if dual link */
> if (intel_dsi->dual_link) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_rmw(dev_priv,
> - TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
> + intel_de_rmw(display,
> + TRANS_DDI_FUNC_CTL2(display, dsi_trans),
> 0, PORT_SYNC_MODE_ENABLE);
> }
>
> @@ -799,8 +805,8 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
> dsi_trans = dsi_port_to_transcoder(port);
>
> /* select data lane width */
> - tmp = intel_de_read(dev_priv,
> - TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
> + tmp = intel_de_read(display,
> + TRANS_DDI_FUNC_CTL(display, dsi_trans));
> tmp &= ~DDI_PORT_WIDTH_MASK;
> tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
>
> @@ -826,16 +832,16 @@ gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
>
> /* enable DDI buffer */
> tmp |= TRANS_DDI_FUNC_ENABLE;
> - intel_de_write(dev_priv,
> - TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans), tmp);
> + intel_de_write(display,
> + TRANS_DDI_FUNC_CTL(display, dsi_trans), tmp);
> }
>
> /* wait for link ready */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
> + if (wait_for_us((intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans)) &
> LINK_READY), 2500))
> - drm_err(&dev_priv->drm, "DSI link not ready\n");
> + drm_err(display->drm, "DSI link not ready\n");
> }
> }
>
> @@ -843,7 +849,7 @@ static void
> gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> const struct drm_display_mode *adjusted_mode =
> &crtc_state->hw.adjusted_mode;
> @@ -910,17 +916,17 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>
> /* minimum hactive as per bspec: 256 pixels */
> if (adjusted_mode->crtc_hdisplay < 256)
> - drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
> + drm_err(display->drm, "hactive is less then 256 pixels\n");
>
> /* if RGB666 format, then hactive must be multiple of 4 pixels */
> if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "hactive pixels are not multiple of 4\n");
>
> /* program TRANS_HTOTAL register */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_write(dev_priv, TRANS_HTOTAL(dev_priv, dsi_trans),
> + intel_de_write(display, TRANS_HTOTAL(display, dsi_trans),
> HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
> }
>
> @@ -929,12 +935,12 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
> /* BSPEC: hsync size should be atleast 16 pixels */
> if (hsync_size < 16)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "hsync size < 16 pixels\n");
> }
>
> if (hback_porch < 16)
> - drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
> + drm_err(display->drm, "hback porch < 16 pixels\n");
>
> if (intel_dsi->dual_link) {
> hsync_start /= 2;
> @@ -943,8 +949,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_write(dev_priv,
> - TRANS_HSYNC(dev_priv, dsi_trans),
> + intel_de_write(display,
> + TRANS_HSYNC(display, dsi_trans),
> HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
> }
> }
> @@ -958,22 +964,22 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> * struct drm_display_mode.
> * For interlace mode: program required pixel minus 2
> */
> - intel_de_write(dev_priv, TRANS_VTOTAL(dev_priv, dsi_trans),
> + intel_de_write(display, TRANS_VTOTAL(display, dsi_trans),
> VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
> }
>
> if (vsync_end < vsync_start || vsync_end > vtotal)
> - drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
> + drm_err(display->drm, "Invalid vsync_end value\n");
>
> if (vsync_start < vactive)
> - drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
> + drm_err(display->drm, "vsync_start less than vactive\n");
>
> /* program TRANS_VSYNC register for video mode only */
> if (is_vid_mode(intel_dsi)) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_write(dev_priv,
> - TRANS_VSYNC(dev_priv, dsi_trans),
> + intel_de_write(display,
> + TRANS_VSYNC(display, dsi_trans),
> VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
> }
> }
> @@ -987,8 +993,8 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> if (is_vid_mode(intel_dsi)) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_write(dev_priv,
> - TRANS_VSYNCSHIFT(dev_priv, dsi_trans),
> + intel_de_write(display,
> + TRANS_VSYNCSHIFT(display, dsi_trans),
> vsync_shift);
> }
> }
> @@ -999,11 +1005,11 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
> * FIXME get rid of these local hacks and do it right,
> * this will not handle eg. delayed vblank correctly.
> */
> - if (DISPLAY_VER(dev_priv) >= 12) {
> + if (DISPLAY_VER(display) >= 12) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_write(dev_priv,
> - TRANS_VBLANK(dev_priv, dsi_trans),
> + intel_de_write(display,
> + TRANS_VBLANK(display, dsi_trans),
> VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
> }
> }
> @@ -1011,20 +1017,20 @@ gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
>
> static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> enum transcoder dsi_trans;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans), 0,
> + intel_de_rmw(display, TRANSCONF(display, dsi_trans), 0,
> TRANSCONF_ENABLE);
>
> /* wait for transcoder to be enabled */
> - if (intel_de_wait_for_set(dev_priv, TRANSCONF(dev_priv, dsi_trans),
> + if (intel_de_wait_for_set(display, TRANSCONF(display, dsi_trans),
> TRANSCONF_STATE_ENABLE, 10))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "DSI transcoder not enabled\n");
> }
> }
> @@ -1032,7 +1038,7 @@ static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
> static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> enum transcoder dsi_trans;
> @@ -1056,21 +1062,21 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> dsi_trans = dsi_port_to_transcoder(port);
>
> /* program hst_tx_timeout */
> - intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
> + intel_de_rmw(display, DSI_HSTX_TO(dsi_trans),
> HSTX_TIMEOUT_VALUE_MASK,
> HSTX_TIMEOUT_VALUE(hs_tx_timeout));
>
> /* FIXME: DSI_CALIB_TO */
>
> /* program lp_rx_host timeout */
> - intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
> + intel_de_rmw(display, DSI_LPRX_HOST_TO(dsi_trans),
> LPRX_TIMEOUT_VALUE_MASK,
> LPRX_TIMEOUT_VALUE(lp_rx_timeout));
>
> /* FIXME: DSI_PWAIT_TO */
>
> /* program turn around timeout */
> - intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
> + intel_de_rmw(display, DSI_TA_TO(dsi_trans),
> TA_TIMEOUT_VALUE_MASK,
> TA_TIMEOUT_VALUE(ta_timeout));
> }
> @@ -1079,7 +1085,7 @@ static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
> static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
> bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> u32 tmp;
>
> @@ -1091,7 +1097,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
> if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
> return;
>
> - tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
> + tmp = intel_de_read(display, UTIL_PIN_CTL);
>
> if (enable) {
> tmp |= UTIL_PIN_DIRECTION_INPUT;
> @@ -1099,7 +1105,7 @@ static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
> } else {
> tmp &= ~UTIL_PIN_ENABLE;
> }
> - intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
> + intel_de_write(display, UTIL_PIN_CTL, tmp);
> }
>
> static void
> @@ -1137,7 +1143,7 @@ gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
>
> static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct mipi_dsi_device *dsi;
> enum port port;
> @@ -1153,14 +1159,14 @@ static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
> * FIXME: This uses the number of DW's currently in the payload
> * receive queue. This is probably not what we want here.
> */
> - tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
> + tmp = intel_de_read(display, DSI_CMD_RXCTL(dsi_trans));
> tmp &= NUMBER_RX_PLOAD_DW_MASK;
> /* multiply "Number Rx Payload DW" by 4 to get max value */
> tmp = tmp * 4;
> dsi = intel_dsi->dsi_hosts[port]->device;
> ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
> if (ret < 0)
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "error setting max return pkt size%d\n", tmp);
> }
>
> @@ -1220,10 +1226,10 @@ static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
> static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
> enum pipe pipe, bool enable)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
>
> - if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
> - intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
> + if (DISPLAY_VER(display) == 11 && pipe == PIPE_B)
> + intel_de_rmw(display, CHICKEN_PAR1_1,
> IGNORE_KVMR_PIPE_A,
> enable ? IGNORE_KVMR_PIPE_A : 0);
> }
> @@ -1236,13 +1242,13 @@ static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
> */
> static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
>
> - if (DISPLAY_VER(i915) == 13) {
> + if (DISPLAY_VER(display) == 13) {
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
> + intel_de_rmw(display, TGL_DSI_CHKN_REG(port),
> TGL_DSI_CHKN_LSHS_GB_MASK,
> TGL_DSI_CHKN_LSHS_GB(4));
> }
> @@ -1276,7 +1282,7 @@ static void gen11_dsi_enable(struct intel_atomic_state *state,
>
> static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> enum transcoder dsi_trans;
> @@ -1285,13 +1291,13 @@ static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
> dsi_trans = dsi_port_to_transcoder(port);
>
> /* disable transcoder */
> - intel_de_rmw(dev_priv, TRANSCONF(dev_priv, dsi_trans),
> + intel_de_rmw(display, TRANSCONF(display, dsi_trans),
> TRANSCONF_ENABLE, 0);
>
> /* wait for transcoder to be disabled */
> - if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dev_priv, dsi_trans),
> + if (intel_de_wait_for_clear(display, TRANSCONF(display, dsi_trans),
> TRANSCONF_STATE_ENABLE, 50))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "DSI trancoder not disabled\n");
> }
> }
> @@ -1308,7 +1314,7 @@ static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
>
> static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> enum transcoder dsi_trans;
> @@ -1317,29 +1323,29 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> /* disable periodic update mode */
> if (is_cmd_mode(intel_dsi)) {
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
> + intel_de_rmw(display, DSI_CMD_FRMCTL(port),
> DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
> }
>
> /* put dsi link in ULPS */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
> + tmp = intel_de_read(display, DSI_LP_MSG(dsi_trans));
> tmp |= LINK_ENTER_ULPS;
> tmp &= ~LINK_ULPS_TYPE_LP11;
> - intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
> + intel_de_write(display, DSI_LP_MSG(dsi_trans), tmp);
>
> - if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
> + if (wait_for_us((intel_de_read(display, DSI_LP_MSG(dsi_trans)) &
> LINK_IN_ULPS),
> 10))
> - drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
> + drm_err(display->drm, "DSI link not in ULPS\n");
> }
>
> /* disable ddi function */
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_rmw(dev_priv,
> - TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans),
> + intel_de_rmw(display,
> + TRANS_DDI_FUNC_CTL(display, dsi_trans),
> TRANS_DDI_FUNC_ENABLE, 0);
> }
>
> @@ -1347,8 +1353,8 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
> if (intel_dsi->dual_link) {
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - intel_de_rmw(dev_priv,
> - TRANS_DDI_FUNC_CTL2(dev_priv, dsi_trans),
> + intel_de_rmw(display,
> + TRANS_DDI_FUNC_CTL2(display, dsi_trans),
> PORT_SYNC_MODE_ENABLE, 0);
> }
> }
> @@ -1356,18 +1362,18 @@ static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
>
> static void gen11_dsi_disable_port(struct intel_encoder *encoder)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
>
> gen11_dsi_ungate_clocks(encoder);
> for_each_dsi_port(port, intel_dsi->ports) {
> - intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
> + intel_de_rmw(display, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
>
> - if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
> + if (wait_for_us((intel_de_read(display, DDI_BUF_CTL(port)) &
> DDI_BUF_IS_IDLE),
> 8))
> - drm_err(&dev_priv->drm,
> + drm_err(display->drm,
> "DDI port:%c buffer not idle\n",
> port_name(port));
> }
> @@ -1376,6 +1382,7 @@ static void gen11_dsi_disable_port(struct intel_encoder *encoder)
>
> static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum port port;
> @@ -1393,7 +1400,7 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
>
> /* set mode to DDI */
> for_each_dsi_port(port, intel_dsi->ports)
> - intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
> + intel_de_rmw(display, ICL_DSI_IO_MODECTL(port),
> COMBO_PHY_MODE_DSI, 0);
> }
>
> @@ -1505,8 +1512,7 @@ static void gen11_dsi_get_timings(struct intel_encoder *encoder,
>
> static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
> {
> - struct drm_device *dev = intel_dsi->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
> enum transcoder dsi_trans;
> u32 val;
>
> @@ -1515,7 +1521,7 @@ static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
> else
> dsi_trans = TRANSCODER_DSI_0;
>
> - val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
> + val = intel_de_read(display, DSI_TRANS_FUNC_CONF(dsi_trans));
> return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
> }
>
> @@ -1558,7 +1564,7 @@ static void gen11_dsi_get_config(struct intel_encoder *encoder,
> static void gen11_dsi_sync_state(struct intel_encoder *encoder,
> const struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_crtc *intel_crtc;
> enum pipe pipe;
>
> @@ -1569,9 +1575,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
> pipe = intel_crtc->pipe;
>
> /* wa verify 1409054076:icl,jsl,ehl */
> - if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
> - !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
> - drm_dbg_kms(&dev_priv->drm,
> + if (DISPLAY_VER(display) == 11 && pipe == PIPE_B &&
> + !(intel_de_read(display, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
> + drm_dbg_kms(display->drm,
> "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
> encoder->base.base.id,
> encoder->base.name);
> @@ -1580,9 +1586,9 @@ static void gen11_dsi_sync_state(struct intel_encoder *encoder,
> static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
> - int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
> + int dsc_max_bpc = DISPLAY_VER(display) >= 12 ? 12 : 10;
> bool use_dsc;
> int ret;
>
> @@ -1607,12 +1613,12 @@ static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
> return ret;
>
> /* DSI specific sanity checks on the common code */
> - drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
> - drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
> - drm_WARN_ON(&dev_priv->drm,
> + drm_WARN_ON(display->drm, vdsc_cfg->vbr_enable);
> + drm_WARN_ON(display->drm, vdsc_cfg->simple_422);
> + drm_WARN_ON(display->drm,
> vdsc_cfg->pic_width % vdsc_cfg->slice_width);
> - drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
> - drm_WARN_ON(&dev_priv->drm,
> + drm_WARN_ON(display->drm, vdsc_cfg->slice_height < 8);
> + drm_WARN_ON(display->drm,
> vdsc_cfg->pic_height % vdsc_cfg->slice_height);
>
> ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
> @@ -1628,7 +1634,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_display *display = to_intel_display(encoder);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> struct intel_connector *intel_connector = intel_dsi->attached_connector;
> struct drm_display_mode *adjusted_mode =
> @@ -1662,7 +1668,7 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> pipe_config->clock_set = true;
>
> if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
> - drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
> + drm_dbg_kms(display->drm, "Attempting to use DSC failed\n");
>
> pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
>
> @@ -1680,15 +1686,13 @@ static int gen11_dsi_compute_config(struct intel_encoder *encoder,
> static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
> struct intel_crtc_state *crtc_state)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> -
> - get_dsi_io_power_domains(i915,
> - enc_to_intel_dsi(encoder));
> + get_dsi_io_power_domains(enc_to_intel_dsi(encoder));
> }
>
> static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> enum pipe *pipe)
> {
> + struct intel_display *display = to_intel_display(encoder);
> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
> enum transcoder dsi_trans;
> @@ -1704,8 +1708,8 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
>
> for_each_dsi_port(port, intel_dsi->ports) {
> dsi_trans = dsi_port_to_transcoder(port);
> - tmp = intel_de_read(dev_priv,
> - TRANS_DDI_FUNC_CTL(dev_priv, dsi_trans));
> + tmp = intel_de_read(display,
> + TRANS_DDI_FUNC_CTL(display, dsi_trans));
> switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
> case TRANS_DDI_EDP_INPUT_A_ON:
> *pipe = PIPE_A;
> @@ -1720,11 +1724,11 @@ static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
> *pipe = PIPE_D;
> break;
> default:
> - drm_err(&dev_priv->drm, "Invalid PIPE input\n");
> + drm_err(display->drm, "Invalid PIPE input\n");
> goto out;
> }
>
> - tmp = intel_de_read(dev_priv, TRANSCONF(dev_priv, dsi_trans));
> + tmp = intel_de_read(display, TRANSCONF(display, dsi_trans));
> ret = tmp & TRANSCONF_ENABLE;
> }
> out:
> @@ -1834,8 +1838,7 @@ static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
>
> static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> {
> - struct drm_device *dev = intel_dsi->base.base.dev;
> - struct drm_i915_private *dev_priv = to_i915(dev);
> + struct intel_display *display = to_intel_display(&intel_dsi->base);
> struct intel_connector *connector = intel_dsi->attached_connector;
> struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
> u32 tlpx_ns;
> @@ -1859,7 +1862,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> */
> prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
> if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
> + drm_dbg_kms(display->drm, "prepare_cnt out of range (%d)\n",
> prepare_cnt);
> prepare_cnt = ICL_PREPARE_CNT_MAX;
> }
> @@ -1868,7 +1871,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
> ths_prepare_ns, tlpx_ns);
> if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
> clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
> }
> @@ -1876,7 +1879,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> /* trail cnt in escape clocks*/
> trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
> if (trail_cnt > ICL_TRAIL_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
> + drm_dbg_kms(display->drm, "trail_cnt out of range (%d)\n",
> trail_cnt);
> trail_cnt = ICL_TRAIL_CNT_MAX;
> }
> @@ -1884,7 +1887,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> /* tclk pre count in escape clocks */
> tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
> if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
> tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
> }
> @@ -1893,7 +1896,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
> ths_prepare_ns, tlpx_ns);
> if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
> + drm_dbg_kms(display->drm, "hs_zero_cnt out of range (%d)\n",
> hs_zero_cnt);
> hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
> }
> @@ -1901,7 +1904,7 @@ static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
> /* hs exit zero cnt in escape clocks */
> exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
> if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
> - drm_dbg_kms(&dev_priv->drm,
> + drm_dbg_kms(display->drm,
> "exit_zero_cnt out of range (%d)\n",
> exit_zero_cnt);
> exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
> @@ -1943,10 +1946,9 @@ static void icl_dsi_add_properties(struct intel_connector *connector)
> fixed_mode->vdisplay);
> }
>
> -void icl_dsi_init(struct drm_i915_private *dev_priv,
> +void icl_dsi_init(struct intel_display *display,
> const struct intel_bios_encoder_data *devdata)
> {
> - struct intel_display *display = &dev_priv->display;
> struct intel_dsi *intel_dsi;
> struct intel_encoder *encoder;
> struct intel_connector *intel_connector;
> @@ -1974,7 +1976,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
> encoder->devdata = devdata;
>
> /* register DSI encoder with DRM subsystem */
> - drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
> + drm_encoder_init(display->drm, &encoder->base,
> + &gen11_dsi_encoder_funcs,
> DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
>
> encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
> @@ -1999,7 +2002,8 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
> encoder->shutdown = intel_dsi_shutdown;
>
> /* register DSI connector with DRM subsystem */
> - drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
> + drm_connector_init(display->drm, connector,
> + &gen11_dsi_connector_funcs,
> DRM_MODE_CONNECTOR_DSI);
> drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
> connector->display_info.subpixel_order = SubPixelHorizontalRGB;
> @@ -2012,12 +2016,12 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
>
> intel_bios_init_panel_late(display, &intel_connector->panel, encoder->devdata, NULL);
>
> - mutex_lock(&dev_priv->drm.mode_config.mutex);
> + mutex_lock(&display->drm->mode_config.mutex);
> intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
> - mutex_unlock(&dev_priv->drm.mode_config.mutex);
> + mutex_unlock(&display->drm->mode_config.mutex);
>
> if (!intel_panel_preferred_fixed_mode(intel_connector)) {
> - drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
> + drm_err(display->drm, "DSI fixed mode info missing\n");
> goto err;
> }
>
> @@ -2030,10 +2034,10 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
> else
> intel_dsi->ports = BIT(port);
>
> - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
> + if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
> intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
>
> - if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
> + if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
> intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
>
> for_each_dsi_port(port, intel_dsi->ports) {
> @@ -2047,7 +2051,7 @@ void icl_dsi_init(struct drm_i915_private *dev_priv,
> }
>
> if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
> - drm_dbg_kms(&dev_priv->drm, "no device found\n");
> + drm_dbg_kms(display->drm, "no device found\n");
> goto err;
> }
>
> diff --git a/drivers/gpu/drm/i915/display/icl_dsi.h b/drivers/gpu/drm/i915/display/icl_dsi.h
> index 43fa7d72eeb1..099fc50e35b4 100644
> --- a/drivers/gpu/drm/i915/display/icl_dsi.h
> +++ b/drivers/gpu/drm/i915/display/icl_dsi.h
> @@ -6,11 +6,11 @@
> #ifndef __ICL_DSI_H__
> #define __ICL_DSI_H__
>
> -struct drm_i915_private;
> struct intel_bios_encoder_data;
> struct intel_crtc_state;
> +struct intel_display;
>
> -void icl_dsi_init(struct drm_i915_private *dev_priv,
> +void icl_dsi_init(struct intel_display *display,
> const struct intel_bios_encoder_data *devdata);
> void icl_dsi_frame_update(struct intel_crtc_state *crtc_state);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index ff4c633c8546..2bd14e2134be 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -4885,7 +4885,7 @@ void intel_ddi_init(struct intel_display *display,
> if (!assert_has_icl_dsi(dev_priv))
> return;
>
> - icl_dsi_init(dev_priv, devdata);
> + icl_dsi_init(display, devdata);
> return;
> }
>
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (9 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 10/11] drm/i915/dsi: " Jani Nikula
@ 2024-10-22 15:57 ` Jani Nikula
2024-10-23 17:28 ` Rodrigo Vivi
2024-10-22 17:14 ` ✓ CI.Patch_applied: success for drm/i915/display: bunch of struct intel_display conversions Patchwork
` (7 subsequent siblings)
18 siblings, 1 reply; 31+ messages in thread
From: Jani Nikula @ 2024-10-22 15:57 UTC (permalink / raw)
To: intel-gfx, intel-xe; +Cc: jani.nikula
With many of the intel_de_* callers switched over to struct
intel_display, we can remove some of the unnecessary generic wrappers.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/display/intel_de.h | 46 ++++++++++---------------
1 file changed, 18 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
index e017cd4a8168..bb51f974e9e2 100644
--- a/drivers/gpu/drm/i915/display/intel_de.h
+++ b/drivers/gpu/drm/i915/display/intel_de.h
@@ -32,7 +32,7 @@ __intel_de_read(struct intel_display *display, i915_reg_t reg)
#define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
static inline u8
-__intel_de_read8(struct intel_display *display, i915_reg_t reg)
+intel_de_read8(struct intel_display *display, i915_reg_t reg)
{
u8 val;
@@ -44,11 +44,10 @@ __intel_de_read8(struct intel_display *display, i915_reg_t reg)
return val;
}
-#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)
static inline u64
-__intel_de_read64_2x32(struct intel_display *display,
- i915_reg_t lower_reg, i915_reg_t upper_reg)
+intel_de_read64_2x32(struct intel_display *display,
+ i915_reg_t lower_reg, i915_reg_t upper_reg)
{
u64 val;
@@ -63,7 +62,6 @@ __intel_de_read64_2x32(struct intel_display *display,
return val;
}
-#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
static inline void
__intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
@@ -88,12 +86,11 @@ __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
#define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
static inline u32
-____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
- u32 clear, u32 set)
+__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
+ u32 clear, u32 set)
{
return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
}
-#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)
static inline u32
__intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
@@ -112,18 +109,17 @@ __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
#define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
static inline int
-____intel_de_wait_for_register_nowl(struct intel_display *display,
- i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+__intel_de_wait_for_register_nowl(struct intel_display *display,
+ i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
return intel_wait_for_register(__to_uncore(display), reg, mask,
value, timeout);
}
-#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+intel_de_wait(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
int ret;
@@ -136,11 +132,10 @@ __intel_de_wait(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value, unsigned int timeout)
+intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value, unsigned int timeout)
{
int ret;
@@ -153,13 +148,12 @@ __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)
static inline int
-__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
- u32 mask, u32 value,
- unsigned int fast_timeout_us,
- unsigned int slow_timeout_ms, u32 *out_value)
+intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
+ u32 mask, u32 value,
+ unsigned int fast_timeout_us,
+ unsigned int slow_timeout_ms, u32 *out_value)
{
int ret;
@@ -173,7 +167,6 @@ __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
return ret;
}
-#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)
static inline int
__intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
@@ -220,19 +213,16 @@ __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
#define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
static inline u32
-__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
+intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
{
return intel_uncore_read_notrace(__to_uncore(display), reg);
}
-#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)
static inline void
-__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
- u32 val)
+intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
{
intel_uncore_write_notrace(__to_uncore(display), reg, val);
}
-#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
static __always_inline void
intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
--
2.39.5
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers
2024-10-22 15:57 ` [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers Jani Nikula
@ 2024-10-23 17:28 ` Rodrigo Vivi
0 siblings, 0 replies; 31+ messages in thread
From: Rodrigo Vivi @ 2024-10-23 17:28 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-gfx, intel-xe
On Tue, Oct 22, 2024 at 06:57:28PM +0300, Jani Nikula wrote:
> With many of the intel_de_* callers switched over to struct
> intel_display, we can remove some of the unnecessary generic wrappers.
>
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
trusting more your compiler then my tired eyes,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_de.h | 46 ++++++++++---------------
> 1 file changed, 18 insertions(+), 28 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_de.h b/drivers/gpu/drm/i915/display/intel_de.h
> index e017cd4a8168..bb51f974e9e2 100644
> --- a/drivers/gpu/drm/i915/display/intel_de.h
> +++ b/drivers/gpu/drm/i915/display/intel_de.h
> @@ -32,7 +32,7 @@ __intel_de_read(struct intel_display *display, i915_reg_t reg)
> #define intel_de_read(p,...) __intel_de_read(__to_intel_display(p), __VA_ARGS__)
>
> static inline u8
> -__intel_de_read8(struct intel_display *display, i915_reg_t reg)
> +intel_de_read8(struct intel_display *display, i915_reg_t reg)
> {
> u8 val;
>
> @@ -44,11 +44,10 @@ __intel_de_read8(struct intel_display *display, i915_reg_t reg)
>
> return val;
> }
> -#define intel_de_read8(p,...) __intel_de_read8(__to_intel_display(p), __VA_ARGS__)
>
> static inline u64
> -__intel_de_read64_2x32(struct intel_display *display,
> - i915_reg_t lower_reg, i915_reg_t upper_reg)
> +intel_de_read64_2x32(struct intel_display *display,
> + i915_reg_t lower_reg, i915_reg_t upper_reg)
> {
> u64 val;
>
> @@ -63,7 +62,6 @@ __intel_de_read64_2x32(struct intel_display *display,
>
> return val;
> }
> -#define intel_de_read64_2x32(p,...) __intel_de_read64_2x32(__to_intel_display(p), __VA_ARGS__)
>
> static inline void
> __intel_de_posting_read(struct intel_display *display, i915_reg_t reg)
> @@ -88,12 +86,11 @@ __intel_de_write(struct intel_display *display, i915_reg_t reg, u32 val)
> #define intel_de_write(p,...) __intel_de_write(__to_intel_display(p), __VA_ARGS__)
>
> static inline u32
> -____intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
> - u32 clear, u32 set)
> +__intel_de_rmw_nowl(struct intel_display *display, i915_reg_t reg,
> + u32 clear, u32 set)
> {
> return intel_uncore_rmw(__to_uncore(display), reg, clear, set);
> }
> -#define __intel_de_rmw_nowl(p,...) ____intel_de_rmw_nowl(__to_intel_display(p), __VA_ARGS__)
>
> static inline u32
> __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
> @@ -112,18 +109,17 @@ __intel_de_rmw(struct intel_display *display, i915_reg_t reg, u32 clear,
> #define intel_de_rmw(p,...) __intel_de_rmw(__to_intel_display(p), __VA_ARGS__)
>
> static inline int
> -____intel_de_wait_for_register_nowl(struct intel_display *display,
> - i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout)
> +__intel_de_wait_for_register_nowl(struct intel_display *display,
> + i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout)
> {
> return intel_wait_for_register(__to_uncore(display), reg, mask,
> value, timeout);
> }
> -#define __intel_de_wait_for_register_nowl(p,...) ____intel_de_wait_for_register_nowl(__to_intel_display(p), __VA_ARGS__)
>
> static inline int
> -__intel_de_wait(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout)
> +intel_de_wait(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout)
> {
> int ret;
>
> @@ -136,11 +132,10 @@ __intel_de_wait(struct intel_display *display, i915_reg_t reg,
>
> return ret;
> }
> -#define intel_de_wait(p,...) __intel_de_wait(__to_intel_display(p), __VA_ARGS__)
>
> static inline int
> -__intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value, unsigned int timeout)
> +intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value, unsigned int timeout)
> {
> int ret;
>
> @@ -153,13 +148,12 @@ __intel_de_wait_fw(struct intel_display *display, i915_reg_t reg,
>
> return ret;
> }
> -#define intel_de_wait_fw(p,...) __intel_de_wait_fw(__to_intel_display(p), __VA_ARGS__)
>
> static inline int
> -__intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
> - u32 mask, u32 value,
> - unsigned int fast_timeout_us,
> - unsigned int slow_timeout_ms, u32 *out_value)
> +intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
> + u32 mask, u32 value,
> + unsigned int fast_timeout_us,
> + unsigned int slow_timeout_ms, u32 *out_value)
> {
> int ret;
>
> @@ -173,7 +167,6 @@ __intel_de_wait_custom(struct intel_display *display, i915_reg_t reg,
>
> return ret;
> }
> -#define intel_de_wait_custom(p,...) __intel_de_wait_custom(__to_intel_display(p), __VA_ARGS__)
>
> static inline int
> __intel_de_wait_for_set(struct intel_display *display, i915_reg_t reg,
> @@ -220,19 +213,16 @@ __intel_de_write_fw(struct intel_display *display, i915_reg_t reg, u32 val)
> #define intel_de_write_fw(p,...) __intel_de_write_fw(__to_intel_display(p), __VA_ARGS__)
>
> static inline u32
> -__intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
> +intel_de_read_notrace(struct intel_display *display, i915_reg_t reg)
> {
> return intel_uncore_read_notrace(__to_uncore(display), reg);
> }
> -#define intel_de_read_notrace(p,...) __intel_de_read_notrace(__to_intel_display(p), __VA_ARGS__)
>
> static inline void
> -__intel_de_write_notrace(struct intel_display *display, i915_reg_t reg,
> - u32 val)
> +intel_de_write_notrace(struct intel_display *display, i915_reg_t reg, u32 val)
> {
> intel_uncore_write_notrace(__to_uncore(display), reg, val);
> }
> -#define intel_de_write_notrace(p,...) __intel_de_write_notrace(__to_intel_display(p), __VA_ARGS__)
>
> static __always_inline void
> intel_de_write_dsb(struct intel_display *display, struct intel_dsb *dsb,
> --
> 2.39.5
>
^ permalink raw reply [flat|nested] 31+ messages in thread
* ✓ CI.Patch_applied: success for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (10 preceding siblings ...)
2024-10-22 15:57 ` [PATCH 11/11] drm/i915/de: remove unnecessary generic wrappers Jani Nikula
@ 2024-10-22 17:14 ` Patchwork
2024-10-22 17:15 ` ✗ CI.checkpatch: warning " Patchwork
` (6 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:14 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : success
== Summary ==
=== Applying kernel patches on branch 'drm-tip' with base: ===
Base commit: 26b9d5af7030 drm-tip: 2024y-10m-22d-17h-04m-04s UTC integration manifest
=== git am output follows ===
Applying: drm/i915/gmbus: convert to struct intel_display
Applying: drm/i915/cx0: convert to struct intel_display
Applying: drm/i915/dpio: convert to struct intel_display
Applying: drm/i915/hdcp: further conversion to struct intel_display
Applying: drm/i915/dp/hdcp: convert to struct intel_display
Applying: drm/i915/crt: convert to struct intel_display
Applying: drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
Applying: drm/i915/power: convert assert_chv_phy_status() to struct intel_display
Applying: drm/i915/ips: convert to struct intel_display
Applying: drm/i915/dsi: convert to struct intel_display
Applying: drm/i915/de: remove unnecessary generic wrappers
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ CI.checkpatch: warning for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (11 preceding siblings ...)
2024-10-22 17:14 ` ✓ CI.Patch_applied: success for drm/i915/display: bunch of struct intel_display conversions Patchwork
@ 2024-10-22 17:15 ` Patchwork
2024-10-22 17:16 ` ✓ CI.KUnit: success " Patchwork
` (5 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:15 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : warning
== Summary ==
+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
30ab6715fc09baee6cc14cb3c89ad8858688d474
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 211d7d1470e43581e633c9d433c17fb65f648924
Author: Jani Nikula <jani.nikula@intel.com>
Date: Tue Oct 22 18:57:28 2024 +0300
drm/i915/de: remove unnecessary generic wrappers
With many of the intel_de_* callers switched over to struct
intel_display, we can remove some of the unnecessary generic wrappers.
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch 26b9d5af7030484e831dd7335a08ec0c3a22f553 drm-intel
0c3d9eb65df4 drm/i915/gmbus: convert to struct intel_display
55c77acbdece drm/i915/cx0: convert to struct intel_display
-:540: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#540: FILE: drivers/gpu/drm/i915/display/intel_cx0_phy.c:2767:
+ if (intel_de_wait_for_clear(display, XELPDP_PORT_M2P_MSGBUS_CTL(display, port, lane),
total: 0 errors, 1 warnings, 0 checks, 904 lines checked
842c365d9be3 drm/i915/dpio: convert to struct intel_display
-:564: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#564: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:84:
}
+static inline void bxt_dpio_phy_init(struct intel_display *display, enum dpio_phy phy)
-:568: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#568: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:87:
}
+static inline void bxt_dpio_phy_uninit(struct intel_display *display, enum dpio_phy phy)
-:572: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#572: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:90:
}
+static inline bool bxt_dpio_phy_is_enabled(struct intel_display *display,
-:578: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#578: FILE: drivers/gpu/drm/i915/display/intel_dpio_phy.h:95:
}
+static inline bool bxt_dpio_phy_verify_state(struct intel_display *display,
total: 0 errors, 0 warnings, 4 checks, 570 lines checked
86c0a1d0033b drm/i915/hdcp: further conversion to struct intel_display
7083e8741d51 drm/i915/dp/hdcp: convert to struct intel_display
9ab5a12c77e4 drm/i915/crt: convert to struct intel_display
-:217: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#217: FILE: drivers/gpu/drm/i915/display/intel_crt.c:497:
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
-:271: CHECK:MULTIPLE_ASSIGNMENTS: multiple assignments should be avoided
#271: FILE: drivers/gpu/drm/i915/display/intel_crt.c:557:
+ save_adpa = adpa = intel_de_read(display, crt->adpa_reg);
-:672: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#672: FILE: drivers/gpu/drm/i915/display/intel_crt.c:1149:
+ display->fdi.rx_config = intel_de_read(display,
FDI_RX_CTL(PIPE_A)) & fdi_config;
-:701: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations
#701: FILE: drivers/gpu/drm/i915/display/intel_crt.h:26:
}
+static inline void intel_crt_init(struct intel_display *display)
total: 0 errors, 0 warnings, 4 checks, 702 lines checked
a621e4a5db86 drm/i915/display: convert vlv_wait_port_ready() to struct intel_display
3bad5a48b835 drm/i915/power: convert assert_chv_phy_status() to struct intel_display
832465aa0289 drm/i915/ips: convert to struct intel_display
96835280d818 drm/i915/dsi: convert to struct intel_display
-:1365: WARNING:LONG_LINE: line length of 101 exceeds 100 columns
#1365: FILE: drivers/gpu/drm/i915/display/icl_dsi.c:2040:
+ if (drm_WARN_ON(display->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
total: 0 errors, 1 warnings, 0 checks, 1302 lines checked
211d7d1470e4 drm/i915/de: remove unnecessary generic wrappers
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ CI.KUnit: success for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (12 preceding siblings ...)
2024-10-22 17:15 ` ✗ CI.checkpatch: warning " Patchwork
@ 2024-10-22 17:16 ` Patchwork
2024-10-22 17:27 ` ✓ CI.Build: " Patchwork
` (4 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:16 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : success
== Summary ==
+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[17:15:05] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:15:09] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[17:15:37] Starting KUnit Kernel (1/1)...
[17:15:37] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:15:37] =================== guc_dbm (7 subtests) ===================
[17:15:37] [PASSED] test_empty
[17:15:37] [PASSED] test_default
[17:15:37] ======================== test_size ========================
[17:15:37] [PASSED] 4
[17:15:37] [PASSED] 8
[17:15:37] [PASSED] 32
[17:15:37] [PASSED] 256
[17:15:37] ==================== [PASSED] test_size ====================
[17:15:37] ======================= test_reuse ========================
[17:15:37] [PASSED] 4
[17:15:37] [PASSED] 8
[17:15:37] [PASSED] 32
[17:15:37] [PASSED] 256
[17:15:37] =================== [PASSED] test_reuse ====================
[17:15:37] =================== test_range_overlap ====================
[17:15:37] [PASSED] 4
[17:15:37] [PASSED] 8
[17:15:37] [PASSED] 32
[17:15:37] [PASSED] 256
[17:15:37] =============== [PASSED] test_range_overlap ================
[17:15:37] =================== test_range_compact ====================
[17:15:37] [PASSED] 4
[17:15:37] [PASSED] 8
[17:15:37] [PASSED] 32
[17:15:37] [PASSED] 256
[17:15:37] =============== [PASSED] test_range_compact ================
[17:15:37] ==================== test_range_spare =====================
[17:15:37] [PASSED] 4
[17:15:37] [PASSED] 8
[17:15:37] [PASSED] 32
[17:15:37] [PASSED] 256
[17:15:37] ================ [PASSED] test_range_spare =================
[17:15:37] ===================== [PASSED] guc_dbm =====================
[17:15:37] =================== guc_idm (6 subtests) ===================
[17:15:37] [PASSED] bad_init
[17:15:37] [PASSED] no_init
[17:15:37] [PASSED] init_fini
[17:15:37] [PASSED] check_used
[17:15:37] [PASSED] check_quota
[17:15:37] [PASSED] check_all
[17:15:37] ===================== [PASSED] guc_idm =====================
[17:15:37] ================== no_relay (3 subtests) ===================
[17:15:37] [PASSED] xe_drops_guc2pf_if_not_ready
[17:15:37] [PASSED] xe_drops_guc2vf_if_not_ready
[17:15:37] [PASSED] xe_rejects_send_if_not_ready
[17:15:37] ==================== [PASSED] no_relay =====================
[17:15:37] ================== pf_relay (14 subtests) ==================
[17:15:37] [PASSED] pf_rejects_guc2pf_too_short
[17:15:37] [PASSED] pf_rejects_guc2pf_too_long
[17:15:37] [PASSED] pf_rejects_guc2pf_no_payload
[17:15:37] [PASSED] pf_fails_no_payload
[17:15:37] [PASSED] pf_fails_bad_origin
[17:15:37] [PASSED] pf_fails_bad_type
[17:15:37] [PASSED] pf_txn_reports_error
[17:15:37] [PASSED] pf_txn_sends_pf2guc
[17:15:37] [PASSED] pf_sends_pf2guc
[17:15:37] [SKIPPED] pf_loopback_nop
[17:15:37] [SKIPPED] pf_loopback_echo
[17:15:37] [SKIPPED] pf_loopback_fail
[17:15:37] [SKIPPED] pf_loopback_busy
[17:15:37] [SKIPPED] pf_loopback_retry
[17:15:37] ==================== [PASSED] pf_relay =====================
[17:15:37] ================== vf_relay (3 subtests) ===================
[17:15:37] [PASSED] vf_rejects_guc2vf_too_short
[17:15:37] [PASSED] vf_rejects_guc2vf_too_long
[17:15:37] [PASSED] vf_rejects_guc2vf_no_payload
[17:15:37] ==================== [PASSED] vf_relay =====================
[17:15:37] ================= pf_service (11 subtests) =================
[17:15:37] [PASSED] pf_negotiate_any
[17:15:37] [PASSED] pf_negotiate_base_match
[17:15:37] [PASSED] pf_negotiate_base_newer
[17:15:37] [PASSED] pf_negotiate_base_next
[17:15:37] [SKIPPED] pf_negotiate_base_older
[17:15:37] [PASSED] pf_negotiate_base_prev
[17:15:37] [PASSED] pf_negotiate_latest_match
[17:15:37] [PASSED] pf_negotiate_latest_newer
[17:15:37] [PASSED] pf_negotiate_latest_next
[17:15:37] [SKIPPED] pf_negotiate_latest_older
[17:15:37] [SKIPPED] pf_negotiate_latest_prev
[17:15:37] =================== [PASSED] pf_service ====================
[17:15:37] ===================== lmtt (1 subtest) =====================
[17:15:37] ======================== test_ops =========================
[17:15:37] [PASSED] 2-level
[17:15:37] [PASSED] multi-level
[17:15:37] ==================== [PASSED] test_ops =====================
[17:15:37] ====================== [PASSED] lmtt =======================
[17:15:37] =================== xe_mocs (2 subtests) ===================
[17:15:37] ================ xe_live_mocs_kernel_kunit ================
[17:15:37] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[17:15:37] ================ xe_live_mocs_reset_kunit =================
[17:15:37] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[17:15:37] ==================== [SKIPPED] xe_mocs =====================
[17:15:37] ================= xe_migrate (2 subtests) ==================
[17:15:37] ================= xe_migrate_sanity_kunit =================
[17:15:37] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[17:15:37] ================== xe_validate_ccs_kunit ==================
[17:15:37] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[17:15:37] =================== [SKIPPED] xe_migrate ===================
[17:15:37] ================== xe_dma_buf (1 subtest) ==================
[17:15:37] ==================== xe_dma_buf_kunit =====================
[17:15:37] ================ [SKIPPED] xe_dma_buf_kunit ================
[17:15:37] =================== [SKIPPED] xe_dma_buf ===================
[17:15:37] ==================== xe_bo (3 subtests) ====================
[17:15:37] ================== xe_ccs_migrate_kunit ===================
[17:15:37] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[17:15:37] ==================== xe_bo_evict_kunit ====================
[17:15:37] =============== [SKIPPED] xe_bo_evict_kunit ================
[17:15:37] =================== xe_bo_shrink_kunit ====================
[17:15:37] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[17:15:37] ===================== [SKIPPED] xe_bo ======================
[17:15:37] ==================== args (11 subtests) ====================
[17:15:37] [PASSED] count_args_test
[17:15:37] [PASSED] call_args_example
[17:15:37] [PASSED] call_args_test
[17:15:37] [PASSED] drop_first_arg_example
[17:15:37] [PASSED] drop_first_arg_test
[17:15:37] [PASSED] first_arg_example
[17:15:37] [PASSED] first_arg_test
[17:15:37] [PASSED] last_arg_example
[17:15:37] [PASSED] last_arg_test
[17:15:37] [PASSED] pick_arg_example
[17:15:37] [PASSED] sep_comma_examplestty: 'standard input': Inappropriate ioctl for device
[17:15:37] ====================== [PASSED] args =======================
[17:15:37] =================== xe_pci (2 subtests) ====================
[17:15:37] [PASSED] xe_gmdid_graphics_ip
[17:15:37] [PASSED] xe_gmdid_media_ip
[17:15:37] ===================== [PASSED] xe_pci ======================
[17:15:37] =================== xe_rtp (2 subtests) ====================
[17:15:37] =============== xe_rtp_process_to_sr_tests ================
[17:15:37] [PASSED] coalesce-same-reg
[17:15:37] [PASSED] no-match-no-add
[17:15:37] [PASSED] match-or
[17:15:37] [PASSED] match-or-xfail
[17:15:37] [PASSED] no-match-no-add-multiple-rules
[17:15:37] [PASSED] two-regs-two-entries
[17:15:37] [PASSED] clr-one-set-other
[17:15:37] [PASSED] set-field
[17:15:37] [PASSED] conflict-duplicate
[17:15:37] [PASSED] conflict-not-disjoint
[17:15:37] [PASSED] conflict-reg-type
[17:15:37] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[17:15:37] ================== xe_rtp_process_tests ===================
[17:15:37] [PASSED] active1
[17:15:37] [PASSED] active2
[17:15:37] [PASSED] active-inactive
[17:15:37] [PASSED] inactive-active
[17:15:37] [PASSED] inactive-1st_or_active-inactive
[17:15:37] [PASSED] inactive-2nd_or_active-inactive
[17:15:37] [PASSED] inactive-last_or_active-inactive
[17:15:37] [PASSED] inactive-no_or_active-inactive
[17:15:37] ============== [PASSED] xe_rtp_process_tests ===============
[17:15:37] ===================== [PASSED] xe_rtp ======================
[17:15:37] ==================== xe_wa (1 subtest) =====================
[17:15:37] ======================== xe_wa_gt =========================
[17:15:37] [PASSED] TIGERLAKE (B0)
[17:15:37] [PASSED] DG1 (A0)
[17:15:37] [PASSED] DG1 (B0)
[17:15:37] [PASSED] ALDERLAKE_S (A0)
[17:15:37] [PASSED] ALDERLAKE_S (B0)
[17:15:37] [PASSED] ALDERLAKE_S (C0)
[17:15:37] [PASSED] ALDERLAKE_S (D0)
[17:15:37] [PASSED] ALDERLAKE_P (A0)
[17:15:37] [PASSED] ALDERLAKE_P (B0)
[17:15:37] [PASSED] ALDERLAKE_P (C0)
[17:15:37] [PASSED] ALDERLAKE_S_RPLS (D0)
[17:15:37] [PASSED] ALDERLAKE_P_RPLU (E0)
[17:15:37] [PASSED] DG2_G10 (C0)
[17:15:37] [PASSED] DG2_G11 (B1)
[17:15:37] [PASSED] DG2_G12 (A1)
[17:15:37] [PASSED] METEORLAKE (g:A0, m:A0)
[17:15:37] [PASSED] METEORLAKE (g:A0, m:A0)
[17:15:37] [PASSED] METEORLAKE (g:A0, m:A0)
[17:15:37] [PASSED] LUNARLAKE (g:A0, m:A0)
[17:15:37] [PASSED] LUNARLAKE (g:B0, m:A0)
[17:15:37] [PASSED] BATTLEMAGE (g:A0, m:A1)
[17:15:37] ==================== [PASSED] xe_wa_gt =====================
[17:15:37] ====================== [PASSED] xe_wa ======================
[17:15:37] ============================================================
[17:15:37] Testing complete. Ran 122 tests: passed: 106, skipped: 16
[17:15:37] Elapsed time: 32.563s total, 4.433s configuring, 27.864s building, 0.220s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[17:15:37] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:15:39] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
../lib/iomap.c:156:5: warning: no previous prototype for ‘ioread64_lo_hi’ [-Wmissing-prototypes]
156 | u64 ioread64_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:163:5: warning: no previous prototype for ‘ioread64_hi_lo’ [-Wmissing-prototypes]
163 | u64 ioread64_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~
../lib/iomap.c:170:5: warning: no previous prototype for ‘ioread64be_lo_hi’ [-Wmissing-prototypes]
170 | u64 ioread64be_lo_hi(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:178:5: warning: no previous prototype for ‘ioread64be_hi_lo’ [-Wmissing-prototypes]
178 | u64 ioread64be_hi_lo(const void __iomem *addr)
| ^~~~~~~~~~~~~~~~
../lib/iomap.c:264:6: warning: no previous prototype for ‘iowrite64_lo_hi’ [-Wmissing-prototypes]
264 | void iowrite64_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:272:6: warning: no previous prototype for ‘iowrite64_hi_lo’ [-Wmissing-prototypes]
272 | void iowrite64_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~
../lib/iomap.c:280:6: warning: no previous prototype for ‘iowrite64be_lo_hi’ [-Wmissing-prototypes]
280 | void iowrite64be_lo_hi(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
../lib/iomap.c:288:6: warning: no previous prototype for ‘iowrite64be_hi_lo’ [-Wmissing-prototypes]
288 | void iowrite64be_hi_lo(u64 val, void __iomem *addr)
| ^~~~~~~~~~~~~~~~~
[17:16:01] Starting KUnit Kernel (1/1)...
[17:16:01] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:01] ================== drm_buddy (7 subtests) ==================
[17:16:01] [PASSED] drm_test_buddy_alloc_limit
[17:16:01] [PASSED] drm_test_buddy_alloc_optimistic
[17:16:01] [PASSED] drm_test_buddy_alloc_pessimistic
[17:16:01] [PASSED] drm_test_buddy_alloc_pathological
[17:16:01] [PASSED] drm_test_buddy_alloc_contiguous
[17:16:01] [PASSED] drm_test_buddy_alloc_clear
[17:16:01] [PASSED] drm_test_buddy_alloc_range_bias
[17:16:01] ==================== [PASSED] drm_buddy ====================
[17:16:01] ============= drm_cmdline_parser (40 subtests) =============
[17:16:01] [PASSED] drm_test_cmdline_force_d_only
[17:16:01] [PASSED] drm_test_cmdline_force_D_only_dvi
[17:16:01] [PASSED] drm_test_cmdline_force_D_only_hdmi
[17:16:01] [PASSED] drm_test_cmdline_force_D_only_not_digital
[17:16:01] [PASSED] drm_test_cmdline_force_e_only
[17:16:01] [PASSED] drm_test_cmdline_res
[17:16:01] [PASSED] drm_test_cmdline_res_vesa
[17:16:01] [PASSED] drm_test_cmdline_res_vesa_rblank
[17:16:01] [PASSED] drm_test_cmdline_res_rblank
[17:16:01] [PASSED] drm_test_cmdline_res_bpp
[17:16:01] [PASSED] drm_test_cmdline_res_refresh
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[17:16:01] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[17:16:01] [PASSED] drm_test_cmdline_res_margins_force_on
[17:16:01] [PASSED] drm_test_cmdline_res_vesa_margins
[17:16:01] [PASSED] drm_test_cmdline_name
[17:16:01] [PASSED] drm_test_cmdline_name_bpp
[17:16:01] [PASSED] drm_test_cmdline_name_option
[17:16:01] [PASSED] drm_test_cmdline_name_bpp_option
[17:16:01] [PASSED] drm_test_cmdline_rotate_0
[17:16:01] [PASSED] drm_test_cmdline_rotate_90
[17:16:01] [PASSED] drm_test_cmdline_rotate_180
[17:16:01] [PASSED] drm_test_cmdline_rotate_270
[17:16:01] [PASSED] drm_test_cmdline_hmirror
[17:16:01] [PASSED] drm_test_cmdline_vmirror
[17:16:01] [PASSED] drm_test_cmdline_margin_options
[17:16:01] [PASSED] drm_test_cmdline_multiple_options
[17:16:01] [PASSED] drm_test_cmdline_bpp_extra_and_option
[17:16:01] [PASSED] drm_test_cmdline_extra_and_option
[17:16:01] [PASSED] drm_test_cmdline_freestanding_options
[17:16:01] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[17:16:01] [PASSED] drm_test_cmdline_panel_orientation
[17:16:01] ================ drm_test_cmdline_invalid =================
[17:16:01] [PASSED] margin_only
[17:16:01] [PASSED] interlace_only
[17:16:01] [PASSED] res_missing_x
[17:16:01] [PASSED] res_missing_y
[17:16:01] [PASSED] res_bad_y
[17:16:01] [PASSED] res_missing_y_bpp
[17:16:01] [PASSED] res_bad_bpp
[17:16:01] [PASSED] res_bad_refresh
[17:16:01] [PASSED] res_bpp_refresh_force_on_off
[17:16:01] [PASSED] res_invalid_mode
[17:16:01] [PASSED] res_bpp_wrong_place_mode
[17:16:01] [PASSED] name_bpp_refresh
[17:16:01] [PASSED] name_refresh
[17:16:01] [PASSED] name_refresh_wrong_mode
[17:16:01] [PASSED] name_refresh_invalid_mode
[17:16:01] [PASSED] rotate_multiple
[17:16:01] [PASSED] rotate_invalid_val
[17:16:01] [PASSED] rotate_truncated
[17:16:01] [PASSED] invalid_option
[17:16:01] [PASSED] invalid_tv_option
[17:16:01] [PASSED] truncated_tv_option
[17:16:01] ============ [PASSED] drm_test_cmdline_invalid =============
[17:16:01] =============== drm_test_cmdline_tv_options ===============
[17:16:01] [PASSED] NTSC
[17:16:01] [PASSED] NTSC_443
[17:16:01] [PASSED] NTSC_J
[17:16:01] [PASSED] PAL
[17:16:01] [PASSED] PAL_M
[17:16:01] [PASSED] PAL_N
[17:16:01] [PASSED] SECAM
[17:16:01] [PASSED] MONO_525
[17:16:01] [PASSED] MONO_625
[17:16:01] =========== [PASSED] drm_test_cmdline_tv_options ===========
[17:16:01] =============== [PASSED] drm_cmdline_parser ================
[17:16:01] ========== drmm_connector_hdmi_init (19 subtests) ==========
[17:16:01] [PASSED] drm_test_connector_hdmi_init_valid
[17:16:01] [PASSED] drm_test_connector_hdmi_init_bpc_8
[17:16:01] [PASSED] drm_test_connector_hdmi_init_bpc_10
[17:16:01] [PASSED] drm_test_connector_hdmi_init_bpc_12
[17:16:01] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[17:16:01] [PASSED] drm_test_connector_hdmi_init_bpc_null
[17:16:01] [PASSED] drm_test_connector_hdmi_init_formats_empty
[17:16:01] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[17:16:01] [PASSED] drm_test_connector_hdmi_init_null_ddc
[17:16:01] [PASSED] drm_test_connector_hdmi_init_null_product
[17:16:01] [PASSED] drm_test_connector_hdmi_init_null_vendor
[17:16:01] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[17:16:01] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[17:16:01] [PASSED] drm_test_connector_hdmi_init_product_valid
[17:16:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[17:16:01] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[17:16:01] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[17:16:01] ========= drm_test_connector_hdmi_init_type_valid =========
[17:16:01] [PASSED] HDMI-A
[17:16:01] [PASSED] HDMI-B
[17:16:01] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[17:16:01] ======== drm_test_connector_hdmi_init_type_invalid ========
[17:16:01] [PASSED] Unknown
[17:16:01] [PASSED] VGA
[17:16:01] [PASSED] DVI-I
[17:16:01] [PASSED] DVI-D
[17:16:01] [PASSED] DVI-A
[17:16:01] [PASSED] Composite
[17:16:01] [PASSED] SVIDEO
[17:16:01] [PASSED] LVDS
[17:16:01] [PASSED] Component
[17:16:01] [PASSED] DIN
[17:16:01] [PASSED] DP
[17:16:01] [PASSED] TV
[17:16:01] [PASSED] eDP
[17:16:01] [PASSED] Virtual
[17:16:01] [PASSED] DSI
[17:16:01] [PASSED] DPI
[17:16:01] [PASSED] Writeback
[17:16:01] [PASSED] SPI
[17:16:01] [PASSED] USB
[17:16:01] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[17:16:01] ============ [PASSED] drmm_connector_hdmi_init =============
[17:16:01] ============= drmm_connector_init (3 subtests) =============
[17:16:01] [PASSED] drm_test_drmm_connector_init
[17:16:01] [PASSED] drm_test_drmm_connector_init_null_ddc
[17:16:01] ========= drm_test_drmm_connector_init_type_valid =========
[17:16:01] [PASSED] Unknown
[17:16:01] [PASSED] VGA
[17:16:01] [PASSED] DVI-I
[17:16:01] [PASSED] DVI-D
[17:16:01] [PASSED] DVI-A
[17:16:01] [PASSED] Composite
[17:16:01] [PASSED] SVIDEO
[17:16:01] [PASSED] LVDS
[17:16:01] [PASSED] Component
[17:16:01] [PASSED] DIN
[17:16:01] [PASSED] DP
[17:16:01] [PASSED] HDMI-A
[17:16:01] [PASSED] HDMI-B
[17:16:01] [PASSED] TV
[17:16:01] [PASSED] eDP
[17:16:01] [PASSED] Virtual
[17:16:01] [PASSED] DSI
[17:16:01] [PASSED] DPI
[17:16:01] [PASSED] Writeback
[17:16:01] [PASSED] SPI
[17:16:01] [PASSED] USB
[17:16:01] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[17:16:01] =============== [PASSED] drmm_connector_init ===============
[17:16:01] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[17:16:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[17:16:01] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[17:16:01] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[17:16:01] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[17:16:01] ========== drm_test_get_tv_mode_from_name_valid ===========
[17:16:01] [PASSED] NTSC
[17:16:01] [PASSED] NTSC-443
[17:16:01] [PASSED] NTSC-J
[17:16:01] [PASSED] PAL
[17:16:01] [PASSED] PAL-M
[17:16:01] [PASSED] PAL-N
[17:16:01] [PASSED] SECAM
[17:16:01] [PASSED] Mono
[17:16:01] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[17:16:01] [PASSED] drm_test_get_tv_mode_from_name_truncated
[17:16:01] ============ [PASSED] drm_get_tv_mode_from_name ============
[17:16:01] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[17:16:01] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[17:16:01] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid =
[17:16:01] [PASSED] VIC 96
[17:16:01] [PASSED] VIC 97
[17:16:01] [PASSED] VIC 101
[17:16:01] [PASSED] VIC 102
[17:16:01] [PASSED] VIC 106
[17:16:01] [PASSED] VIC 107
[17:16:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[17:16:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[17:16:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[17:16:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[17:16:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[17:16:01] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[17:16:01] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[17:16:01] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[17:16:01] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name ====
[17:16:01] [PASSED] Automatic
[17:16:01] [PASSED] Full
[17:16:01] [PASSED] Limited 16:235
[17:16:01] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[17:16:01] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[17:16:01] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[17:16:01] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[17:16:01] === drm_test_drm_hdmi_connector_get_output_format_name ====
[17:16:01] [PASSED] RGB
[17:16:01] [PASSED] YUV 4:2:0
[17:16:01] [PASSED] YUV 4:2:2
[17:16:01] [PASSED] YUV 4:4:4
[17:16:01] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[17:16:01] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[17:16:01] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[17:16:01] ============= drm_damage_helper (21 subtests) ==============
[17:16:01] [PASSED] drm_test_damage_iter_no_damage
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_src_moved
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_not_visible
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[17:16:01] [PASSED] drm_test_damage_iter_no_damage_no_fb
[17:16:01] [PASSED] drm_test_damage_iter_simple_damage
[17:16:01] [PASSED] drm_test_damage_iter_single_damage
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_outside_src
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_src_moved
[17:16:01] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[17:16:01] [PASSED] drm_test_damage_iter_damage
[17:16:01] [PASSED] drm_test_damage_iter_damage_one_intersect
[17:16:01] [PASSED] drm_test_damage_iter_damage_one_outside
[17:16:01] [PASSED] drm_test_damage_iter_damage_src_moved
[17:16:01] [PASSED] drm_test_damage_iter_damage_not_visible
[17:16:01] ================ [PASSED] drm_damage_helper ================
[17:16:01] ============== drm_dp_mst_helper (3 subtests) ==============
[17:16:01] ============== drm_test_dp_mst_calc_pbn_mode ==============
[17:16:01] [PASSED] Clock 154000 BPP 30 DSC disabled
[17:16:01] [PASSED] Clock 234000 BPP 30 DSC disabled
[17:16:01] [PASSED] Clock 297000 BPP 24 DSC disabled
[17:16:01] [PASSED] Clock 332880 BPP 24 DSC enabled
[17:16:01] [PASSED] Clock 324540 BPP 24 DSC enabled
[17:16:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[17:16:01] ============== drm_test_dp_mst_calc_pbn_div ===============
[17:16:01] [PASSED] Link rate 2000000 lane count 4
[17:16:01] [PASSED] Link rate 2000000 lane count 2
[17:16:01] [PASSED] Link rate 2000000 lane count 1
[17:16:01] [PASSED] Link rate 1350000 lane count 4
[17:16:01] [PASSED] Link rate 1350000 lane count 2
[17:16:01] [PASSED] Link rate 1350000 lane count 1
[17:16:01] [PASSED] Link rate 1000000 lane count 4
[17:16:01] [PASSED] Link rate 1000000 lane count 2
[17:16:01] [PASSED] Link rate 1000000 lane count 1
[17:16:01] [PASSED] Link rate 810000 lane count 4
[17:16:01] [PASSED] Link rate 810000 lane count 2
[17:16:01] [PASSED] Link rate 810000 lane count 1
[17:16:01] [PASSED] Link rate 540000 lane count 4
[17:16:01] [PASSED] Link rate 540000 lane count 2
[17:16:01] [PASSED] Link rate 540000 lane count 1
[17:16:01] [PASSED] Link rate 270000 lane count 4
[17:16:01] [PASSED] Link rate 270000 lane count 2
[17:16:01] [PASSED] Link rate 270000 lane count 1
[17:16:01] [PASSED] Link rate 162000 lane count 4
[17:16:01] [PASSED] Link rate 162000 lane count 2
[17:16:01] [PASSED] Link rate 162000 lane count 1
[17:16:01] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[17:16:01] ========= drm_test_dp_mst_sideband_msg_req_decode =========
[17:16:01] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[17:16:01] [PASSED] DP_POWER_UP_PHY with port number
[17:16:01] [PASSED] DP_POWER_DOWN_PHY with port number
[17:16:01] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[17:16:01] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[17:16:01] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[17:16:01] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[17:16:01] [PASSED] DP_QUERY_PAYLOAD with port number
[17:16:01] [PASSED] DP_QUERY_PAYLOAD with VCPI
[17:16:01] [PASSED] DP_REMOTE_DPCD_READ with port number
[17:16:01] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[17:16:01] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[17:16:01] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[17:16:01] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[17:16:01] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[17:16:01] [PASSED] DP_REMOTE_I2C_READ with port number
[17:16:01] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[17:16:01] [PASSED] DP_REMOTE_I2C_READ with transactions array
[17:16:01] [PASSED] DP_REMOTE_I2C_WRITE with port number
[17:16:01] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[17:16:01] [PASSED] DP_REMOTE_I2C_WRITE with data array
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[17:16:01] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[17:16:01] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[17:16:01] ================ [PASSED] drm_dp_mst_helper ================
[17:16:01] ================== drm_exec (7 subtests) ===================
[17:16:01] [PASSED] sanitycheck
[17:16:01] [PASSED] test_lock
[17:16:01] [PASSED] test_lock_unlock
[17:16:01] [PASSED] test_duplicates
[17:16:01] [PASSED] test_prepare
[17:16:01] [PASSED] test_prepare_array
[17:16:01] [PASSED] test_multiple_loops
[17:16:01] ==================== [PASSED] drm_exec =====================
[17:16:01] =========== drm_format_helper_test (17 subtests) ===========
[17:16:01] ============== drm_test_fb_xrgb8888_to_gray8 ==============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[17:16:01] ============= drm_test_fb_xrgb8888_to_rgb332 ==============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[17:16:01] ============= drm_test_fb_xrgb8888_to_rgb565 ==============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[17:16:01] ============ drm_test_fb_xrgb8888_to_xrgb1555 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[17:16:01] ============ drm_test_fb_xrgb8888_to_argb1555 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[17:16:01] ============ drm_test_fb_xrgb8888_to_rgba5551 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[17:16:01] ============= drm_test_fb_xrgb8888_to_rgb888 ==============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[17:16:01] ============ drm_test_fb_xrgb8888_to_argb8888 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[17:16:01] =========== drm_test_fb_xrgb8888_to_xrgb2101010 ===========
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[17:16:01] =========== drm_test_fb_xrgb8888_to_argb2101010 ===========
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[17:16:01] ============== drm_test_fb_xrgb8888_to_mono ===============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[17:16:01] ==================== drm_test_fb_swab =====================
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ================ [PASSED] drm_test_fb_swab =================
[17:16:01] ============ drm_test_fb_xrgb8888_to_xbgr8888 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[17:16:01] ============ drm_test_fb_xrgb8888_to_abgr8888 =============
[17:16:01] [PASSED] single_pixel_source_buffer
[17:16:01] [PASSED] single_pixel_clip_rectangle
[17:16:01] [PASSED] well_known_colors
[17:16:01] [PASSED] destination_pitch
[17:16:01] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[17:16:01] ================= drm_test_fb_clip_offset =================
[17:16:01] [PASSED] pass through
[17:16:01] [PASSED] horizontal offset
[17:16:01] [PASSED] vertical offset
[17:16:01] [PASSED] horizontal and vertical offset
[17:16:01] [PASSED] horizontal offset (custom pitch)
[17:16:01] [PASSED] vertical offset (custom pitch)
[17:16:01] [PASSED] horizontal and vertical offset (custom pitch)
[17:16:01] ============= [PASSED] drm_test_fb_clip_offset =============
[17:16:01] ============== drm_test_fb_build_fourcc_list ==============
[17:16:01] [PASSED] no native formats
[17:16:01] [PASSED] XRGB8888 as native format
[17:16:01] [PASSED] remove duplicates
[17:16:01] [PASSED] convert alpha formats
[17:16:01] [PASSED] random formats
[17:16:01] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[17:16:01] =================== drm_test_fb_memcpy ====================
[17:16:01] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[17:16:01] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[17:16:01] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[17:16:01] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[17:16:01] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[17:16:01] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[17:16:01] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[17:16:01] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[17:16:01] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[17:16:01] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[17:16:01] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[17:16:01] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[17:16:01] =============== [PASSED] drm_test_fb_memcpy ================
[17:16:01] ============= [PASSED] drm_format_helper_test ==============
[17:16:01] ================= drm_format (18 subtests) =================
[17:16:01] [PASSED] drm_test_format_block_width_invalid
[17:16:01] [PASSED] drm_test_format_block_width_one_plane
[17:16:01] [PASSED] drm_test_format_block_width_two_plane
[17:16:01] [PASSED] drm_test_format_block_width_three_plane
[17:16:01] [PASSED] drm_test_format_block_width_tiled
[17:16:01] [PASSED] drm_test_format_block_height_invalid
[17:16:01] [PASSED] drm_test_format_block_height_one_plane
[17:16:01] [PASSED] drm_test_format_block_height_two_plane
[17:16:01] [PASSED] drm_test_format_block_height_three_plane
[17:16:01] [PASSED] drm_test_format_block_height_tiled
[17:16:01] [PASSED] drm_test_format_min_pitch_invalid
[17:16:01] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[17:16:01] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[17:16:01] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[17:16:01] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[17:16:01] [PASSED] drm_test_format_min_pitch_two_plane
[17:16:01] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[17:16:01] [PASSED] drm_test_format_min_pitch_tiled
[17:16:01] =================== [PASSED] drm_format ====================
[17:16:01] ============== drm_framebuffer (10 subtests) ===============
[17:16:01] ========== drm_test_framebuffer_check_src_coords ==========
[17:16:01] [PASSED] Success: source fits into fb
[17:16:01] [PASSED] Fail: overflowing fb with x-axis coordinate
[17:16:01] [PASSED] Fail: overflowing fb with y-axis coordinate
[17:16:01] [PASSED] Fail: overflowing fb with source width
[17:16:01] [PASSED] Fail: overflowing fb with source height
[17:16:01] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[17:16:01] [PASSED] drm_test_framebuffer_cleanup
[17:16:01] =============== drm_test_framebuffer_create ===============
[17:16:01] [PASSED] ABGR8888 normal sizes
[17:16:01] [PASSED] ABGR8888 max sizes
[17:16:01] [PASSED] ABGR8888 pitch greater than min required
[17:16:01] [PASSED] ABGR8888 pitch less than min required
[17:16:01] [PASSED] ABGR8888 Invalid width
[17:16:01] [PASSED] ABGR8888 Invalid buffer handle
[17:16:01] [PASSED] No pixel format
[17:16:01] [PASSED] ABGR8888 Width 0
[17:16:01] [PASSED] ABGR8888 Height 0
[17:16:01] [PASSED] ABGR8888 Out of bound height * pitch combination
[17:16:01] [PASSED] ABGR8888 Large buffer offset
[17:16:01] [PASSED] ABGR8888 Buffer offset for inexistent plane
[17:16:01] [PASSED] ABGR8888 Invalid flag
[17:16:01] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[17:16:01] [PASSED] ABGR8888 Valid buffer modifier
[17:16:01] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[17:16:01] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] NV12 Normal sizes
[17:16:01] [PASSED] NV12 Max sizes
[17:16:01] [PASSED] NV12 Invalid pitch
[17:16:01] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[17:16:01] [PASSED] NV12 different modifier per-plane
[17:16:01] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[17:16:01] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] NV12 Modifier for inexistent plane
[17:16:01] [PASSED] NV12 Handle for inexistent plane
[17:16:01] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[17:16:01] [PASSED] YVU420 Normal sizes
[17:16:01] [PASSED] YVU420 Max sizes
[17:16:01] [PASSED] YVU420 Invalid pitch
[17:16:01] [PASSED] YVU420 Different pitches
[17:16:01] [PASSED] YVU420 Different buffer offsets/pitches
[17:16:01] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[17:16:01] [PASSED] YVU420 Valid modifier
[17:16:01] [PASSED] YVU420 Different modifiers per plane
[17:16:01] [PASSED] YVU420 Modifier for inexistent plane
[17:16:01] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[17:16:01] [PASSED] X0L2 Normal sizes
[17:16:01] [PASSED] X0L2 Max sizes
[17:16:01] [PASSED] X0L2 Invalid pitch
[17:16:01] [PASSED] X0L2 Pitch greater than minimum required
[17:16:01] [PASSED] X0L2 Handle for inexistent plane
[17:16:01] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[17:16:01] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[17:16:01] [PASSED] X0L2 Valid modifier
[17:16:01] [PASSED] X0L2 Modifier for inexistent plane
[17:16:01] =========== [PASSED] drm_test_framebuffer_create ===========
[17:16:01] [PASSED] drm_test_framebuffer_free
[17:16:01] [PASSED] drm_test_framebuffer_init
[17:16:01] [PASSED] drm_test_framebuffer_init_bad_format
[17:16:01] [PASSED] drm_test_framebuffer_init_dev_mismatch
[17:16:01] [PASSED] drm_test_framebuffer_lookup
[17:16:01] [PASSED] drm_test_framebuffer_lookup_inexistent
[17:16:01] [PASSED] drm_test_framebuffer_modifiers_not_supported
[17:16:01] ================= [PASSED] drm_framebuffer =================
[17:16:01] ================ drm_gem_shmem (8 subtests) ================
[17:16:01] [PASSED] drm_gem_shmem_test_obj_create
[17:16:01] [PASSED] drm_gem_shmem_test_obj_create_private
[17:16:01] [PASSED] drm_gem_shmem_test_pin_pages
[17:16:01] [PASSED] drm_gem_shmem_test_vmap
[17:16:01] [PASSED] drm_gem_shmem_test_get_pages_sgt
[17:16:01] [PASSED] drm_gem_shmem_test_get_sg_table
[17:16:01] [PASSED] drm_gem_shmem_test_madvise
[17:16:01] [PASSED] drm_gem_shmem_test_purge
[17:16:01] ================== [PASSED] drm_gem_shmem ==================
[17:16:01] === drm_atomic_helper_connector_hdmi_check (22 subtests) ===
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[17:16:01] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[17:16:01] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback
[17:16:01] [PASSED] drm_test_check_max_tmds_rate_format_fallback
[17:16:01] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[17:16:01] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[17:16:01] [PASSED] drm_test_check_output_bpc_dvi
[17:16:01] [PASSED] drm_test_check_output_bpc_format_vic_1
[17:16:01] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[17:16:01] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[17:16:01] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[17:16:01] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[17:16:01] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[17:16:01] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[17:16:01] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[17:16:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[17:16:01] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[17:16:01] [PASSED] drm_test_check_broadcast_rgb_value
[17:16:01] [PASSED] drm_test_check_bpc_8_value
[17:16:01] [PASSED] drm_test_check_bpc_10_value
[17:16:01] [PASSED] drm_test_check_bpc_12_value
[17:16:01] [PASSED] drm_test_check_format_value
[17:16:01] [PASSED] drm_test_check_tmds_char_value
[17:16:01] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[17:16:01] ================= drm_managed (2 subtests) =================
[17:16:01] [PASSED] drm_test_managed_release_action
[17:16:01] [PASSED] drm_test_managed_run_action
[17:16:01] =================== [PASSED] drm_managed ===================
[17:16:01] =================== drm_mm (6 subtests) ====================
[17:16:01] [PASSED] drm_test_mm_init
[17:16:01] [PASSED] drm_test_mm_debug
[17:16:01] [PASSED] drm_test_mm_align32
[17:16:01] [PASSED] drm_test_mm_align64
[17:16:01] [PASSED] drm_test_mm_lowest
[17:16:01] [PASSED] drm_test_mm_highest
[17:16:01] ===================== [PASSED] drm_mm ======================
[17:16:01] ============= drm_modes_analog_tv (5 subtests) =============
[17:16:01] [PASSED] drm_test_modes_analog_tv_mono_576i
[17:16:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[17:16:01] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[17:16:01] [PASSED] drm_test_modes_analog_tv_pal_576i
[17:16:01] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[17:16:01] =============== [PASSED] drm_modes_analog_tv ===============
stty: 'standard input': Inappropriate ioctl for device
[17:16:01] ============== drm_plane_helper (2 subtests) ===============
[17:16:01] =============== drm_test_check_plane_state ================
[17:16:01] [PASSED] clipping_simple
[17:16:01] [PASSED] clipping_rotate_reflect
[17:16:01] [PASSED] positioning_simple
[17:16:01] [PASSED] upscaling
[17:16:01] [PASSED] downscaling
[17:16:01] [PASSED] rounding1
[17:16:01] [PASSED] rounding2
[17:16:01] [PASSED] rounding3
[17:16:01] [PASSED] rounding4
[17:16:01] =========== [PASSED] drm_test_check_plane_state ============
[17:16:01] =========== drm_test_check_invalid_plane_state ============
[17:16:01] [PASSED] positioning_invalid
[17:16:01] [PASSED] upscaling_invalid
[17:16:01] [PASSED] downscaling_invalid
[17:16:01] ======= [PASSED] drm_test_check_invalid_plane_state ========
[17:16:01] ================ [PASSED] drm_plane_helper =================
[17:16:01] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[17:16:01] ====== drm_test_connector_helper_tv_get_modes_check =======
[17:16:01] [PASSED] None
[17:16:01] [PASSED] PAL
[17:16:01] [PASSED] NTSC
[17:16:01] [PASSED] Both, NTSC Default
[17:16:01] [PASSED] Both, PAL Default
[17:16:01] [PASSED] Both, NTSC Default, with PAL on command-line
[17:16:01] [PASSED] Both, PAL Default, with NTSC on command-line
[17:16:01] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[17:16:01] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[17:16:01] ================== drm_rect (9 subtests) ===================
[17:16:01] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[17:16:01] [PASSED] drm_test_rect_clip_scaled_not_clipped
[17:16:01] [PASSED] drm_test_rect_clip_scaled_clipped
[17:16:01] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[17:16:01] ================= drm_test_rect_intersect =================
[17:16:01] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[17:16:01] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[17:16:01] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[17:16:01] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[17:16:01] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[17:16:01] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[17:16:01] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[17:16:01] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[17:16:01] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[17:16:01] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[17:16:01] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[17:16:01] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[17:16:01] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[17:16:01] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[17:16:01] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[17:16:01] ============= [PASSED] drm_test_rect_intersect =============
[17:16:01] ================ drm_test_rect_calc_hscale ================
[17:16:01] [PASSED] normal use
[17:16:01] [PASSED] out of max range
[17:16:01] [PASSED] out of min range
[17:16:01] [PASSED] zero dst
[17:16:01] [PASSED] negative src
[17:16:01] [PASSED] negative dst
[17:16:01] ============ [PASSED] drm_test_rect_calc_hscale ============
[17:16:01] ================ drm_test_rect_calc_vscale ================
[17:16:01] [PASSED] normal use
[17:16:01] [PASSED] out of max range
[17:16:01] [PASSED] out of min range
[17:16:01] [PASSED] zero dst
[17:16:01] [PASSED] negative src
[17:16:01] [PASSED] negative dst
[17:16:01] ============ [PASSED] drm_test_rect_calc_vscale ============
[17:16:01] ================== drm_test_rect_rotate ===================
[17:16:01] [PASSED] reflect-x
[17:16:01] [PASSED] reflect-y
[17:16:01] [PASSED] rotate-0
[17:16:01] [PASSED] rotate-90
[17:16:01] [PASSED] rotate-180
[17:16:01] [PASSED] rotate-270
[17:16:01] ============== [PASSED] drm_test_rect_rotate ===============
[17:16:01] ================ drm_test_rect_rotate_inv =================
[17:16:01] [PASSED] reflect-x
[17:16:01] [PASSED] reflect-y
[17:16:01] [PASSED] rotate-0
[17:16:01] [PASSED] rotate-90
[17:16:01] [PASSED] rotate-180
[17:16:01] [PASSED] rotate-270
[17:16:01] ============ [PASSED] drm_test_rect_rotate_inv =============
[17:16:01] ==================== [PASSED] drm_rect =====================
[17:16:01] ============================================================
[17:16:01] Testing complete. Ran 526 tests: passed: 526
[17:16:02] Elapsed time: 24.181s total, 1.681s configuring, 22.280s building, 0.179s running
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[17:16:02] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[17:16:03] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json ARCH=um O=.kunit --jobs=48
[17:16:11] Starting KUnit Kernel (1/1)...
[17:16:11] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[17:16:11] ================= ttm_device (5 subtests) ==================
[17:16:11] [PASSED] ttm_device_init_basic
[17:16:11] [PASSED] ttm_device_init_multiple
[17:16:11] [PASSED] ttm_device_fini_basic
[17:16:11] [PASSED] ttm_device_init_no_vma_man
[17:16:11] ================== ttm_device_init_pools ==================
[17:16:11] [PASSED] No DMA allocations, no DMA32 required
[17:16:11] [PASSED] DMA allocations, DMA32 required
[17:16:11] [PASSED] No DMA allocations, DMA32 required
[17:16:11] [PASSED] DMA allocations, no DMA32 required
[17:16:11] ============== [PASSED] ttm_device_init_pools ==============
[17:16:11] =================== [PASSED] ttm_device ====================
[17:16:11] ================== ttm_pool (8 subtests) ===================
[17:16:11] ================== ttm_pool_alloc_basic ===================
[17:16:11] [PASSED] One page
[17:16:11] [PASSED] More than one page
[17:16:11] [PASSED] Above the allocation limit
[17:16:11] [PASSED] One page, with coherent DMA mappings enabled
[17:16:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:16:11] ============== [PASSED] ttm_pool_alloc_basic ===============
[17:16:11] ============== ttm_pool_alloc_basic_dma_addr ==============
[17:16:11] [PASSED] One page
[17:16:11] [PASSED] More than one page
[17:16:11] [PASSED] Above the allocation limit
[17:16:11] [PASSED] One page, with coherent DMA mappings enabled
[17:16:11] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[17:16:11] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[17:16:11] [PASSED] ttm_pool_alloc_order_caching_match
[17:16:11] [PASSED] ttm_pool_alloc_caching_mismatch
[17:16:11] [PASSED] ttm_pool_alloc_order_mismatch
[17:16:11] [PASSED] ttm_pool_free_dma_alloc
[17:16:11] [PASSED] ttm_pool_free_no_dma_alloc
[17:16:11] [PASSED] ttm_pool_fini_basic
[17:16:11] ==================== [PASSED] ttm_pool =====================
[17:16:11] ================ ttm_resource (8 subtests) =================
[17:16:11] ================= ttm_resource_init_basic =================
[17:16:11] [PASSED] Init resource in TTM_PL_SYSTEM
[17:16:11] [PASSED] Init resource in TTM_PL_VRAM
[17:16:11] [PASSED] Init resource in a private placement
[17:16:11] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[17:16:11] ============= [PASSED] ttm_resource_init_basic =============
[17:16:11] [PASSED] ttm_resource_init_pinned
[17:16:11] [PASSED] ttm_resource_fini_basic
[17:16:11] [PASSED] ttm_resource_manager_init_basic
[17:16:11] [PASSED] ttm_resource_manager_usage_basic
[17:16:11] [PASSED] ttm_resource_manager_set_used_basic
[17:16:11] [PASSED] ttm_sys_man_alloc_basic
[17:16:11] [PASSED] ttm_sys_man_free_basic
[17:16:11] ================== [PASSED] ttm_resource ===================
[17:16:11] =================== ttm_tt (15 subtests) ===================
[17:16:11] ==================== ttm_tt_init_basic ====================
[17:16:11] [PASSED] Page-aligned size
[17:16:11] [PASSED] Extra pages requested
[17:16:11] ================ [PASSED] ttm_tt_init_basic ================
[17:16:11] [PASSED] ttm_tt_init_misaligned
[17:16:11] [PASSED] ttm_tt_fini_basic
[17:16:11] [PASSED] ttm_tt_fini_sg
[17:16:11] [PASSED] ttm_tt_fini_shmem
[17:16:11] [PASSED] ttm_tt_create_basic
[17:16:11] [PASSED] ttm_tt_create_invalid_bo_type
[17:16:11] [PASSED] ttm_tt_create_ttm_exists
[17:16:11] [PASSED] ttm_tt_create_failed
[17:16:11] [PASSED] ttm_tt_destroy_basic
[17:16:11] [PASSED] ttm_tt_populate_null_ttm
[17:16:11] [PASSED] ttm_tt_populate_populated_ttm
[17:16:11] [PASSED] ttm_tt_unpopulate_basic
[17:16:11] [PASSED] ttm_tt_unpopulate_empty_ttm
[17:16:11] [PASSED] ttm_tt_swapin_basic
[17:16:11] ===================== [PASSED] ttm_tt ======================
[17:16:11] =================== ttm_bo (14 subtests) ===================
[17:16:11] =========== ttm_bo_reserve_optimistic_no_ticket ===========
[17:16:11] [PASSED] Cannot be interrupted and sleeps
[17:16:11] [PASSED] Cannot be interrupted, locks straight away
[17:16:11] [PASSED] Can be interrupted, sleeps
[17:16:11] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[17:16:11] [PASSED] ttm_bo_reserve_locked_no_sleep
[17:16:11] [PASSED] ttm_bo_reserve_no_wait_ticket
[17:16:11] [PASSED] ttm_bo_reserve_double_resv
[17:16:11] [PASSED] ttm_bo_reserve_interrupted
[17:16:11] [PASSED] ttm_bo_reserve_deadlock
[17:16:11] [PASSED] ttm_bo_unreserve_basic
[17:16:11] [PASSED] ttm_bo_unreserve_pinned
[17:16:11] [PASSED] ttm_bo_unreserve_bulk
[17:16:11] [PASSED] ttm_bo_put_basic
[17:16:11] [PASSED] ttm_bo_put_shared_resv
[17:16:11] [PASSED] ttm_bo_pin_basic
[17:16:11] [PASSED] ttm_bo_pin_unpin_resource
[17:16:11] [PASSED] ttm_bo_multiple_pin_one_unpin
[17:16:11] ===================== [PASSED] ttm_bo ======================
[17:16:11] ============== ttm_bo_validate (22 subtests) ===============
[17:16:11] ============== ttm_bo_init_reserved_sys_man ===============
[17:16:11] [PASSED] Buffer object for userspace
[17:16:11] [PASSED] Kernel buffer object
[17:16:11] [PASSED] Shared buffer object
[17:16:11] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[17:16:11] ============== ttm_bo_init_reserved_mock_man ==============
[17:16:11] [PASSED] Buffer object for userspace
[17:16:11] [PASSED] Kernel buffer object
[17:16:11] [PASSED] Shared buffer object
[17:16:11] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[17:16:11] [PASSED] ttm_bo_init_reserved_resv
[17:16:11] ================== ttm_bo_validate_basic ==================
[17:16:11] [PASSED] Buffer object for userspace
[17:16:11] [PASSED] Kernel buffer object
[17:16:11] [PASSED] Shared buffer object
[17:16:11] ============== [PASSED] ttm_bo_validate_basic ==============
[17:16:11] [PASSED] ttm_bo_validate_invalid_placement
[17:16:11] ============= ttm_bo_validate_same_placement ==============
[17:16:11] [PASSED] System manager
[17:16:11] [PASSED] VRAM manager
[17:16:11] ========= [PASSED] ttm_bo_validate_same_placement ==========
[17:16:11] [PASSED] ttm_bo_validate_failed_alloc
[17:16:11] [PASSED] ttm_bo_validate_pinned
[17:16:11] [PASSED] ttm_bo_validate_busy_placement
[17:16:11] ================ ttm_bo_validate_multihop =================
[17:16:11] [PASSED] Buffer object for userspace
[17:16:11] [PASSED] Kernel buffer object
[17:16:11] [PASSED] Shared buffer object
[17:16:11] ============ [PASSED] ttm_bo_validate_multihop =============
[17:16:11] ========== ttm_bo_validate_no_placement_signaled ==========
[17:16:11] [PASSED] Buffer object in system domain, no page vector
[17:16:11] [PASSED] Buffer object in system domain with an existing page vector
[17:16:11] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[17:16:11] ======== ttm_bo_validate_no_placement_not_signaled ========
[17:16:11] [PASSED] Buffer object for userspace
[17:16:11] [PASSED] Kernel buffer object
[17:16:11] [PASSED] Shared buffer object
[17:16:11] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[17:16:11] [PASSED] ttm_bo_validate_move_fence_signaled
[17:16:11] ========= ttm_bo_validate_move_fence_not_signaled =========
[17:16:11] [PASSED] Waits for GPU
[17:16:11] [PASSED] Tries to lock straight away
[17:16:11] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[17:16:11] [PASSED] ttm_bo_validate_swapout
[17:16:11] [PASSED] ttm_bo_validate_happy_evict
[17:16:11] [PASSED] ttm_bo_validate_all_pinned_evict
[17:16:11] [PASSED] ttm_bo_validate_allowed_only_evict
[17:16:11] [PASSED] ttm_bo_validate_deleted_evict
[17:16:11] [PASSED] ttm_bo_validate_busy_domain_evict
[17:16:11] [PASSED] ttm_bo_validate_evict_gutting
[17:16:11] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[17:16:11] ================= [PASSED] ttm_bo_validate =================
[17:16:11] ============================================================
[17:16:11] Testing complete. Ran 102 tests: passed: 102
[17:16:12] Elapsed time: 9.919s total, 1.591s configuring, 7.661s building, 0.554s running
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ CI.Build: success for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (13 preceding siblings ...)
2024-10-22 17:16 ` ✓ CI.KUnit: success " Patchwork
@ 2024-10-22 17:27 ` Patchwork
2024-10-22 17:30 ` ✓ CI.Hooks: " Patchwork
` (3 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:27 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : success
== Summary ==
lib/modules/6.12.0-rc4-xe/kernel/sound/core/snd-hwdep.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/core/snd.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/core/snd-pcm.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/core/snd-compress.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/core/snd-timer.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soundcore.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/atom/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/atom/snd-soc-sst-atom-hifi2-platform.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/atom/sst/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-acpi.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/atom/sst/snd-intel-sst-core.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/common/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/intel/common/snd-soc-acpi-intel-match.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/amd/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/amd/acp/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/amd/acp/snd-soc-acpi-amd-match.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/amd/snd-acp-config.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-tgl.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-mlink.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-ptl.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-cnl.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-lnl.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-common.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda-generic.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-intel-hda.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/intel/snd-sof-pci-intel-mtl.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/amd/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/amd/snd-sof-amd-renoir.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/amd/snd-sof-amd-acp.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/snd-sof-utils.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/snd-sof-pci.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/snd-sof.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/snd-sof-probes.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/xtensa/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/sof/xtensa/snd-sof-xtensa-dsp.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/snd-soc-core.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/snd-soc-acpi.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/codecs/
lib/modules/6.12.0-rc4-xe/kernel/sound/soc/codecs/snd-soc-hdac-hda.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/snd-intel-sdw-acpi.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/ext/
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/ext/snd-hda-ext-core.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/snd-intel-dspcfg.ko
lib/modules/6.12.0-rc4-xe/kernel/sound/hda/snd-hda-core.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kernel/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kernel/msr.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kernel/cpuid.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/sha512-ssse3.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/crct10dif-pclmul.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/ghash-clmulni-intel.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/sha1-ssse3.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/crc32-pclmul.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/sha256-ssse3.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/aesni-intel.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/crypto/polyval-clmulni.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/events/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/events/intel/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/events/intel/intel-cstate.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/events/rapl.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kvm/
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kvm/kvm.ko
lib/modules/6.12.0-rc4-xe/kernel/arch/x86/kvm/kvm-intel.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/
lib/modules/6.12.0-rc4-xe/kernel/crypto/crypto_simd.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/cmac.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/ccm.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/cryptd.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/polyval-generic.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/async_xor.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/async_tx.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/async_memcpy.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/async_pq.ko
lib/modules/6.12.0-rc4-xe/kernel/crypto/async_tx/async_raid6_recov.ko
lib/modules/6.12.0-rc4-xe/build
lib/modules/6.12.0-rc4-xe/modules.alias.bin
lib/modules/6.12.0-rc4-xe/modules.builtin
lib/modules/6.12.0-rc4-xe/modules.softdep
lib/modules/6.12.0-rc4-xe/modules.alias
lib/modules/6.12.0-rc4-xe/modules.order
lib/modules/6.12.0-rc4-xe/modules.symbols
lib/modules/6.12.0-rc4-xe/modules.dep.bin
+ mv kernel-nodebug.tar.gz ..
+ cd ..
+ rm -rf archive
++ date +%s
+ echo -e '\e[0Ksection_end:1729618063:package_x86_64_nodebug\r\e[0K'
+ sync
^[[0Ksection_end:1729618063:package_x86_64_nodebug
^[[0K
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ CI.Hooks: success for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (14 preceding siblings ...)
2024-10-22 17:27 ` ✓ CI.Build: " Patchwork
@ 2024-10-22 17:30 ` Patchwork
2024-10-22 17:31 ` ✗ CI.checksparse: warning " Patchwork
` (2 subsequent siblings)
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:30 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : success
== Summary ==
run-parts: executing /workspace/ci/hooks/00-showenv
+ export
+ grep -Ei '(^|\W)CI_'
declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64-default"
declare -x CI_KERNEL_SRC_DIR="/workspace/kernel"
declare -x CI_TOOLS_SRC_DIR="/workspace/ci"
declare -x CI_WORKSPACE_DIR="/workspace"
run-parts: executing /workspace/ci/hooks/10-build-W1
+ SRC_DIR=/workspace/kernel
+ RESTORE_DISPLAY_CONFIG=0
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ cd /workspace/kernel
++ nproc
+ make -j48 O=/workspace/kernel/build64-default modules_prepare
make[1]: Entering directory '/workspace/kernel/build64-default'
GEN Makefile
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
mkdir -p /workspace/kernel/build64-default/tools/objtool && make O=/workspace/kernel/build64-default subdir=tools/objtool --no-print-directory -C objtool
CALL ../scripts/checksyscalls.sh
INSTALL libsubcmd_headers
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/exec-cmd.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/help.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/pager.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/parse-options.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/run-command.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/sigchain.o
CC /workspace/kernel/build64-default/tools/objtool/libsubcmd/subcmd-config.o
LD /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd-in.o
AR /workspace/kernel/build64-default/tools/objtool/libsubcmd/libsubcmd.a
CC /workspace/kernel/build64-default/tools/objtool/weak.o
CC /workspace/kernel/build64-default/tools/objtool/check.o
CC /workspace/kernel/build64-default/tools/objtool/special.o
CC /workspace/kernel/build64-default/tools/objtool/builtin-check.o
CC /workspace/kernel/build64-default/tools/objtool/objtool.o
CC /workspace/kernel/build64-default/tools/objtool/elf.o
CC /workspace/kernel/build64-default/tools/objtool/orc_gen.o
CC /workspace/kernel/build64-default/tools/objtool/orc_dump.o
CC /workspace/kernel/build64-default/tools/objtool/libstring.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/special.o
CC /workspace/kernel/build64-default/tools/objtool/libctype.o
CC /workspace/kernel/build64-default/tools/objtool/str_error_r.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/decode.o
CC /workspace/kernel/build64-default/tools/objtool/librbtree.o
CC /workspace/kernel/build64-default/tools/objtool/arch/x86/orc.o
LD /workspace/kernel/build64-default/tools/objtool/arch/x86/objtool-in.o
LD /workspace/kernel/build64-default/tools/objtool/objtool-in.o
LINK /workspace/kernel/build64-default/tools/objtool/objtool
make[1]: Leaving directory '/workspace/kernel/build64-default'
++ nproc
+ make -j48 O=/workspace/kernel/build64-default W=1 drivers/gpu/drm/xe
make[1]: Entering directory '/workspace/kernel/build64-default'
make[2]: Nothing to be done for 'drivers/gpu/drm/xe'.
make[1]: Leaving directory '/workspace/kernel/build64-default'
run-parts: executing /workspace/ci/hooks/11-build-32b
+++ realpath /workspace/ci/hooks/11-build-32b
++ dirname /workspace/ci/hooks/11-build-32b
+ THIS_SCRIPT_DIR=/workspace/ci/hooks
+ SRC_DIR=/workspace/kernel
+ TOOLS_SRC_DIR=/workspace/ci
+ '[' -n /workspace/kernel/build64-default ']'
+ BUILD_DIR=/workspace/kernel/build64-default
+ BUILD_DIR=/workspace/kernel/build64-default/build32
+ cd /workspace/kernel
+ mkdir -p /workspace/kernel/build64-default/build32
++ nproc
+ make -j48 ARCH=i386 O=/workspace/kernel/build64-default/build32 defconfig
make[1]: Entering directory '/workspace/kernel/build64-default/build32'
GEN Makefile
HOSTCC scripts/basic/fixdep
HOSTCC scripts/kconfig/conf.o
HOSTCC scripts/kconfig/confdata.o
HOSTCC scripts/kconfig/expr.o
YACC scripts/kconfig/parser.tab.[ch]
LEX scripts/kconfig/lexer.lex.c
HOSTCC scripts/kconfig/menu.o
HOSTCC scripts/kconfig/preprocess.o
HOSTCC scripts/kconfig/symbol.o
HOSTCC scripts/kconfig/util.o
HOSTCC scripts/kconfig/lexer.lex.o
HOSTCC scripts/kconfig/parser.tab.o
HOSTLD scripts/kconfig/conf
*** Default configuration is based on 'i386_defconfig'
#
# configuration written to .config
#
make[1]: Leaving directory '/workspace/kernel/build64-default/build32'
+ cd /workspace/kernel/build64-default/build32
+ /workspace/kernel/scripts/kconfig/merge_config.sh .config /workspace/ci/kernel/10-xe.fragment
Using .config as base
Merging /workspace/ci/kernel/10-xe.fragment
Value of CONFIG_DRM_XE is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_DRM_XE is not set
New value: CONFIG_DRM_XE=m
Value of CONFIG_SND_DEBUG is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_SND_DEBUG is not set
New value: CONFIG_SND_DEBUG=y
Value of CONFIG_SND_HDA_INTEL is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: CONFIG_SND_HDA_INTEL=y
New value: CONFIG_SND_HDA_INTEL=m
Value of CONFIG_SND_HDA_CODEC_HDMI is redefined by fragment /workspace/ci/kernel/10-xe.fragment:
Previous value: # CONFIG_SND_HDA_CODEC_HDMI is not set
New value: CONFIG_SND_HDA_CODEC_HDMI=m
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
#
# configuration written to .config
#
Value requested for CONFIG_HAVE_UID16 not in final .config
Requested value: CONFIG_HAVE_UID16=y
Actual value:
Value requested for CONFIG_UID16 not in final .config
Requested value: CONFIG_UID16=y
Actual value:
Value requested for CONFIG_X86_32 not in final .config
Requested value: CONFIG_X86_32=y
Actual value:
Value requested for CONFIG_OUTPUT_FORMAT not in final .config
Requested value: CONFIG_OUTPUT_FORMAT="elf32-i386"
Actual value: CONFIG_OUTPUT_FORMAT="elf64-x86-64"
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MIN not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MIN=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MIN=28
Value requested for CONFIG_ARCH_MMAP_RND_BITS_MAX not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS_MAX=16
Actual value: CONFIG_ARCH_MMAP_RND_BITS_MAX=32
Value requested for CONFIG_PGTABLE_LEVELS not in final .config
Requested value: CONFIG_PGTABLE_LEVELS=2
Actual value: CONFIG_PGTABLE_LEVELS=5
Value requested for CONFIG_X86_BIGSMP not in final .config
Requested value: # CONFIG_X86_BIGSMP is not set
Actual value:
Value requested for CONFIG_X86_INTEL_QUARK not in final .config
Requested value: # CONFIG_X86_INTEL_QUARK is not set
Actual value:
Value requested for CONFIG_X86_RDC321X not in final .config
Requested value: # CONFIG_X86_RDC321X is not set
Actual value:
Value requested for CONFIG_X86_32_NON_STANDARD not in final .config
Requested value: # CONFIG_X86_32_NON_STANDARD is not set
Actual value:
Value requested for CONFIG_X86_32_IRIS not in final .config
Requested value: # CONFIG_X86_32_IRIS is not set
Actual value:
Value requested for CONFIG_M486SX not in final .config
Requested value: # CONFIG_M486SX is not set
Actual value:
Value requested for CONFIG_M486 not in final .config
Requested value: # CONFIG_M486 is not set
Actual value:
Value requested for CONFIG_M586 not in final .config
Requested value: # CONFIG_M586 is not set
Actual value:
Value requested for CONFIG_M586TSC not in final .config
Requested value: # CONFIG_M586TSC is not set
Actual value:
Value requested for CONFIG_M586MMX not in final .config
Requested value: # CONFIG_M586MMX is not set
Actual value:
Value requested for CONFIG_M686 not in final .config
Requested value: CONFIG_M686=y
Actual value:
Value requested for CONFIG_MPENTIUMII not in final .config
Requested value: # CONFIG_MPENTIUMII is not set
Actual value:
Value requested for CONFIG_MPENTIUMIII not in final .config
Requested value: # CONFIG_MPENTIUMIII is not set
Actual value:
Value requested for CONFIG_MPENTIUMM not in final .config
Requested value: # CONFIG_MPENTIUMM is not set
Actual value:
Value requested for CONFIG_MPENTIUM4 not in final .config
Requested value: # CONFIG_MPENTIUM4 is not set
Actual value:
Value requested for CONFIG_MK6 not in final .config
Requested value: # CONFIG_MK6 is not set
Actual value:
Value requested for CONFIG_MK7 not in final .config
Requested value: # CONFIG_MK7 is not set
Actual value:
Value requested for CONFIG_MCRUSOE not in final .config
Requested value: # CONFIG_MCRUSOE is not set
Actual value:
Value requested for CONFIG_MEFFICEON not in final .config
Requested value: # CONFIG_MEFFICEON is not set
Actual value:
Value requested for CONFIG_MWINCHIPC6 not in final .config
Requested value: # CONFIG_MWINCHIPC6 is not set
Actual value:
Value requested for CONFIG_MWINCHIP3D not in final .config
Requested value: # CONFIG_MWINCHIP3D is not set
Actual value:
Value requested for CONFIG_MELAN not in final .config
Requested value: # CONFIG_MELAN is not set
Actual value:
Value requested for CONFIG_MGEODEGX1 not in final .config
Requested value: # CONFIG_MGEODEGX1 is not set
Actual value:
Value requested for CONFIG_MGEODE_LX not in final .config
Requested value: # CONFIG_MGEODE_LX is not set
Actual value:
Value requested for CONFIG_MCYRIXIII not in final .config
Requested value: # CONFIG_MCYRIXIII is not set
Actual value:
Value requested for CONFIG_MVIAC3_2 not in final .config
Requested value: # CONFIG_MVIAC3_2 is not set
Actual value:
Value requested for CONFIG_MVIAC7 not in final .config
Requested value: # CONFIG_MVIAC7 is not set
Actual value:
Value requested for CONFIG_X86_GENERIC not in final .config
Requested value: # CONFIG_X86_GENERIC is not set
Actual value:
Value requested for CONFIG_X86_INTERNODE_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_INTERNODE_CACHE_SHIFT=5
Actual value: CONFIG_X86_INTERNODE_CACHE_SHIFT=6
Value requested for CONFIG_X86_L1_CACHE_SHIFT not in final .config
Requested value: CONFIG_X86_L1_CACHE_SHIFT=5
Actual value: CONFIG_X86_L1_CACHE_SHIFT=6
Value requested for CONFIG_X86_USE_PPRO_CHECKSUM not in final .config
Requested value: CONFIG_X86_USE_PPRO_CHECKSUM=y
Actual value:
Value requested for CONFIG_X86_MINIMUM_CPU_FAMILY not in final .config
Requested value: CONFIG_X86_MINIMUM_CPU_FAMILY=6
Actual value: CONFIG_X86_MINIMUM_CPU_FAMILY=64
Value requested for CONFIG_CPU_SUP_TRANSMETA_32 not in final .config
Requested value: CONFIG_CPU_SUP_TRANSMETA_32=y
Actual value:
Value requested for CONFIG_CPU_SUP_VORTEX_32 not in final .config
Requested value: CONFIG_CPU_SUP_VORTEX_32=y
Actual value:
Value requested for CONFIG_HPET_TIMER not in final .config
Requested value: # CONFIG_HPET_TIMER is not set
Actual value: CONFIG_HPET_TIMER=y
Value requested for CONFIG_NR_CPUS_RANGE_END not in final .config
Requested value: CONFIG_NR_CPUS_RANGE_END=8
Actual value: CONFIG_NR_CPUS_RANGE_END=512
Value requested for CONFIG_NR_CPUS_DEFAULT not in final .config
Requested value: CONFIG_NR_CPUS_DEFAULT=8
Actual value: CONFIG_NR_CPUS_DEFAULT=64
Value requested for CONFIG_X86_ANCIENT_MCE not in final .config
Requested value: # CONFIG_X86_ANCIENT_MCE is not set
Actual value:
Value requested for CONFIG_X86_LEGACY_VM86 not in final .config
Requested value: # CONFIG_X86_LEGACY_VM86 is not set
Actual value:
Value requested for CONFIG_X86_ESPFIX32 not in final .config
Requested value: CONFIG_X86_ESPFIX32=y
Actual value:
Value requested for CONFIG_TOSHIBA not in final .config
Requested value: # CONFIG_TOSHIBA is not set
Actual value:
Value requested for CONFIG_X86_REBOOTFIXUPS not in final .config
Requested value: # CONFIG_X86_REBOOTFIXUPS is not set
Actual value:
Value requested for CONFIG_MICROCODE_INITRD32 not in final .config
Requested value: CONFIG_MICROCODE_INITRD32=y
Actual value:
Value requested for CONFIG_NOHIGHMEM not in final .config
Requested value: # CONFIG_NOHIGHMEM is not set
Actual value:
Value requested for CONFIG_HIGHMEM4G not in final .config
Requested value: CONFIG_HIGHMEM4G=y
Actual value:
Value requested for CONFIG_HIGHMEM64G not in final .config
Requested value: # CONFIG_HIGHMEM64G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_3G not in final .config
Requested value: CONFIG_VMSPLIT_3G=y
Actual value:
Value requested for CONFIG_VMSPLIT_3G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_3G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G not in final .config
Requested value: # CONFIG_VMSPLIT_2G is not set
Actual value:
Value requested for CONFIG_VMSPLIT_2G_OPT not in final .config
Requested value: # CONFIG_VMSPLIT_2G_OPT is not set
Actual value:
Value requested for CONFIG_VMSPLIT_1G not in final .config
Requested value: # CONFIG_VMSPLIT_1G is not set
Actual value:
Value requested for CONFIG_PAGE_OFFSET not in final .config
Requested value: CONFIG_PAGE_OFFSET=0xC0000000
Actual value:
Value requested for CONFIG_HIGHMEM not in final .config
Requested value: CONFIG_HIGHMEM=y
Actual value:
Value requested for CONFIG_X86_PAE not in final .config
Requested value: # CONFIG_X86_PAE is not set
Actual value:
Value requested for CONFIG_ARCH_FLATMEM_ENABLE not in final .config
Requested value: CONFIG_ARCH_FLATMEM_ENABLE=y
Actual value:
Value requested for CONFIG_ARCH_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_ARCH_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_ILLEGAL_POINTER_VALUE not in final .config
Requested value: CONFIG_ILLEGAL_POINTER_VALUE=0
Actual value: CONFIG_ILLEGAL_POINTER_VALUE=0xdead000000000000
Value requested for CONFIG_HIGHPTE not in final .config
Requested value: # CONFIG_HIGHPTE is not set
Actual value:
Value requested for CONFIG_COMPAT_VDSO not in final .config
Requested value: # CONFIG_COMPAT_VDSO is not set
Actual value:
Value requested for CONFIG_FUNCTION_PADDING_CFI not in final .config
Requested value: CONFIG_FUNCTION_PADDING_CFI=0
Actual value: CONFIG_FUNCTION_PADDING_CFI=11
Value requested for CONFIG_FUNCTION_PADDING_BYTES not in final .config
Requested value: CONFIG_FUNCTION_PADDING_BYTES=4
Actual value: CONFIG_FUNCTION_PADDING_BYTES=16
Value requested for CONFIG_APM not in final .config
Requested value: # CONFIG_APM is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K6 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K6 is not set
Actual value:
Value requested for CONFIG_X86_POWERNOW_K7 not in final .config
Requested value: # CONFIG_X86_POWERNOW_K7 is not set
Actual value:
Value requested for CONFIG_X86_GX_SUSPMOD not in final .config
Requested value: # CONFIG_X86_GX_SUSPMOD is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_ICH not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_ICH is not set
Actual value:
Value requested for CONFIG_X86_SPEEDSTEP_SMI not in final .config
Requested value: # CONFIG_X86_SPEEDSTEP_SMI is not set
Actual value:
Value requested for CONFIG_X86_CPUFREQ_NFORCE2 not in final .config
Requested value: # CONFIG_X86_CPUFREQ_NFORCE2 is not set
Actual value:
Value requested for CONFIG_X86_LONGRUN not in final .config
Requested value: # CONFIG_X86_LONGRUN is not set
Actual value:
Value requested for CONFIG_X86_LONGHAUL not in final .config
Requested value: # CONFIG_X86_LONGHAUL is not set
Actual value:
Value requested for CONFIG_X86_E_POWERSAVER not in final .config
Requested value: # CONFIG_X86_E_POWERSAVER is not set
Actual value:
Value requested for CONFIG_PCI_GOBIOS not in final .config
Requested value: # CONFIG_PCI_GOBIOS is not set
Actual value:
Value requested for CONFIG_PCI_GOMMCONFIG not in final .config
Requested value: # CONFIG_PCI_GOMMCONFIG is not set
Actual value:
Value requested for CONFIG_PCI_GODIRECT not in final .config
Requested value: # CONFIG_PCI_GODIRECT is not set
Actual value:
Value requested for CONFIG_PCI_GOANY not in final .config
Requested value: CONFIG_PCI_GOANY=y
Actual value:
Value requested for CONFIG_PCI_BIOS not in final .config
Requested value: CONFIG_PCI_BIOS=y
Actual value:
Value requested for CONFIG_ISA not in final .config
Requested value: # CONFIG_ISA is not set
Actual value:
Value requested for CONFIG_SCx200 not in final .config
Requested value: # CONFIG_SCx200 is not set
Actual value:
Value requested for CONFIG_OLPC not in final .config
Requested value: # CONFIG_OLPC is not set
Actual value:
Value requested for CONFIG_ALIX not in final .config
Requested value: # CONFIG_ALIX is not set
Actual value:
Value requested for CONFIG_NET5501 not in final .config
Requested value: # CONFIG_NET5501 is not set
Actual value:
Value requested for CONFIG_GEOS not in final .config
Requested value: # CONFIG_GEOS is not set
Actual value:
Value requested for CONFIG_COMPAT_32 not in final .config
Requested value: CONFIG_COMPAT_32=y
Actual value:
Value requested for CONFIG_HAVE_ATOMIC_IOMAP not in final .config
Requested value: CONFIG_HAVE_ATOMIC_IOMAP=y
Actual value:
Value requested for CONFIG_ARCH_32BIT_OFF_T not in final .config
Requested value: CONFIG_ARCH_32BIT_OFF_T=y
Actual value:
Value requested for CONFIG_ARCH_WANT_IPC_PARSE_VERSION not in final .config
Requested value: CONFIG_ARCH_WANT_IPC_PARSE_VERSION=y
Actual value:
Value requested for CONFIG_MODULES_USE_ELF_REL not in final .config
Requested value: CONFIG_MODULES_USE_ELF_REL=y
Actual value:
Value requested for CONFIG_ARCH_MMAP_RND_BITS not in final .config
Requested value: CONFIG_ARCH_MMAP_RND_BITS=8
Actual value: CONFIG_ARCH_MMAP_RND_BITS=28
Value requested for CONFIG_CLONE_BACKWARDS not in final .config
Requested value: CONFIG_CLONE_BACKWARDS=y
Actual value:
Value requested for CONFIG_OLD_SIGSUSPEND3 not in final .config
Requested value: CONFIG_OLD_SIGSUSPEND3=y
Actual value:
Value requested for CONFIG_OLD_SIGACTION not in final .config
Requested value: CONFIG_OLD_SIGACTION=y
Actual value:
Value requested for CONFIG_ARCH_SPLIT_ARG64 not in final .config
Requested value: CONFIG_ARCH_SPLIT_ARG64=y
Actual value:
Value requested for CONFIG_FUNCTION_ALIGNMENT not in final .config
Requested value: CONFIG_FUNCTION_ALIGNMENT=4
Actual value: CONFIG_FUNCTION_ALIGNMENT=16
Value requested for CONFIG_SELECT_MEMORY_MODEL not in final .config
Requested value: CONFIG_SELECT_MEMORY_MODEL=y
Actual value:
Value requested for CONFIG_FLATMEM_MANUAL not in final .config
Requested value: CONFIG_FLATMEM_MANUAL=y
Actual value:
Value requested for CONFIG_SPARSEMEM_MANUAL not in final .config
Requested value: # CONFIG_SPARSEMEM_MANUAL is not set
Actual value:
Value requested for CONFIG_FLATMEM not in final .config
Requested value: CONFIG_FLATMEM=y
Actual value:
Value requested for CONFIG_SPARSEMEM_STATIC not in final .config
Requested value: CONFIG_SPARSEMEM_STATIC=y
Actual value:
Value requested for CONFIG_BOUNCE not in final .config
Requested value: CONFIG_BOUNCE=y
Actual value:
Value requested for CONFIG_KMAP_LOCAL not in final .config
Requested value: CONFIG_KMAP_LOCAL=y
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_COMPAQ not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_COMPAQ is not set
Actual value:
Value requested for CONFIG_HOTPLUG_PCI_IBM not in final .config
Requested value: # CONFIG_HOTPLUG_PCI_IBM is not set
Actual value:
Value requested for CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH not in final .config
Requested value: CONFIG_EFI_CAPSULE_QUIRK_QUARK_CSH=y
Actual value:
Value requested for CONFIG_PCH_PHUB not in final .config
Requested value: # CONFIG_PCH_PHUB is not set
Actual value:
Value requested for CONFIG_SCSI_NSP32 not in final .config
Requested value: # CONFIG_SCSI_NSP32 is not set
Actual value:
Value requested for CONFIG_PATA_CS5520 not in final .config
Requested value: # CONFIG_PATA_CS5520 is not set
Actual value:
Value requested for CONFIG_PATA_CS5530 not in final .config
Requested value: # CONFIG_PATA_CS5530 is not set
Actual value:
Value requested for CONFIG_PATA_CS5535 not in final .config
Requested value: # CONFIG_PATA_CS5535 is not set
Actual value:
Value requested for CONFIG_PATA_CS5536 not in final .config
Requested value: # CONFIG_PATA_CS5536 is not set
Actual value:
Value requested for CONFIG_PATA_SC1200 not in final .config
Requested value: # CONFIG_PATA_SC1200 is not set
Actual value:
Value requested for CONFIG_PCH_GBE not in final .config
Requested value: # CONFIG_PCH_GBE is not set
Actual value:
Value requested for CONFIG_INPUT_WISTRON_BTNS not in final .config
Requested value: # CONFIG_INPUT_WISTRON_BTNS is not set
Actual value:
Value requested for CONFIG_SERIAL_TIMBERDALE not in final .config
Requested value: # CONFIG_SERIAL_TIMBERDALE is not set
Actual value:
Value requested for CONFIG_SERIAL_PCH_UART not in final .config
Requested value: # CONFIG_SERIAL_PCH_UART is not set
Actual value:
Value requested for CONFIG_HW_RANDOM_GEODE not in final .config
Requested value: CONFIG_HW_RANDOM_GEODE=y
Actual value:
Value requested for CONFIG_SONYPI not in final .config
Requested value: # CONFIG_SONYPI is not set
Actual value:
Value requested for CONFIG_PC8736x_GPIO not in final .config
Requested value: # CONFIG_PC8736x_GPIO is not set
Actual value:
Value requested for CONFIG_NSC_GPIO not in final .config
Requested value: # CONFIG_NSC_GPIO is not set
Actual value:
Value requested for CONFIG_I2C_EG20T not in final .config
Requested value: # CONFIG_I2C_EG20T is not set
Actual value:
Value requested for CONFIG_SCx200_ACB not in final .config
Requested value: # CONFIG_SCx200_ACB is not set
Actual value:
Value requested for CONFIG_PTP_1588_CLOCK_PCH not in final .config
Requested value: # CONFIG_PTP_1588_CLOCK_PCH is not set
Actual value:
Value requested for CONFIG_SBC8360_WDT not in final .config
Requested value: # CONFIG_SBC8360_WDT is not set
Actual value:
Value requested for CONFIG_SBC7240_WDT not in final .config
Requested value: # CONFIG_SBC7240_WDT is not set
Actual value:
Value requested for CONFIG_MFD_CS5535 not in final .config
Requested value: # CONFIG_MFD_CS5535 is not set
Actual value:
Value requested for CONFIG_AGP_ALI not in final .config
Requested value: # CONFIG_AGP_ALI is not set
Actual value:
Value requested for CONFIG_AGP_ATI not in final .config
Requested value: # CONFIG_AGP_ATI is not set
Actual value:
Value requested for CONFIG_AGP_AMD not in final .config
Requested value: # CONFIG_AGP_AMD is not set
Actual value:
Value requested for CONFIG_AGP_NVIDIA not in final .config
Requested value: # CONFIG_AGP_NVIDIA is not set
Actual value:
Value requested for CONFIG_AGP_SWORKS not in final .config
Requested value: # CONFIG_AGP_SWORKS is not set
Actual value:
Value requested for CONFIG_AGP_EFFICEON not in final .config
Requested value: # CONFIG_AGP_EFFICEON is not set
Actual value:
Value requested for CONFIG_SND_PCM not in final .config
Requested value: CONFIG_SND_PCM=y
Actual value: CONFIG_SND_PCM=m
Value requested for CONFIG_SND_HWDEP not in final .config
Requested value: CONFIG_SND_HWDEP=y
Actual value: CONFIG_SND_HWDEP=m
Value requested for CONFIG_SND_DYNAMIC_MINORS not in final .config
Requested value: # CONFIG_SND_DYNAMIC_MINORS is not set
Actual value: CONFIG_SND_DYNAMIC_MINORS=y
Value requested for CONFIG_SND_CS5530 not in final .config
Requested value: # CONFIG_SND_CS5530 is not set
Actual value:
Value requested for CONFIG_SND_CS5535AUDIO not in final .config
Requested value: # CONFIG_SND_CS5535AUDIO is not set
Actual value:
Value requested for CONFIG_SND_SIS7019 not in final .config
Requested value: # CONFIG_SND_SIS7019 is not set
Actual value:
Value requested for CONFIG_SND_HDA not in final .config
Requested value: CONFIG_SND_HDA=y
Actual value: CONFIG_SND_HDA=m
Value requested for CONFIG_SND_HDA_CORE not in final .config
Requested value: CONFIG_SND_HDA_CORE=y
Actual value: CONFIG_SND_HDA_CORE=m
Value requested for CONFIG_SND_INTEL_DSP_CONFIG not in final .config
Requested value: CONFIG_SND_INTEL_DSP_CONFIG=y
Actual value: CONFIG_SND_INTEL_DSP_CONFIG=m
Value requested for CONFIG_SND_INTEL_SOUNDWIRE_ACPI not in final .config
Requested value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=y
Actual value: CONFIG_SND_INTEL_SOUNDWIRE_ACPI=m
Value requested for CONFIG_LEDS_OT200 not in final .config
Requested value: # CONFIG_LEDS_OT200 is not set
Actual value:
Value requested for CONFIG_PCH_DMA not in final .config
Requested value: # CONFIG_PCH_DMA is not set
Actual value:
Value requested for CONFIG_CLKSRC_I8253 not in final .config
Requested value: CONFIG_CLKSRC_I8253=y
Actual value:
Value requested for CONFIG_MAILBOX not in final .config
Requested value: # CONFIG_MAILBOX is not set
Actual value: CONFIG_MAILBOX=y
Value requested for CONFIG_CRYPTO_SERPENT_SSE2_586 not in final .config
Requested value: # CONFIG_CRYPTO_SERPENT_SSE2_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_TWOFISH_586 not in final .config
Requested value: # CONFIG_CRYPTO_TWOFISH_586 is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_GEODE not in final .config
Requested value: # CONFIG_CRYPTO_DEV_GEODE is not set
Actual value:
Value requested for CONFIG_CRYPTO_DEV_HIFN_795X not in final .config
Requested value: # CONFIG_CRYPTO_DEV_HIFN_795X is not set
Actual value:
Value requested for CONFIG_CRYPTO_LIB_POLY1305_RSIZE not in final .config
Requested value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=1
Actual value: CONFIG_CRYPTO_LIB_POLY1305_RSIZE=11
Value requested for CONFIG_AUDIT_GENERIC not in final .config
Requested value: CONFIG_AUDIT_GENERIC=y
Actual value:
Value requested for CONFIG_GENERIC_VDSO_32 not in final .config
Requested value: CONFIG_GENERIC_VDSO_32=y
Actual value:
Value requested for CONFIG_DEBUG_KMAP_LOCAL not in final .config
Requested value: # CONFIG_DEBUG_KMAP_LOCAL is not set
Actual value:
Value requested for CONFIG_DEBUG_HIGHMEM not in final .config
Requested value: # CONFIG_DEBUG_HIGHMEM is not set
Actual value:
Value requested for CONFIG_HAVE_DEBUG_STACKOVERFLOW not in final .config
Requested value: CONFIG_HAVE_DEBUG_STACKOVERFLOW=y
Actual value:
Value requested for CONFIG_DEBUG_STACKOVERFLOW not in final .config
Requested value: # CONFIG_DEBUG_STACKOVERFLOW is not set
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_TRACER not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_TRACER=y
Actual value:
Value requested for CONFIG_HAVE_FUNCTION_GRAPH_RETVAL not in final .config
Requested value: CONFIG_HAVE_FUNCTION_GRAPH_RETVAL=y
Actual value:
Value requested for CONFIG_DRM_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_KUNIT_TEST=m
Actual value:
Value requested for CONFIG_DRM_XE_WERROR not in final .config
Requested value: CONFIG_DRM_XE_WERROR=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG not in final .config
Requested value: CONFIG_DRM_XE_DEBUG=y
Actual value:
Value requested for CONFIG_DRM_XE_DEBUG_MEM not in final .config
Requested value: CONFIG_DRM_XE_DEBUG_MEM=y
Actual value:
Value requested for CONFIG_DRM_XE_KUNIT_TEST not in final .config
Requested value: CONFIG_DRM_XE_KUNIT_TEST=m
Actual value:
++ nproc
+ make -j48 ARCH=i386 olddefconfig
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
#
# configuration written to .config
#
++ nproc
+ make -j48 ARCH=i386
SYNC include/config/auto.conf.cmd
GEN Makefile
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
WARNING: unmet direct dependencies detected for FB_IOMEM_HELPERS
Depends on [n]: HAS_IOMEM [=y] && FB_CORE [=n]
Selected by [m]:
- DRM_XE_DISPLAY [=y] && HAS_IOMEM [=y] && DRM [=y] && DRM_XE [=m] && DRM_XE [=m]=m [=m]
GEN Makefile
WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h
WRAP arch/x86/include/generated/uapi/asm/errno.h
WRAP arch/x86/include/generated/uapi/asm/fcntl.h
UPD include/generated/uapi/linux/version.h
WRAP arch/x86/include/generated/uapi/asm/ioctl.h
WRAP arch/x86/include/generated/uapi/asm/ioctls.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h
WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h
WRAP arch/x86/include/generated/uapi/asm/param.h
SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h
WRAP arch/x86/include/generated/uapi/asm/poll.h
WRAP arch/x86/include/generated/uapi/asm/resource.h
SYSTBL arch/x86/include/generated/asm/syscalls_32.h
WRAP arch/x86/include/generated/uapi/asm/socket.h
WRAP arch/x86/include/generated/uapi/asm/sockios.h
WRAP arch/x86/include/generated/uapi/asm/termbits.h
WRAP arch/x86/include/generated/uapi/asm/termios.h
WRAP arch/x86/include/generated/uapi/asm/types.h
UPD include/generated/compile.h
HOSTCC arch/x86/tools/relocs_32.o
HOSTCC arch/x86/tools/relocs_64.o
HOSTCC arch/x86/tools/relocs_common.o
WRAP arch/x86/include/generated/asm/early_ioremap.h
WRAP arch/x86/include/generated/asm/mcs_spinlock.h
WRAP arch/x86/include/generated/asm/mmzone.h
WRAP arch/x86/include/generated/asm/irq_regs.h
WRAP arch/x86/include/generated/asm/kmap_size.h
HOSTCC scripts/kallsyms
WRAP arch/x86/include/generated/asm/local64.h
HOSTCC scripts/sorttable
WRAP arch/x86/include/generated/asm/mmiowb.h
WRAP arch/x86/include/generated/asm/module.lds.h
HOSTCC scripts/asn1_compiler
WRAP arch/x86/include/generated/asm/rwonce.h
HOSTCC scripts/selinux/genheaders/genheaders
HOSTCC scripts/selinux/mdp/mdp
HOSTLD arch/x86/tools/relocs
UPD include/config/kernel.release
UPD include/generated/utsrelease.h
CC scripts/mod/empty.o
HOSTCC scripts/mod/mk_elfconfig
CC scripts/mod/devicetable-offsets.s
UPD scripts/mod/devicetable-offsets.h
MKELF scripts/mod/elfconfig.h
HOSTCC scripts/mod/modpost.o
HOSTCC scripts/mod/sumversion.o
HOSTCC scripts/mod/file2alias.o
HOSTCC scripts/mod/symsearch.o
HOSTLD scripts/mod/modpost
CC kernel/bounds.s
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-arch-fallback.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-instrumented.h
CHKSHA1 /workspace/kernel/include/linux/atomic/atomic-long.h
UPD include/generated/timeconst.h
UPD include/generated/bounds.h
CC arch/x86/kernel/asm-offsets.s
UPD include/generated/asm-offsets.h
CALL /workspace/kernel/scripts/checksyscalls.sh
LDS scripts/module.lds
CC init/main.o
HOSTCC usr/gen_init_cpio
CC init/do_mounts.o
CC init/do_mounts_initrd.o
CC certs/system_keyring.o
CC init/initramfs.o
UPD init/utsversion-tmp.h
CC init/calibrate.o
CC ipc/util.o
CC ipc/msgutil.o
CC init/init_task.o
CC mm/filemap.o
CC ipc/msg.o
CC security/commoncap.o
CC mm/mempool.o
CC init/version.o
CC security/lsm_syscalls.o
CC ipc/sem.o
CC io_uring/io_uring.o
CC mm/oom_kill.o
CC arch/x86/realmode/init.o
CC ipc/shm.o
AS arch/x86/lib/atomic64_cx8_32.o
CC security/min_addr.o
CC arch/x86/video/video-common.o
CC arch/x86/pci/i386.o
CC security/keys/gc.o
AR arch/x86/net/built-in.a
CC arch/x86/power/cpu.o
AR arch/x86/crypto/built-in.a
CC security/integrity/iint.o
GEN security/selinux/flask.h security/selinux/av_permissions.h
CC block/partitions/core.o
CC arch/x86/events/amd/core.o
CC fs/nfs_common/nfsacl.o
AR virt/lib/built-in.a
AR arch/x86/entry/vsyscall/built-in.a
AR drivers/cache/built-in.a
CC lib/math/div64.o
AR arch/x86/virt/svm/built-in.a
AR arch/x86/platform/atom/built-in.a
CC net/core/sock.o
CC arch/x86/mm/pat/set_memory.o
CC fs/notify/dnotify/dnotify.o
CC arch/x86/kernel/fpu/init.o
CC security/selinux/avc.o
CC arch/x86/kernel/fpu/bugs.o
AR drivers/irqchip/built-in.a
AR virt/built-in.a
CC sound/core/seq/seq.o
CC fs/iomap/trace.o
AR arch/x86/virt/vmx/built-in.a
AR drivers/bus/mhi/built-in.a
AS arch/x86/lib/checksum_32.o
CC arch/x86/entry/vdso/vma.o
AR arch/x86/platform/ce4100/built-in.a
AR arch/x86/virt/built-in.a
AR drivers/bus/built-in.a
CC arch/x86/kernel/cpu/mce/core.o
CC lib/crypto/mpi/generic_mpih-lshift.o
CC arch/x86/entry/vdso/extable.o
CC arch/x86/platform/efi/memmap.o
CC kernel/sched/core.o
AR drivers/pwm/built-in.a
CC arch/x86/lib/cmdline.o
AR drivers/leds/trigger/built-in.a
CC crypto/asymmetric_keys/asymmetric_type.o
AR drivers/leds/blink/built-in.a
AR drivers/leds/simple/built-in.a
CC drivers/leds/led-core.o
CC fs/quota/dquot.o
AS arch/x86/lib/cmpxchg8b_emu.o
CC lib/math/gcd.o
CC arch/x86/lib/cpu.o
CC fs/proc/task_mmu.o
CC lib/math/lcm.o
CC lib/math/int_log.o
CC lib/math/int_pow.o
GEN usr/initramfs_data.cpio
COPY usr/initramfs_inc_data
AS usr/initramfs_data.o
CC io_uring/opdef.o
HOSTCC certs/extract-cert
AR usr/built-in.a
CC arch/x86/kernel/fpu/core.o
CC lib/math/int_sqrt.o
CC arch/x86/events/intel/core.o
CC lib/math/reciprocal_div.o
CC lib/math/rational.o
CC sound/core/seq/seq_lock.o
CC arch/x86/lib/delay.o
AS arch/x86/realmode/rm/header.o
AS arch/x86/realmode/rm/trampoline_32.o
CC lib/crypto/mpi/generic_mpih-mul1.o
AR arch/x86/video/built-in.a
AS arch/x86/realmode/rm/stack.o
CC kernel/sched/fair.o
AS arch/x86/realmode/rm/reboot.o
CERT certs/x509_certificate_list
AS arch/x86/realmode/rm/wakeup_asm.o
CERT certs/signing_key.x509
AS certs/system_certificates.o
CC lib/zlib_inflate/inffast.o
CC arch/x86/realmode/rm/wakemain.o
AR certs/built-in.a
CC security/integrity/integrity_audit.o
CC lib/zlib_deflate/deflate.o
CC drivers/leds/led-class.o
CC arch/x86/events/zhaoxin/core.o
CC io_uring/kbuf.o
CC fs/nfs_common/grace.o
CC arch/x86/kernel/cpu/mtrr/mtrr.o
CC arch/x86/kernel/cpu/microcode/core.o
CC crypto/asymmetric_keys/restrict.o
CC arch/x86/realmode/rm/video-mode.o
CC arch/x86/pci/init.o
AR sound/i2c/other/built-in.a
CC security/keys/key.o
AR sound/i2c/built-in.a
CC arch/x86/pci/pcbios.o
AR fs/notify/dnotify/built-in.a
CC arch/x86/kernel/cpu/mce/severity.o
LDS arch/x86/entry/vdso/vdso32/vdso32.lds
CC fs/notify/inotify/inotify_fsnotify.o
CC arch/x86/platform/efi/quirks.o
AS arch/x86/entry/vdso/vdso32/note.o
AS arch/x86/entry/vdso/vdso32/system_call.o
CC lib/zlib_inflate/inflate.o
AS arch/x86/entry/vdso/vdso32/sigreturn.o
CC block/partitions/msdos.o
AS arch/x86/lib/getuser.o
AS arch/x86/realmode/rm/copy.o
CC arch/x86/power/hibernate_32.o
CC arch/x86/entry/vdso/vdso32/vclock_gettime.o
AS arch/x86/realmode/rm/bioscall.o
GEN arch/x86/lib/inat-tables.c
CC arch/x86/realmode/rm/regs.o
CC arch/x86/lib/insn-eval.o
AR lib/math/built-in.a
CC sound/core/seq/seq_clientmgr.o
CC arch/x86/events/amd/lbr.o
CC arch/x86/realmode/rm/video-vga.o
CC arch/x86/events/amd/ibs.o
CC arch/x86/realmode/rm/video-vesa.o
CC io_uring/rsrc.o
CC lib/zlib_inflate/infutil.o
CC arch/x86/realmode/rm/video-bios.o
AS arch/x86/power/hibernate_asm_32.o
CC lib/crypto/memneq.o
CC arch/x86/kernel/cpu/microcode/intel.o
CC lib/crypto/mpi/generic_mpih-mul2.o
CC fs/iomap/iter.o
PASYMS arch/x86/realmode/rm/pasyms.h
CC crypto/asymmetric_keys/signature.o
CC lib/crypto/utils.o
CC drivers/leds/led-triggers.o
CC mm/fadvise.o
LDS arch/x86/realmode/rm/realmode.lds
AR fs/notify/fanotify/built-in.a
LD arch/x86/realmode/rm/realmode.elf
CC arch/x86/events/intel/bts.o
RELOCS arch/x86/realmode/rm/realmode.relocs
OBJCOPY arch/x86/realmode/rm/realmode.bin
AS arch/x86/realmode/rmpiggy.o
AR arch/x86/realmode/built-in.a
CC arch/x86/kernel/cpu/mce/genpool.o
CC fs/notify/inotify/inotify_user.o
CC arch/x86/mm/pat/memtype.o
CC arch/x86/kernel/acpi/boot.o
CC fs/iomap/buffered-io.o
AR security/integrity/built-in.a
CC arch/x86/kernel/fpu/regset.o
CC fs/nfs_common/common.o
CC crypto/asymmetric_keys/public_key.o
CC lib/zlib_inflate/inftrees.o
AR init/built-in.a
CC arch/x86/pci/mmconfig_32.o
ASN.1 crypto/asymmetric_keys/x509.asn1.[ch]
CC security/security.o
CC arch/x86/kernel/cpu/mtrr/if.o
CC lib/zlib_deflate/deftree.o
CC arch/x86/entry/vdso/vdso32/vgetcpu.o
CC mm/maccess.o
CC mm/page-writeback.o
CC arch/x86/power/hibernate.o
CC arch/x86/kernel/cpu/cacheinfo.o
AR arch/x86/events/zhaoxin/built-in.a
CC lib/crypto/mpi/generic_mpih-mul3.o
CC security/selinux/hooks.o
CC arch/x86/events/amd/uncore.o
HOSTCC arch/x86/entry/vdso/vdso2c
CC kernel/sched/build_policy.o
CC lib/zlib_inflate/inflate_syms.o
CC block/partitions/efi.o
CC arch/x86/kernel/apic/apic.o
CC arch/x86/platform/efi/efi.o
CC mm/folio-compat.o
CC ipc/syscall.o
CC arch/x86/lib/insn.o
CC security/keys/keyring.o
CC ipc/ipc_sysctl.o
AR arch/x86/platform/geode/built-in.a
CC kernel/locking/mutex.o
CC arch/x86/kernel/cpu/mce/intel.o
CC fs/proc/inode.o
CC sound/core/sound.o
CC arch/x86/kernel/cpu/microcode/amd.o
AR lib/zlib_inflate/built-in.a
CC fs/iomap/direct-io.o
AR drivers/leds/built-in.a
CC arch/x86/kernel/acpi/sleep.o
CC drivers/pci/msi/pcidev_msi.o
CC arch/x86/entry/vdso/vdso32-setup.o
CC drivers/pci/pcie/portdrv.o
CC fs/quota/quota_v2.o
ASN.1 crypto/asymmetric_keys/x509_akid.asn1.[ch]
CC crypto/asymmetric_keys/x509_loader.o
CC arch/x86/lib/kaslr.o
AR fs/nfs_common/built-in.a
CC arch/x86/kernel/cpu/mce/amd.o
CC arch/x86/kernel/cpu/mtrr/generic.o
CC lib/zlib_deflate/deflate_syms.o
CC arch/x86/pci/direct.o
CC lib/crypto/mpi/generic_mpih-rshift.o
CC security/lsm_audit.o
CC arch/x86/mm/pat/memtype_interval.o
CC fs/iomap/fiemap.o
CC arch/x86/kernel/fpu/signal.o
AR fs/notify/inotify/built-in.a
CC fs/notify/fsnotify.o
AR arch/x86/power/built-in.a
AS arch/x86/entry/entry.o
AS arch/x86/kernel/acpi/wakeup_32.o
CC security/keys/keyctl.o
CC crypto/asymmetric_keys/x509_public_key.o
ASN.1 crypto/asymmetric_keys/pkcs7.asn1.[ch]
CC arch/x86/mm/init.o
CC arch/x86/events/core.o
VDSO arch/x86/entry/vdso/vdso32.so.dbg
CC arch/x86/lib/memcpy_32.o
OBJCOPY arch/x86/entry/vdso/vdso32.so
VDSO2C arch/x86/entry/vdso/vdso-image-32.c
CC arch/x86/entry/vdso/vdso-image-32.o
CC sound/core/seq/seq_memory.o
AS arch/x86/lib/memmove_32.o
CC arch/x86/lib/misc.o
CC arch/x86/lib/pc-conf-reg.o
AR lib/zlib_deflate/built-in.a
CC drivers/pci/pcie/rcec.o
CC arch/x86/kernel/cpu/mce/threshold.o
CC ipc/mqueue.o
CC arch/x86/pci/mmconfig-shared.o
CC fs/kernfs/mount.o
CC fs/sysfs/file.o
AR block/partitions/built-in.a
CC block/bdev.o
CC crypto/api.o
CC arch/x86/events/probe.o
AS arch/x86/lib/putuser.o
AS arch/x86/lib/retpoline.o
AR arch/x86/entry/vdso/built-in.a
CC drivers/pci/msi/api.o
AS arch/x86/entry/entry_32.o
CC arch/x86/lib/string_32.o
CC arch/x86/entry/syscall_32.o
AR arch/x86/events/amd/built-in.a
CC arch/x86/kernel/acpi/cstate.o
CC arch/x86/platform/efi/efi_32.o
CC net/ethernet/eth.o
CC arch/x86/lib/strstr_32.o
CC fs/quota/quota_tree.o
CC fs/proc/root.o
CC lib/crypto/mpi/generic_mpih-sub1.o
CC arch/x86/lib/usercopy.o
CC fs/kernfs/inode.o
AR arch/x86/kernel/cpu/microcode/built-in.a
CC arch/x86/pci/fixup.o
AR arch/x86/mm/pat/built-in.a
CC fs/sysfs/dir.o
CC crypto/asymmetric_keys/pkcs7_trust.o
CC drivers/video/console/dummycon.o
AR drivers/idle/built-in.a
CC kernel/sched/build_utility.o
CC fs/notify/notification.o
CC fs/notify/group.o
CC lib/crypto/mpi/generic_mpih-add1.o
CC net/core/request_sock.o
CC arch/x86/lib/usercopy_32.o
CC fs/kernfs/dir.o
CC kernel/locking/semaphore.o
CC ipc/namespace.o
CC arch/x86/kernel/cpu/mtrr/cleanup.o
CC drivers/pci/pcie/aspm.o
CC arch/x86/kernel/fpu/xstate.o
CC sound/core/seq/seq_queue.o
CC crypto/asymmetric_keys/pkcs7_verify.o
AR arch/x86/kernel/acpi/built-in.a
CC arch/x86/mm/init_32.o
CC arch/x86/lib/msr-smp.o
CC net/core/skbuff.o
CC fs/devpts/inode.o
AR sound/drivers/opl3/built-in.a
CC drivers/pci/msi/msi.o
CC arch/x86/kernel/apic/apic_common.o
AR sound/drivers/opl4/built-in.a
CC fs/sysfs/symlink.o
CC fs/iomap/seek.o
AR sound/drivers/mpu401/built-in.a
AR sound/drivers/vx/built-in.a
AR sound/drivers/pcsp/built-in.a
AR sound/drivers/built-in.a
CC arch/x86/events/intel/ds.o
CC drivers/pci/pcie/pme.o
CC drivers/video/backlight/backlight.o
CC fs/kernfs/file.o
AS arch/x86/platform/efi/efi_stub_32.o
CC mm/readahead.o
CC arch/x86/platform/efi/runtime-map.o
CC security/keys/permission.o
AR drivers/pci/pwrctl/built-in.a
CC drivers/video/console/vgacon.o
AR arch/x86/platform/iris/built-in.a
CC ipc/mq_sysctl.o
CC kernel/locking/rwsem.o
CC arch/x86/lib/cache-smp.o
CC fs/proc/base.o
CC fs/proc/generic.o
CC arch/x86/lib/msr.o
CC lib/crypto/mpi/mpicoder.o
CC fs/quota/quota.o
CC fs/notify/mark.o
CC arch/x86/platform/intel/iosf_mbi.o
AR arch/x86/platform/intel-mid/built-in.a
CC crypto/asymmetric_keys/x509.asn1.o
CC arch/x86/mm/fault.o
CC arch/x86/pci/acpi.o
CC crypto/asymmetric_keys/x509_akid.asn1.o
CC arch/x86/entry/common.o
AR arch/x86/kernel/cpu/mce/built-in.a
AS arch/x86/entry/thunk.o
CC net/core/datagram.o
CC crypto/asymmetric_keys/x509_cert_parser.o
CC arch/x86/events/utils.o
CC fs/quota/kqid.o
CC block/fops.o
CC arch/x86/kernel/apic/apic_noop.o
CC io_uring/notif.o
CC arch/x86/kernel/cpu/mtrr/amd.o
AR drivers/char/ipmi/built-in.a
CC lib/lzo/lzo1x_compress.o
CC lib/lz4/lz4_decompress.o
CC sound/core/seq/seq_fifo.o
CC fs/iomap/swapfile.o
AR ipc/built-in.a
CC fs/sysfs/mount.o
CC crypto/cipher.o
AR fs/devpts/built-in.a
CC crypto/compress.o
AR net/ethernet/built-in.a
CC kernel/locking/percpu-rwsem.o
CC lib/lzo/lzo1x_decompress_safe.o
CC fs/notify/fdinfo.o
CC security/keys/process_keys.o
CC arch/x86/kernel/apic/ipi.o
AR arch/x86/platform/efi/built-in.a
CC security/keys/request_key.o
CC security/keys/request_key_auth.o
CC sound/core/init.o
AR drivers/video/backlight/built-in.a
CC lib/crypto/chacha.o
AR drivers/video/fbdev/core/built-in.a
CC drivers/pci/msi/irqdomain.o
CC lib/crypto/mpi/mpi-add.o
CC crypto/asymmetric_keys/pkcs7.asn1.o
AR drivers/video/fbdev/omap/built-in.a
CC arch/x86/kernel/cpu/scattered.o
CC crypto/asymmetric_keys/pkcs7_parser.o
AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a
AR net/802/built-in.a
AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a
AR drivers/video/fbdev/omap2/omapfb/built-in.a
AR arch/x86/platform/intel/built-in.a
AR arch/x86/kernel/fpu/built-in.a
CC io_uring/tctx.o
AR drivers/video/fbdev/omap2/built-in.a
CC block/bio.o
AR arch/x86/platform/intel-quark/built-in.a
AR drivers/video/fbdev/built-in.a
AR drivers/pci/pcie/built-in.a
CC arch/x86/kernel/cpu/mtrr/cyrix.o
CC arch/x86/kernel/cpu/mtrr/centaur.o
AR arch/x86/platform/olpc/built-in.a
CC fs/kernfs/symlink.o
AR arch/x86/platform/scx200/built-in.a
AR sound/isa/ad1816a/built-in.a
CC arch/x86/pci/legacy.o
AR drivers/amba/built-in.a
AR arch/x86/platform/ts5500/built-in.a
AR sound/isa/ad1848/built-in.a
CC drivers/pnp/pnpacpi/core.o
CC drivers/acpi/acpica/dsargs.o
CC sound/core/memory.o
AR arch/x86/platform/uv/built-in.a
AR sound/isa/cs423x/built-in.a
AR arch/x86/platform/built-in.a
AR sound/isa/es1688/built-in.a
AS arch/x86/lib/msr-reg.o
AR sound/isa/galaxy/built-in.a
CC kernel/power/qos.o
AR sound/isa/gus/built-in.a
CC arch/x86/lib/msr-reg-export.o
AR sound/isa/msnd/built-in.a
AR sound/isa/opti9xx/built-in.a
AR sound/isa/sb/built-in.a
CC mm/swap.o
AR sound/isa/wavefront/built-in.a
AR arch/x86/entry/built-in.a
AR drivers/video/console/built-in.a
CC drivers/pnp/core.o
CC drivers/video/aperture.o
AR sound/isa/wss/built-in.a
CC drivers/pnp/card.o
AR sound/isa/built-in.a
CC io_uring/filetable.o
CC crypto/algapi.o
CC sound/core/seq/seq_prioq.o
AR lib/lzo/built-in.a
AR drivers/acpi/pmic/built-in.a
CC arch/x86/kernel/cpu/topology_common.o
CC security/selinux/selinuxfs.o
CC lib/crypto/mpi/mpi-bit.o
AS arch/x86/lib/hweight.o
CC arch/x86/lib/iomem.o
CC kernel/locking/spinlock.o
AR fs/iomap/built-in.a
AR fs/notify/built-in.a
CC drivers/video/cmdline.o
CC fs/sysfs/group.o
AR drivers/clk/actions/built-in.a
CC fs/quota/netlink.o
CC arch/x86/kernel/apic/vector.o
AR drivers/clk/analogbits/built-in.a
CC drivers/acpi/acpica/dscontrol.o
AR drivers/clk/bcm/built-in.a
CC block/elevator.o
AR drivers/clk/imgtec/built-in.a
AR drivers/clk/imx/built-in.a
AR drivers/clk/ingenic/built-in.a
CC fs/netfs/buffered_read.o
AR drivers/clk/mediatek/built-in.a
CC fs/ext4/balloc.o
AR drivers/clk/microchip/built-in.a
AR crypto/asymmetric_keys/built-in.a
AR drivers/clk/mstar/built-in.a
AR drivers/clk/mvebu/built-in.a
CC fs/jbd2/transaction.o
AR drivers/clk/ralink/built-in.a
CC fs/ramfs/inode.o
AR drivers/clk/renesas/built-in.a
AR drivers/clk/socfpga/built-in.a
AR drivers/clk/sophgo/built-in.a
AR drivers/clk/sprd/built-in.a
CC fs/hugetlbfs/inode.o
AR drivers/clk/starfive/built-in.a
CC fs/fat/cache.o
CC arch/x86/mm/ioremap.o
AR drivers/clk/sunxi-ng/built-in.a
AR drivers/clk/ti/built-in.a
AR drivers/clk/versatile/built-in.a
CC arch/x86/kernel/cpu/mtrr/legacy.o
CC fs/isofs/namei.o
AR drivers/clk/xilinx/built-in.a
AR drivers/clk/built-in.a
CC arch/x86/mm/extable.o
CC arch/x86/pci/irq.o
CC fs/nfs/client.o
CC drivers/pnp/pnpacpi/rsparser.o
CC arch/x86/lib/atomic64_32.o
CC kernel/locking/osq_lock.o
CC fs/isofs/inode.o
AR drivers/pci/msi/built-in.a
CC arch/x86/lib/inat.o
AR fs/kernfs/built-in.a
CC drivers/pci/hotplug/pci_hotplug_core.o
CC block/blk-core.o
CC arch/x86/events/rapl.o
CC drivers/video/nomodeset.o
CC mm/truncate.o
CC security/keys/user_defined.o
CC drivers/acpi/acpica/dsdebug.o
AR arch/x86/lib/built-in.a
CC sound/core/seq/seq_timer.o
AR arch/x86/lib/lib.a
CC net/core/stream.o
CC lib/crypto/mpi/mpi-cmp.o
CC arch/x86/events/intel/knc.o
CC arch/x86/kernel/cpu/topology_ext.o
AR lib/lz4/built-in.a
CC kernel/locking/qspinlock.o
CC kernel/power/main.o
AR drivers/pci/controller/dwc/built-in.a
CC drivers/acpi/acpica/dsfield.o
AR drivers/pci/controller/mobiveil/built-in.a
CC arch/x86/pci/common.o
AR drivers/pci/controller/plda/built-in.a
AR drivers/pci/controller/built-in.a
CC security/keys/proc.o
CC kernel/printk/printk.o
CC block/blk-sysfs.o
AR arch/x86/kernel/cpu/mtrr/built-in.a
AR fs/sysfs/built-in.a
CC fs/exportfs/expfs.o
CC sound/core/control.o
CC io_uring/rw.o
CC fs/proc/array.o
CC net/core/scm.o
CC arch/x86/kernel/apic/init.o
CC drivers/video/hdmi.o
AR fs/quota/built-in.a
CC arch/x86/kernel/cpu/topology_amd.o
CC security/device_cgroup.o
CC fs/ramfs/file-mmu.o
CC fs/netfs/buffered_write.o
CC arch/x86/events/msr.o
CC kernel/locking/rtmutex_api.o
CC drivers/acpi/acpica/dsinit.o
CC crypto/scatterwalk.o
CC fs/fat/dir.o
CC lib/zstd/zstd_decompress_module.o
CC lib/xz/xz_dec_syms.o
CC lib/crypto/mpi/mpi-sub-ui.o
CC arch/x86/mm/mmap.o
CC lib/zstd/decompress/huf_decompress.o
CC drivers/pci/hotplug/acpi_pcihp.o
CC lib/xz/xz_dec_stream.o
AR drivers/pnp/pnpacpi/built-in.a
CC sound/core/seq/seq_system.o
CC arch/x86/events/intel/lbr.o
CC security/keys/sysctl.o
CC drivers/pnp/driver.o
CC arch/x86/kernel/cpu/common.o
AR fs/exportfs/built-in.a
AR drivers/pci/switch/built-in.a
CC drivers/acpi/dptf/int340x_thermal.o
CC kernel/locking/qrwlock.o
CC lib/dim/dim.o
CC drivers/acpi/acpica/dsmethod.o
CC drivers/acpi/x86/apple.o
CC kernel/irq/irqdesc.o
CC kernel/rcu/update.o
AR kernel/livepatch/built-in.a
CC drivers/acpi/acpica/dsmthdat.o
CC arch/x86/kernel/apic/hw_nmi.o
CC mm/vmscan.o
CC arch/x86/pci/early.o
AR fs/hugetlbfs/built-in.a
CC kernel/power/console.o
CC lib/fonts/fonts.o
CC fs/isofs/dir.o
AR fs/ramfs/built-in.a
CC fs/jbd2/commit.o
AR sound/pci/ac97/built-in.a
CC drivers/acpi/x86/cmos_rtc.o
AR drivers/video/built-in.a
AR sound/pci/ali5451/built-in.a
CC drivers/pnp/resource.o
AR sound/pci/asihpi/built-in.a
CC arch/x86/kernel/kprobes/core.o
AR sound/pci/au88x0/built-in.a
CC arch/x86/kernel/cpu/rdrand.o
CC crypto/proc.o
AR sound/pci/aw2/built-in.a
CC security/selinux/netlink.o
AR sound/pci/ctxfi/built-in.a
AR sound/pci/ca0106/built-in.a
AR sound/pci/cs46xx/built-in.a
AR sound/pci/cs5535audio/built-in.a
CC lib/crypto/mpi/mpi-div.o
AR sound/pci/lola/built-in.a
CC drivers/pnp/manager.o
AR sound/pci/lx6464es/built-in.a
CC lib/xz/xz_dec_lzma2.o
CC fs/proc/fd.o
AR sound/pci/echoaudio/built-in.a
AR sound/pci/emu10k1/built-in.a
CC lib/xz/xz_dec_bcj.o
CC kernel/power/process.o
CC arch/x86/mm/pgtable.o
AR sound/pci/hda/built-in.a
CC lib/dim/net_dim.o
CC [M] sound/pci/hda/hda_bind.o
CC security/keys/keyctl_pkey.o
AR drivers/acpi/dptf/built-in.a
CC arch/x86/mm/physaddr.o
CC sound/core/seq/seq_ports.o
CC kernel/printk/printk_safe.o
CC net/sched/sch_generic.o
CC drivers/acpi/acpica/dsobject.o
CC drivers/acpi/acpica/dsopcode.o
AR kernel/sched/built-in.a
CC lib/argv_split.o
CC lib/fonts/font_8x16.o
CC fs/nfs/dir.o
CC kernel/printk/nbcon.o
AR drivers/pci/hotplug/built-in.a
CC drivers/pci/access.o
CC arch/x86/kernel/apic/io_apic.o
AR kernel/locking/built-in.a
CC arch/x86/kernel/cpu/match.o
CC mm/shrinker.o
CC fs/lockd/clntlock.o
CC arch/x86/pci/bus_numa.o
CC fs/ext4/bitmap.o
CC fs/netfs/direct_read.o
CC io_uring/net.o
CC kernel/irq/handle.o
LDS arch/x86/kernel/vmlinux.lds
CC [M] sound/pci/hda/hda_codec.o
CC drivers/acpi/x86/lpss.o
CC lib/bug.o
CC drivers/acpi/x86/s2idle.o
CC crypto/aead.o
CC fs/isofs/util.o
CC kernel/rcu/sync.o
AR lib/fonts/built-in.a
CC kernel/dma/mapping.o
CC drivers/acpi/acpica/dspkginit.o
CC fs/jbd2/recovery.o
CC fs/jbd2/checkpoint.o
CC lib/crypto/mpi/mpi-mod.o
CC lib/crypto/aes.o
CC arch/x86/pci/amd_bus.o
CC block/blk-flush.o
AR security/keys/built-in.a
CC security/selinux/nlmsgtab.o
CC arch/x86/mm/tlb.o
AR lib/xz/built-in.a
CC lib/dim/rdma_dim.o
CC lib/zstd/decompress/zstd_ddict.o
CC drivers/acpi/acpica/dsutils.o
CC arch/x86/kernel/kprobes/opt.o
CC fs/fat/fatent.o
CC drivers/pnp/support.o
CC arch/x86/events/intel/p4.o
CC fs/nls/nls_base.o
AR sound/ppc/built-in.a
CC lib/crypto/mpi/mpi-mul.o
CC sound/core/seq/seq_info.o
CC lib/zstd/decompress/zstd_decompress.o
CC fs/proc/proc_tty.o
CC arch/x86/events/intel/p6.o
AR sound/pci/ice1712/built-in.a
CC drivers/dma/dw/core.o
AR drivers/soc/apple/built-in.a
CC kernel/irq/manage.o
AR drivers/soc/aspeed/built-in.a
AR drivers/soc/bcm/built-in.a
CC drivers/virtio/virtio.o
AR drivers/soc/fsl/built-in.a
AR drivers/soc/fujitsu/built-in.a
AR drivers/soc/hisilicon/built-in.a
AR drivers/soc/imx/built-in.a
AR fs/unicode/built-in.a
CC drivers/pci/bus.o
CC arch/x86/kernel/cpu/bugs.o
AR drivers/soc/ixp4xx/built-in.a
AR drivers/soc/loongson/built-in.a
CC arch/x86/kernel/cpu/aperfmperf.o
AR drivers/soc/mediatek/built-in.a
AR drivers/soc/microchip/built-in.a
AR drivers/soc/nuvoton/built-in.a
AR drivers/soc/pxa/built-in.a
AR drivers/soc/amlogic/built-in.a
CC fs/ext4/block_validity.o
AR lib/dim/built-in.a
AR drivers/soc/qcom/built-in.a
AR drivers/soc/renesas/built-in.a
CC kernel/printk/printk_ringbuffer.o
CC drivers/pnp/interface.o
AR drivers/soc/rockchip/built-in.a
CC kernel/power/suspend.o
AR drivers/soc/sunxi/built-in.a
CC fs/isofs/rock.o
CC drivers/pnp/quirks.o
AR drivers/soc/ti/built-in.a
CC fs/netfs/direct_write.o
AR drivers/soc/versatile/built-in.a
CC drivers/acpi/x86/utils.o
CC arch/x86/kernel/apic/msi.o
AR drivers/soc/xilinx/built-in.a
AR drivers/soc/built-in.a
CC block/blk-settings.o
CC drivers/virtio/virtio_ring.o
CC drivers/acpi/acpica/dswexec.o
CC arch/x86/mm/cpu_entry_area.o
CC security/selinux/netif.o
CC drivers/pci/probe.o
CC fs/nls/nls_cp437.o
CC sound/core/seq/seq_dummy.o
CC crypto/geniv.o
CC lib/crypto/arc4.o
AR arch/x86/pci/built-in.a
CC [M] sound/pci/hda/hda_jack.o
CC lib/crypto/mpi/mpih-cmp.o
AS arch/x86/kernel/head_32.o
CC fs/proc/cmdline.o
CC fs/lockd/clntproc.o
CC drivers/pci/host-bridge.o
CC fs/nfs/file.o
AR arch/x86/kernel/kprobes/built-in.a
CC arch/x86/kernel/cpu/cpuid-deps.o
CC fs/jbd2/revoke.o
CC fs/jbd2/journal.o
CC lib/zstd/decompress/zstd_decompress_block.o
CC drivers/acpi/acpica/dswload.o
CC drivers/pnp/system.o
CC drivers/acpi/x86/blacklist.o
CC arch/x86/kernel/apic/probe_32.o
CC fs/nls/nls_ascii.o
CC drivers/dma/hsu/hsu.o
CC arch/x86/kernel/cpu/umwait.o
CC drivers/acpi/tables.o
MKCAP arch/x86/kernel/cpu/capflags.c
CC arch/x86/events/intel/pt.o
CC lib/crypto/gf128mul.o
CC arch/x86/mm/maccess.o
CC kernel/printk/sysctl.o
CC lib/zstd/zstd_common_module.o
CC net/core/gen_stats.o
CC drivers/dma/dw/dw.o
CC fs/fat/file.o
AR sound/core/seq/built-in.a
CC lib/crypto/mpi/mpih-div.o
CC sound/core/misc.o
CC lib/buildid.o
CC fs/ext4/dir.o
CC fs/isofs/export.o
CC kernel/rcu/srcutree.o
CC fs/autofs/init.o
CC arch/x86/mm/pgprot.o
CC fs/proc/consoles.o
CC drivers/acpi/acpica/dswload2.o
CC net/sched/sch_mq.o
CC fs/nls/nls_iso8859-1.o
CC arch/x86/events/intel/uncore.o
CC fs/netfs/iterator.o
CC block/blk-ioc.o
AR arch/x86/kernel/apic/built-in.a
CC arch/x86/events/intel/uncore_nhmex.o
AR drivers/acpi/x86/built-in.a
CC arch/x86/kernel/head32.o
CC arch/x86/kernel/ebda.o
AR kernel/printk/built-in.a
CC arch/x86/kernel/platform-quirks.o
AR drivers/pnp/built-in.a
CC arch/x86/kernel/process_32.o
CC kernel/power/hibernate.o
CC io_uring/poll.o
AR sound/arm/built-in.a
CC security/selinux/netnode.o
CC crypto/lskcipher.o
CC kernel/irq/spurious.o
CC kernel/dma/direct.o
CC arch/x86/events/intel/uncore_snb.o
CC drivers/dma/dw/idma32.o
CC fs/nls/nls_utf8.o
CC drivers/dma/dw/acpi.o
CC fs/fat/inode.o
CC lib/crypto/mpi/mpih-mul.o
CC drivers/acpi/acpica/dswscope.o
AR drivers/dma/hsu/built-in.a
CC drivers/acpi/osi.o
CC crypto/skcipher.o
CC mm/shmem.o
CC arch/x86/mm/pgtable_32.o
CC fs/proc/cpuinfo.o
CC sound/core/device.o
CC [M] sound/pci/hda/hda_auto_parser.o
CC arch/x86/mm/iomap_32.o
CC fs/isofs/joliet.o
CC fs/lockd/clntxdr.o
CC fs/autofs/inode.o
CC fs/isofs/compress.o
CC kernel/irq/resend.o
CC fs/nfs/getroot.o
AR fs/nls/built-in.a
CC kernel/entry/common.o
AR drivers/dma/idxd/built-in.a
CC kernel/rcu/tree.o
CC security/selinux/netport.o
CC net/netlink/af_netlink.o
CC drivers/virtio/virtio_anchor.o
AR net/bpf/built-in.a
CC drivers/acpi/acpica/dswstate.o
CC block/blk-map.o
CC kernel/module/main.o
CC net/core/gen_estimator.o
CC drivers/pci/remove.o
CC fs/ext4/ext4_jbd2.o
CC fs/ext4/extents.o
CC net/core/net_namespace.o
CC sound/core/info.o
CC net/sched/sch_frag.o
CC net/core/secure_seq.o
CC kernel/rcu/rcu_segcblist.o
AR drivers/dma/dw/built-in.a
CC fs/9p/vfs_super.o
AR drivers/dma/amd/built-in.a
CC fs/proc/devices.o
CC fs/netfs/locking.o
AR drivers/dma/mediatek/built-in.a
CC kernel/irq/chip.o
AR drivers/dma/qcom/built-in.a
AR drivers/dma/stm32/built-in.a
AR fs/hostfs/built-in.a
AR drivers/dma/ti/built-in.a
CC fs/lockd/host.o
AR drivers/dma/xilinx/built-in.a
CC drivers/dma/dmaengine.o
CC net/sched/sch_api.o
CC arch/x86/mm/hugetlbpage.o
CC arch/x86/mm/dump_pagetables.o
CC lib/crypto/mpi/mpi-pow.o
CC kernel/dma/ops_helpers.o
CC fs/lockd/svc.o
CC drivers/acpi/acpica/evevent.o
CC drivers/virtio/virtio_pci_modern_dev.o
CC fs/proc/interrupts.o
CC fs/fat/misc.o
CC io_uring/eventfd.o
CC fs/autofs/root.o
CC kernel/irq/dummychip.o
AR fs/isofs/built-in.a
CC lib/crypto/blake2s.o
CC drivers/pci/pci.o
CC kernel/power/snapshot.o
CC fs/autofs/symlink.o
CC drivers/acpi/acpica/evgpe.o
CC crypto/seqiv.o
CC [M] sound/pci/hda/hda_sysfs.o
CC arch/x86/events/intel/uncore_snbep.o
CC kernel/entry/syscall_user_dispatch.o
CC fs/nfs/inode.o
CC sound/core/isadma.o
CC lib/zstd/common/debug.o
CC lib/clz_tab.o
CC lib/zstd/common/entropy_common.o
CC arch/x86/events/intel/uncore_discovery.o
CC drivers/acpi/osl.o
CC fs/proc/loadavg.o
CC fs/ext4/extents_status.o
CC block/blk-merge.o
CC fs/9p/vfs_inode.o
CC kernel/module/strict_rwx.o
CC fs/nfs/super.o
CC arch/x86/events/intel/cstate.o
CC fs/fat/nfs.o
CC kernel/dma/remap.o
CC net/sched/sch_blackhole.o
CC security/selinux/status.o
CC crypto/echainiv.o
CC lib/crypto/mpi/mpiutil.o
CC lib/zstd/common/error_private.o
CC lib/zstd/common/fse_decompress.o
CC arch/x86/mm/highmem_32.o
CC fs/netfs/main.o
AR fs/jbd2/built-in.a
CC fs/nfs/io.o
CC drivers/virtio/virtio_pci_legacy_dev.o
CC kernel/irq/devres.o
CC io_uring/uring_cmd.o
CC drivers/acpi/acpica/evgpeblk.o
CC sound/core/vmaster.o
CC fs/nfs/direct.o
CC block/blk-timeout.o
CC io_uring/openclose.o
CC kernel/power/swap.o
AR kernel/entry/built-in.a
CC drivers/acpi/utils.o
CC fs/autofs/waitq.o
CC [M] sound/pci/hda/hda_controller.o
CC net/ethtool/ioctl.o
CC fs/proc/meminfo.o
CC drivers/dma/virt-dma.o
CC net/ethtool/common.o
CC net/core/flow_dissector.o
CC fs/9p/vfs_inode_dotl.o
AR kernel/dma/built-in.a
CC arch/x86/kernel/signal.o
CC fs/lockd/svclock.o
CC lib/zstd/common/zstd_common.o
AR lib/crypto/mpi/built-in.a
CC lib/crypto/blake2s-generic.o
CC crypto/ahash.o
CC kernel/irq/autoprobe.o
CC drivers/acpi/acpica/evgpeinit.o
AR lib/zstd/built-in.a
CC crypto/shash.o
AR arch/x86/mm/built-in.a
CC fs/nfs/pagelist.o
CC fs/fat/namei_vfat.o
CC drivers/virtio/virtio_pci_modern.o
CC block/blk-lib.o
CC sound/core/ctljack.o
CC [M] sound/pci/hda/hda_proc.o
CC [M] sound/pci/hda/hda_hwdep.o
CC fs/lockd/svcshare.o
CC security/selinux/ss/ebitmap.o
CC kernel/module/kmod.o
CC kernel/module/tree_lookup.o
CC drivers/acpi/acpica/evgpeutil.o
CC fs/debugfs/inode.o
CC mm/util.o
CC mm/mmzone.o
CC lib/crypto/sha1.o
CC drivers/dma/acpi-dma.o
CC drivers/acpi/acpica/evglock.o
CC kernel/irq/irqdomain.o
CC net/netlink/genetlink.o
CC fs/proc/stat.o
CC fs/autofs/expire.o
CC net/netlink/policy.o
CC fs/autofs/dev-ioctl.o
CC net/sched/cls_api.o
CC sound/core/jack.o
CC net/core/sysctl_net_core.o
CC drivers/pci/pci-driver.o
CC net/ethtool/netlink.o
CC net/ethtool/bitset.o
CC net/core/dev.o
CC io_uring/sqpoll.o
CC fs/9p/vfs_addr.o
CC lib/crypto/sha256.o
CC drivers/acpi/acpica/evhandler.o
CC arch/x86/kernel/cpu/powerflags.o
CC mm/vmstat.o
CC block/blk-mq.o
CC security/selinux/ss/hashtab.o
CC drivers/virtio/virtio_pci_common.o
CC kernel/power/user.o
CC drivers/acpi/acpica/evmisc.o
CC io_uring/xattr.o
CC crypto/akcipher.o
CC io_uring/nop.o
CC fs/lockd/svcproc.o
CC fs/proc/uptime.o
CC fs/netfs/misc.o
CC mm/backing-dev.o
CC kernel/module/kallsyms.o
CC arch/x86/kernel/cpu/topology.o
AR drivers/dma/built-in.a
CC arch/x86/kernel/signal_32.o
CC kernel/futex/core.o
CC kernel/time/time.o
AR arch/x86/events/intel/built-in.a
AR arch/x86/events/built-in.a
CC fs/fat/namei_msdos.o
CC fs/debugfs/file.o
CC fs/tracefs/inode.o
CC sound/core/timer.o
CC drivers/acpi/acpica/evregion.o
CC [M] fs/efivarfs/inode.o
CC [M] sound/pci/hda/patch_hdmi.o
AR lib/crypto/built-in.a
CC lib/cmdline.o
CC lib/cpumask.o
CC [M] fs/efivarfs/file.o
AR fs/autofs/built-in.a
CC fs/proc/util.o
CC kernel/module/procfs.o
CC security/selinux/ss/symtab.o
CC fs/9p/vfs_file.o
CC kernel/irq/proc.o
CC net/core/dev_addr_lists.o
CC net/ethtool/strset.o
CC kernel/power/poweroff.o
CC security/selinux/ss/sidtab.o
CC sound/core/hrtimer.o
CC arch/x86/kernel/cpu/proc.o
CC drivers/acpi/acpica/evrgnini.o
CC crypto/sig.o
CC [M] fs/efivarfs/super.o
CC net/sched/act_api.o
CC drivers/virtio/virtio_pci_legacy.o
CC fs/9p/vfs_dir.o
CC kernel/futex/syscalls.o
CC kernel/cgroup/cgroup.o
CC drivers/acpi/reboot.o
CC crypto/kpp.o
CC drivers/pci/search.o
CC kernel/futex/pi.o
AR kernel/power/built-in.a
CC [M] sound/pci/hda/hda_eld.o
CC drivers/acpi/acpica/evsci.o
CC lib/ctype.o
CC fs/proc/version.o
CC fs/proc/softirqs.o
CC lib/dec_and_lock.o
CC fs/lockd/svcsubs.o
CC kernel/module/sysfs.o
AR sound/pci/korg1212/built-in.a
CC fs/open.o
CC lib/decompress.o
CC drivers/tty/vt/vt_ioctl.o
AR sound/pci/mixart/built-in.a
AR net/netlink/built-in.a
AR kernel/rcu/built-in.a
CC arch/x86/kernel/cpu/feat_ctl.o
CC security/selinux/ss/avtab.o
CC drivers/char/hw_random/core.o
CC net/core/dst.o
CC fs/tracefs/event_inode.o
CC fs/netfs/objects.o
CC lib/decompress_bunzip2.o
CC kernel/time/timer.o
CC kernel/time/hrtimer.o
AR fs/fat/built-in.a
CC kernel/futex/requeue.o
CC fs/nfs/read.o
CC kernel/irq/migration.o
CC io_uring/fs.o
CC [M] fs/efivarfs/vars.o
CC drivers/virtio/virtio_pci_admin_legacy_io.o
CC drivers/acpi/acpica/evxface.o
CC fs/read_write.o
CC mm/mm_init.o
CC kernel/cgroup/rstat.o
AR fs/debugfs/built-in.a
CC mm/percpu.o
CC mm/slab_common.o
CC fs/proc/namespaces.o
CC drivers/pci/rom.o
AR sound/pci/nm256/built-in.a
CC fs/file_table.o
AR sound/pci/oxygen/built-in.a
CC arch/x86/kernel/traps.o
CC fs/9p/vfs_dentry.o
CC fs/9p/v9fs.o
CC arch/x86/kernel/cpu/intel.o
CC fs/ext4/file.o
CC drivers/char/agp/backend.o
CC drivers/char/mem.o
ASN.1 crypto/rsapubkey.asn1.[ch]
ASN.1 crypto/rsaprivkey.asn1.[ch]
CC fs/lockd/mon.o
CC crypto/rsa.o
CC kernel/irq/cpuhotplug.o
AR kernel/module/built-in.a
CC sound/core/seq_device.o
CC fs/9p/fid.o
AR sound/pci/pcxhr/built-in.a
CC lib/decompress_inflate.o
CC net/ethtool/linkinfo.o
CC block/blk-mq-tag.o
CC drivers/acpi/acpica/evxfevnt.o
CC net/core/netevent.o
AR drivers/iommu/amd/built-in.a
CC kernel/futex/waitwake.o
CC drivers/char/hw_random/intel-rng.o
AR drivers/iommu/intel/built-in.a
CC kernel/cgroup/namespace.o
CC drivers/virtio/virtio_input.o
AR drivers/iommu/arm/arm-smmu/built-in.a
AR drivers/iommu/arm/arm-smmu-v3/built-in.a
AR drivers/iommu/arm/built-in.a
AR drivers/iommu/iommufd/built-in.a
CC drivers/iommu/iommu.o
LD [M] fs/efivarfs/efivarfs.o
CC fs/lockd/trace.o
CC block/blk-stat.o
CC drivers/tty/vt/vc_screen.o
CC drivers/pci/setup-res.o
AR fs/tracefs/built-in.a
CC drivers/tty/vt/selection.o
CC io_uring/splice.o
CC net/ethtool/linkmodes.o
CC drivers/acpi/acpica/evxfgpe.o
CC fs/9p/xattr.o
CC fs/netfs/read_collect.o
CC fs/proc/self.o
CC lib/decompress_unlz4.o
CC drivers/char/agp/generic.o
CC crypto/rsa_helper.o
CC security/selinux/ss/policydb.o
CC [M] sound/core/hwdep.o
CC drivers/char/agp/isoch.o
CC mm/compaction.o
CC [M] sound/pci/hda/hda_intel.o
CC crypto/rsa-pkcs1pad.o
CC kernel/irq/pm.o
CC block/blk-mq-sysfs.o
CC arch/x86/kernel/cpu/tsx.o
CC fs/netfs/read_pgpriv2.o
CC net/ethtool/rss.o
CC kernel/irq/msi.o
CC net/sched/sch_fifo.o
CC net/sched/cls_cgroup.o
CC drivers/virtio/virtio_dma_buf.o
CC drivers/char/hw_random/amd-rng.o
CC drivers/acpi/acpica/evxfregn.o
AR kernel/futex/built-in.a
CC fs/ext4/fsmap.o
CC drivers/tty/vt/keyboard.o
CC drivers/iommu/iommu-traces.o
CC drivers/tty/hvc/hvc_console.o
CC drivers/iommu/iommu-sysfs.o
CC block/blk-mq-cpumap.o
CC mm/show_mem.o
AR drivers/gpu/host1x/built-in.a
CC drivers/char/agp/amd64-agp.o
CC lib/decompress_unlzma.o
CC fs/proc/thread_self.o
CC net/netfilter/core.o
CC drivers/char/agp/intel-agp.o
AR drivers/gpu/drm/tests/built-in.a
AR drivers/gpu/drm/arm/built-in.a
CC drivers/pci/irq.o
CC drivers/gpu/drm/display/drm_display_helper_mod.o
CC drivers/char/random.o
AR fs/9p/built-in.a
AR sound/sh/built-in.a
CC drivers/iommu/dma-iommu.o
CC fs/nfs/symlink.o
CC fs/lockd/xdr.o
CC arch/x86/kernel/cpu/intel_epb.o
CC io_uring/sync.o
CC drivers/acpi/acpica/exconcat.o
CC drivers/acpi/nvs.o
CC [M] sound/core/pcm.o
CC kernel/time/timekeeping.o
AR sound/pci/riptide/built-in.a
CC arch/x86/kernel/idt.o
CC fs/ext4/fsync.o
CC block/blk-mq-sched.o
AR drivers/gpu/vga/built-in.a
CC drivers/char/hw_random/geode-rng.o
CC crypto/acompress.o
CC fs/lockd/clnt4xdr.o
CC drivers/acpi/wakeup.o
AR drivers/virtio/built-in.a
CC fs/ext4/hash.o
CC kernel/trace/trace_clock.o
CC drivers/gpu/drm/display/drm_dp_dual_mode_helper.o
CC kernel/bpf/core.o
CC fs/proc/proc_sysctl.o
CC mm/interval_tree.o
CC drivers/tty/vt/vt.o
AR sound/synth/emux/built-in.a
AR sound/synth/built-in.a
CC kernel/events/core.o
CC arch/x86/kernel/cpu/amd.o
CC drivers/acpi/acpica/exconfig.o
CC fs/nfs/unlink.o
CC fs/netfs/read_retry.o
CC drivers/gpu/drm/ttm/ttm_tt.o
AR drivers/tty/hvc/built-in.a
CC lib/decompress_unlzo.o
CC kernel/irq/affinity.o
CC net/ethtool/linkstate.o
CC drivers/pci/vpd.o
CC kernel/cgroup/cgroup-v1.o
CC io_uring/msg_ring.o
CC crypto/scompress.o
CC fs/netfs/write_collect.o
CC drivers/char/agp/intel-gtt.o
CC net/sched/ematch.o
CC kernel/trace/ring_buffer.o
CC [M] sound/core/pcm_native.o
CC drivers/gpu/drm/display/drm_dp_helper.o
CC fs/super.o
CC drivers/char/hw_random/via-rng.o
CC drivers/acpi/acpica/exconvrt.o
CC mm/list_lru.o
CC net/netfilter/nf_log.o
CC kernel/cgroup/freezer.o
CC kernel/fork.o
CC kernel/events/ring_buffer.o
LD [M] sound/pci/hda/snd-hda-codec.o
CC drivers/tty/serial/8250/8250_core.o
AR drivers/tty/ipwireless/built-in.a
LD [M] sound/pci/hda/snd-hda-codec-hdmi.o
CC kernel/time/ntp.o
LD [M] sound/pci/hda/snd-hda-intel.o
CC kernel/irq/matrix.o
AR sound/pci/rme9652/built-in.a
CC fs/lockd/xdr4.o
AR sound/pci/trident/built-in.a
AR sound/pci/ymfpci/built-in.a
AR sound/pci/vx222/built-in.a
AR sound/pci/built-in.a
CC drivers/tty/serial/8250/8250_platform.o
CC drivers/acpi/sleep.o
CC kernel/cgroup/legacy_freezer.o
CC lib/decompress_unxz.o
CC fs/proc/proc_net.o
CC block/ioctl.o
CC kernel/time/clocksource.o
AR drivers/char/hw_random/built-in.a
CC net/ipv4/netfilter/nf_defrag_ipv4.o
CC net/ipv4/route.o
CC drivers/gpu/drm/ttm/ttm_bo.o
CC drivers/acpi/acpica/excreate.o
CC drivers/iommu/iova.o
CC arch/x86/kernel/cpu/hygon.o
CC drivers/pci/setup-bus.o
CC arch/x86/kernel/cpu/centaur.o
CC crypto/algboss.o
CC io_uring/advise.o
CC io_uring/epoll.o
CC net/ethtool/debug.o
CC drivers/acpi/acpica/exdebug.o
CC drivers/acpi/acpica/exdump.o
CC lib/decompress_unzstd.o
CC drivers/gpu/drm/ttm/ttm_bo_util.o
CC net/ipv4/netfilter/nf_reject_ipv4.o
AR drivers/char/agp/built-in.a
CC drivers/char/misc.o
AR net/sched/built-in.a
CC net/ethtool/wol.o
CC drivers/tty/serial/serial_core.o
CC security/selinux/ss/services.o
CC kernel/events/callchain.o
CC mm/workingset.o
CC fs/ext4/ialloc.o
CC arch/x86/kernel/cpu/transmeta.o
CC lib/dump_stack.o
CC drivers/gpu/drm/display/drm_dp_mst_topology.o
CC drivers/gpu/drm/i915/i915_config.o
CC net/netfilter/nf_queue.o
CC mm/debug.o
CC drivers/tty/serial/8250/8250_pnp.o
CC kernel/cgroup/pids.o
AR drivers/gpu/drm/renesas/rcar-du/built-in.a
CC drivers/acpi/acpica/exfield.o
AR drivers/gpu/drm/renesas/rz-du/built-in.a
AR drivers/gpu/drm/renesas/built-in.a
CC fs/proc/kcore.o
CC drivers/char/virtio_console.o
CC fs/netfs/write_issue.o
CC kernel/time/jiffies.o
CC net/ipv4/netfilter/ip_tables.o
CC kernel/time/timer_list.o
CC crypto/testmgr.o
CC drivers/gpu/drm/i915/i915_driver.o
CC lib/earlycpio.o
CC fs/lockd/svc4proc.o
AR drivers/iommu/built-in.a
CC drivers/gpu/drm/ttm/ttm_bo_vm.o
CC drivers/gpu/drm/i915/i915_drm_client.o
CC block/genhd.o
CC net/ipv4/netfilter/iptable_filter.o
AR kernel/irq/built-in.a
AR drivers/gpu/drm/omapdrm/built-in.a
AR drivers/gpu/drm/tilcdc/built-in.a
CC kernel/trace/trace.o
CC drivers/gpu/drm/i915/i915_getparam.o
CC net/ipv4/inetpeer.o
CC net/xfrm/xfrm_policy.o
CC drivers/acpi/acpica/exfldio.o
CC kernel/cgroup/rdma.o
CC io_uring/statx.o
CC fs/nfs/write.o
CC lib/extable.o
CC fs/lockd/procfs.o
CC arch/x86/kernel/cpu/zhaoxin.o
CC net/unix/af_unix.o
CC crypto/cmac.o
CC drivers/acpi/acpica/exmisc.o
CC net/ipv6/netfilter/ip6_tables.o
CC net/ethtool/features.o
CC block/ioprio.o
CC io_uring/timeout.o
CC fs/ext4/indirect.o
CC drivers/tty/serial/8250/8250_rsa.o
COPY drivers/tty/vt/defkeymap.c
CC drivers/tty/vt/consolemap.o
CC drivers/char/hpet.o
CC mm/gup.o
CC kernel/time/timeconv.o
CC lib/flex_proportions.o
CC arch/x86/kernel/cpu/vortex.o
CC fs/proc/vmcore.o
CC drivers/tty/serial/serial_base_bus.o
CC drivers/acpi/acpica/exmutex.o
CC drivers/gpu/drm/ttm/ttm_module.o
CC drivers/acpi/acpica/exnames.o
CC crypto/hmac.o
AR kernel/bpf/built-in.a
CC kernel/trace/trace_output.o
CC drivers/pci/vc.o
CC kernel/cgroup/cpuset.o
CC kernel/trace/trace_seq.o
CC net/netfilter/nf_sockopt.o
CC kernel/time/timecounter.o
CC lib/idr.o
CC kernel/time/alarmtimer.o
CC arch/x86/kernel/cpu/perfctr-watchdog.o
AR fs/netfs/built-in.a
CC kernel/trace/trace_stat.o
CC fs/nfs/namespace.o
CC net/ipv6/netfilter/ip6table_filter.o
CC arch/x86/kernel/irq.o
AR fs/lockd/built-in.a
CC security/selinux/ss/conditional.o
CC drivers/tty/tty_io.o
CC net/ipv4/protocol.o
CC drivers/tty/serial/8250/8250_port.o
CC drivers/tty/serial/8250/8250_dma.o
CC drivers/acpi/acpica/exoparg1.o
AR sound/usb/misc/built-in.a
AR sound/usb/usx2y/built-in.a
AR sound/usb/caiaq/built-in.a
CC security/selinux/ss/mls.o
HOSTCC drivers/tty/vt/conmakehash
AR sound/usb/6fire/built-in.a
CC block/badblocks.o
AR sound/usb/hiface/built-in.a
CC [M] sound/core/pcm_lib.o
AR sound/usb/bcd2000/built-in.a
AR sound/usb/built-in.a
CC drivers/gpu/drm/ttm/ttm_execbuf_util.o
CC drivers/connector/cn_queue.o
CC drivers/gpu/drm/virtio/virtgpu_drv.o
CC net/ipv4/netfilter/iptable_mangle.o
CC net/ethtool/privflags.o
CC arch/x86/kernel/cpu/vmware.o
CC crypto/crypto_null.o
CC drivers/tty/vt/defkeymap.o
CC drivers/connector/connector.o
CC net/netfilter/utils.o
CC drivers/char/nvram.o
CC drivers/pci/mmap.o
CC net/core/neighbour.o
CC lib/irq_regs.o
CC io_uring/fdinfo.o
CC drivers/gpu/drm/i915/i915_ioctl.o
CONMK drivers/tty/vt/consolemap_deftbl.c
CC drivers/tty/vt/consolemap_deftbl.o
CC arch/x86/kernel/irq_32.o
CC fs/proc/kmsg.o
AR drivers/tty/vt/built-in.a
CC drivers/acpi/acpica/exoparg2.o
CC drivers/gpu/drm/display/drm_dsc_helper.o
CC crypto/md5.o
CC block/blk-rq-qos.o
CC lib/is_single_threaded.o
CC fs/ext4/inline.o
CC drivers/gpu/drm/ttm/ttm_range_manager.o
CC net/ipv6/af_inet6.o
CC kernel/exec_domain.o
CC drivers/gpu/drm/virtio/virtgpu_kms.o
CC kernel/cgroup/misc.o
AR sound/firewire/built-in.a
CC drivers/pci/devres.o
CC arch/x86/kernel/cpu/hypervisor.o
CC net/ethtool/rings.o
CC [M] sound/core/pcm_misc.o
CC net/packet/af_packet.o
CC kernel/time/posix-timers.o
CC drivers/acpi/acpica/exoparg3.o
CC fs/nfs/mount_clnt.o
CC lib/klist.o
CC net/ethtool/channels.o
CC fs/proc/page.o
CC drivers/gpu/drm/ttm/ttm_resource.o
CC fs/char_dev.o
CC crypto/sha256_generic.o
CC net/ipv6/netfilter/ip6table_mangle.o
CC net/core/rtnetlink.o
AR drivers/char/built-in.a
AR net/dsa/built-in.a
CC net/unix/garbage.o
CC arch/x86/kernel/cpu/mshyperv.o
CC drivers/gpu/drm/i915/i915_irq.o
CC net/ipv4/netfilter/ipt_REJECT.o
CC [M] net/ipv4/netfilter/iptable_nat.o
CC security/selinux/ss/context.o
CC drivers/gpu/drm/ttm/ttm_pool.o
CC block/disk-events.o
CC lib/kobject.o
CC drivers/connector/cn_proc.o
CC drivers/acpi/acpica/exoparg6.o
CC lib/kobject_uevent.o
CC io_uring/cancel.o
CC kernel/panic.o
CC fs/stat.o
CC kernel/cpu.o
CC mm/mmap_lock.o
CC kernel/exit.o
CC drivers/gpu/drm/display/drm_hdcp_helper.o
CC kernel/softirq.o
CC net/netfilter/nfnetlink.o
CC arch/x86/kernel/cpu/debugfs.o
CC drivers/gpu/drm/virtio/virtgpu_gem.o
CC drivers/tty/serial/serial_ctrl.o
CC kernel/events/hw_breakpoint.o
CC crypto/sha512_generic.o
CC drivers/pci/proc.o
CC kernel/time/posix-cpu-timers.o
AR fs/proc/built-in.a
CC drivers/acpi/acpica/exprep.o
CC crypto/sha3_generic.o
CC [M] sound/core/pcm_memory.o
CC drivers/tty/n_tty.o
CC kernel/cgroup/debug.o
AR drivers/gpu/drm/imx/built-in.a
CC io_uring/waitid.o
CC net/core/utils.o
CC drivers/tty/serial/8250/8250_dwlib.o
CC block/blk-ia-ranges.o
CC drivers/gpu/drm/i915/i915_mitigations.o
CC net/ethtool/coalesce.o
CC fs/nfs/nfstrace.o
AR sound/sparc/built-in.a
CC net/ipv6/anycast.o
CC net/ipv6/ip6_output.o
CC arch/x86/kernel/cpu/capflags.o
CC drivers/acpi/acpica/exregion.o
CC security/selinux/netlabel.o
AR arch/x86/kernel/cpu/built-in.a
CC arch/x86/kernel/dumpstack_32.o
CC net/xfrm/xfrm_state.o
CC kernel/events/uprobes.o
CC net/xfrm/xfrm_hash.o
CC drivers/gpu/drm/ttm/ttm_device.o
CC drivers/gpu/drm/display/drm_hdmi_helper.o
CC net/ipv6/netfilter/nf_defrag_ipv6_hooks.o
CC net/unix/sysctl_net_unix.o
CC lib/logic_pio.o
CC lib/maple_tree.o
CC fs/ext4/inode.o
CC mm/highmem.o
CC net/ethtool/pause.o
AR net/ipv4/netfilter/built-in.a
CC net/ipv4/ip_input.o
CC drivers/gpu/drm/virtio/virtgpu_vram.o
CC [M] sound/core/memalloc.o
CC crypto/ecb.o
AR drivers/connector/built-in.a
CC net/sunrpc/clnt.o
CC net/sunrpc/auth_gss/auth_gss.o
CC drivers/tty/serial/8250/8250_pcilib.o
CC net/sunrpc/xprt.o
CC kernel/time/posix-clock.o
CC io_uring/register.o
CC drivers/acpi/acpica/exresnte.o
CC drivers/pci/pci-sysfs.o
CC drivers/acpi/acpica/exresolv.o
CC net/netfilter/nfnetlink_log.o
AR kernel/cgroup/built-in.a
CC kernel/trace/trace_printk.o
CC net/ethtool/eee.o
CC block/early-lookup.o
CC kernel/trace/pid_list.o
CC net/ipv4/ip_fragment.o
CC drivers/gpu/drm/ttm/ttm_sys_manager.o
CC mm/memory.o
CC arch/x86/kernel/time.o
CC crypto/cbc.o
CC net/sunrpc/socklib.o
CC drivers/gpu/drm/display/drm_scdc_helper.o
AR drivers/gpu/drm/i2c/built-in.a
CC net/ethtool/tsinfo.o
CC drivers/acpi/acpica/exresop.o
CC drivers/gpu/drm/i915/i915_module.o
CC kernel/resource.o
CC [M] sound/core/pcm_timer.o
AR net/wireless/tests/built-in.a
CC net/wireless/core.o
CC drivers/gpu/drm/virtio/virtgpu_display.o
AR net/unix/built-in.a
CC net/ethtool/cabletest.o
CC drivers/pci/slot.o
CC drivers/tty/serial/8250/8250_early.o
CC arch/x86/kernel/ioport.o
AR sound/spi/built-in.a
CC fs/nfs/export.o
CC net/sunrpc/auth_gss/gss_generic_token.o
CC block/bounce.o
CC drivers/gpu/drm/ttm/ttm_agp_backend.o
AR drivers/gpu/drm/panel/built-in.a
CC crypto/ctr.o
CC crypto/gcm.o
CC kernel/time/itimer.o
CC lib/memcat_p.o
CC net/wireless/sysfs.o
CC drivers/acpi/acpica/exserial.o
CC arch/x86/kernel/dumpstack.o
CC arch/x86/kernel/nmi.o
CC net/ipv6/netfilter/nf_conntrack_reasm.o
AR net/mac80211/tests/built-in.a
CC net/mac80211/main.o
AR security/selinux/built-in.a
AR security/built-in.a
CC fs/nfs/sysfs.o
CC mm/mincore.o
CC mm/mlock.o
CC kernel/trace/trace_sched_switch.o
CC io_uring/truncate.o
CC drivers/acpi/device_sysfs.o
AR drivers/gpu/drm/display/built-in.a
CC arch/x86/kernel/ldt.o
LD [M] sound/core/snd-hwdep.o
LD [M] sound/core/snd-pcm.o
AR sound/core/built-in.a
CC drivers/acpi/acpica/exstore.o
AR sound/parisc/built-in.a
CC net/ipv6/netfilter/nf_reject_ipv6.o
AR sound/pcmcia/vx/built-in.a
AR sound/pcmcia/pdaudiocf/built-in.a
AR sound/pcmcia/built-in.a
AR sound/mips/built-in.a
AR sound/soc/built-in.a
CC drivers/base/power/sysfs.o
AR sound/atmel/built-in.a
CC drivers/block/loop.o
CC drivers/gpu/drm/virtio/virtgpu_vq.o
AR sound/hda/built-in.a
CC [M] sound/hda/hda_bus_type.o
CC drivers/tty/serial/8250/8250_exar.o
AR kernel/events/built-in.a
CC [M] sound/hda/hdac_bus.o
CC [M] sound/hda/hdac_device.o
CC drivers/pci/pci-acpi.o
CC drivers/base/firmware_loader/builtin/main.o
AR drivers/gpu/drm/ttm/built-in.a
CC drivers/base/regmap/regmap.o
CC drivers/gpu/drm/virtio/virtgpu_fence.o
CC drivers/block/virtio_blk.o
CC drivers/base/firmware_loader/main.o
AR net/packet/built-in.a
CC block/bsg.o
CC drivers/gpu/drm/i915/i915_params.o
CC net/netfilter/nf_conntrack_core.o
CC net/ipv4/ip_forward.o
CC drivers/acpi/acpica/exstoren.o
CC net/ipv6/netfilter/ip6t_ipv6header.o
CC fs/ext4/ioctl.o
AR drivers/base/firmware_loader/builtin/built-in.a
CC kernel/trace/trace_nop.o
CC crypto/ccm.o
CC net/ethtool/tunnels.o
CC kernel/time/clockevents.o
CC fs/exec.o
CC drivers/tty/serial/8250/8250_lpss.o
CC drivers/base/power/generic_ops.o
CC drivers/base/power/common.o
AR drivers/base/test/built-in.a
CC drivers/pci/iomap.o
CC drivers/acpi/acpica/exstorob.o
CC net/xfrm/xfrm_input.o
CC arch/x86/kernel/setup.o
CC io_uring/memmap.o
CC fs/nfs/fs_context.o
CC net/sunrpc/auth_gss/gss_mech_switch.o
AR drivers/misc/eeprom/built-in.a
AR drivers/misc/cb710/built-in.a
AR drivers/misc/ti-st/built-in.a
AR drivers/mfd/built-in.a
CC fs/pipe.o
AR drivers/misc/lis3lv02d/built-in.a
AR drivers/misc/cardreader/built-in.a
AR drivers/misc/keba/built-in.a
AR drivers/misc/built-in.a
CC net/sunrpc/xprtsock.o
CC block/blk-cgroup.o
CC net/netlabel/netlabel_user.o
CC kernel/trace/blktrace.o
CC drivers/pci/quirks.o
CC net/netfilter/nf_conntrack_standalone.o
CC kernel/sysctl.o
CC net/core/link_watch.o
CC drivers/acpi/acpica/exsystem.o
CC [M] sound/hda/hdac_sysfs.o
CC drivers/base/power/qos.o
CC kernel/time/tick-common.o
CC block/blk-ioprio.o
CC net/ethtool/fec.o
CC crypto/aes_generic.o
CC drivers/gpu/drm/virtio/virtgpu_object.o
CC drivers/gpu/drm/i915/i915_pci.o
AR drivers/base/firmware_loader/built-in.a
CC net/xfrm/xfrm_output.o
CC net/xfrm/xfrm_sysctl.o
CC drivers/tty/serial/8250/8250_mid.o
CC net/core/filter.o
CC drivers/acpi/acpica/extrace.o
CC drivers/tty/serial/serial_port.o
CC net/wireless/radiotap.o
AR drivers/block/built-in.a
CC drivers/tty/tty_ioctl.o
CC drivers/gpu/drm/i915/i915_scatterlist.o
CC block/blk-iolatency.o
CC io_uring/io-wq.o
CC net/ipv6/netfilter/ip6t_REJECT.o
CC net/ipv4/ip_options.o
CC net/ipv6/ip6_input.o
CC drivers/acpi/acpica/exutils.o
CC arch/x86/kernel/x86_init.o
CC net/sunrpc/auth_gss/svcauth_gss.o
CC drivers/gpu/drm/virtio/virtgpu_debugfs.o
CC net/mac80211/status.o
CC net/netlabel/netlabel_kapi.o
CC crypto/crc32c_generic.o
CC [M] sound/hda/hdac_regmap.o
CC net/sunrpc/sched.o
CC drivers/tty/serial/8250/8250_pci.o
CC drivers/acpi/acpica/hwacpi.o
CC net/sunrpc/auth.o
CC drivers/tty/serial/8250/8250_pericom.o
CC net/netfilter/nf_conntrack_expect.o
CC [M] sound/hda/hdac_controller.o
CC block/blk-iocost.o
CC net/ethtool/eeprom.o
CC drivers/gpu/drm/i915/i915_suspend.o
CC block/mq-deadline.o
CC kernel/time/tick-broadcast.o
CC fs/ext4/mballoc.o
CC kernel/capability.o
CC drivers/tty/serial/earlycon.o
CC net/netfilter/nf_conntrack_helper.o
CC crypto/authenc.o
CC drivers/base/power/runtime.o
CC mm/mmap.o
CC net/ipv6/addrconf.o
CC drivers/pci/pci-label.o
CC drivers/acpi/acpica/hwesleep.o
CC fs/nfs/nfsroot.o
CC drivers/gpu/drm/virtio/virtgpu_plane.o
CC arch/x86/kernel/i8259.o
CC io_uring/futex.o
CC net/mac80211/driver-ops.o
CC net/xfrm/xfrm_replay.o
CC kernel/trace/trace_events.o
AR net/ipv6/netfilter/built-in.a
CC net/sunrpc/auth_gss/gss_rpc_upcall.o
CC drivers/base/regmap/regcache.o
AR drivers/nfc/built-in.a
CC net/ipv6/addrlabel.o
CC net/core/sock_diag.o
AR drivers/dax/hmem/built-in.a
AR drivers/dax/built-in.a
CC kernel/ptrace.o
CC drivers/acpi/acpica/hwgpe.o
CC net/xfrm/xfrm_device.o
CC fs/nfs/sysctl.o
CC arch/x86/kernel/irqinit.o
CC net/wireless/util.o
CC drivers/pci/vgaarb.o
CC net/ipv4/ip_output.o
CC kernel/time/tick-broadcast-hrtimer.o
CC drivers/base/regmap/regcache-rbtree.o
CC net/sunrpc/auth_null.o
CC [M] sound/hda/hdac_stream.o
AR drivers/gpu/drm/bridge/analogix/built-in.a
AR drivers/gpu/drm/bridge/cadence/built-in.a
AR drivers/gpu/drm/bridge/imx/built-in.a
CC io_uring/napi.o
CC net/ipv6/route.o
AR drivers/gpu/drm/bridge/synopsys/built-in.a
CC net/ipv4/ip_sockglue.o
AR drivers/gpu/drm/bridge/built-in.a
CC drivers/acpi/device_pm.o
CC drivers/base/component.o
CC net/ethtool/stats.o
CC net/ethtool/phc_vclocks.o
CC net/netlabel/netlabel_domainhash.o
CC drivers/gpu/drm/virtio/virtgpu_ioctl.o
CC drivers/acpi/acpica/hwregs.o
CC kernel/time/tick-oneshot.o
CC crypto/authencesn.o
CC drivers/gpu/drm/i915/i915_switcheroo.o
AR drivers/tty/serial/8250/built-in.a
AR drivers/tty/serial/built-in.a
CC drivers/base/power/wakeirq.o
CC drivers/tty/tty_ldisc.o
CC kernel/user.o
CC lib/nmi_backtrace.o
CC [M] sound/hda/array.o
CC net/sunrpc/auth_tls.o
CC net/netfilter/nf_conntrack_proto.o
CC arch/x86/kernel/jump_label.o
CC net/rfkill/core.o
CC drivers/base/regmap/regcache-flat.o
CC drivers/acpi/acpica/hwsleep.o
CC net/xfrm/xfrm_nat_keepalive.o
CC kernel/time/tick-sched.o
CC fs/nfs/nfs3super.o
CC net/netlabel/netlabel_addrlist.o
CC drivers/dma-buf/dma-buf.o
CC net/core/dev_ioctl.o
CC net/mac80211/sta_info.o
CC net/sunrpc/auth_gss/gss_rpc_xdr.o
CC arch/x86/kernel/irq_work.o
CC crypto/lzo.o
CC net/sunrpc/auth_unix.o
CC drivers/base/power/main.o
AR drivers/gpu/drm/hisilicon/built-in.a
CC kernel/signal.o
CC net/netlabel/netlabel_mgmt.o
CC lib/objpool.o
AR drivers/pci/built-in.a
AR sound/x86/built-in.a
CC net/wireless/reg.o
CC drivers/acpi/acpica/hwvalid.o
CC drivers/gpu/drm/virtio/virtgpu_prime.o
CC mm/mmu_gather.o
CC drivers/gpu/drm/i915/i915_sysfs.o
CC fs/ext4/migrate.o
CC [M] sound/hda/hdmi_chmap.o
CC drivers/tty/tty_buffer.o
CC net/rfkill/input.o
CC drivers/base/regmap/regcache-maple.o
CC drivers/acpi/acpica/hwxface.o
CC net/ethtool/mm.o
CC kernel/trace/trace_export.o
AR drivers/cxl/core/built-in.a
CC drivers/macintosh/mac_hid.o
AR drivers/cxl/built-in.a
CC fs/ext4/mmp.o
CC lib/plist.o
AR io_uring/built-in.a
CC crypto/lzo-rle.o
CC crypto/rng.o
CC net/netlabel/netlabel_unlabeled.o
CC net/wireless/scan.o
CC lib/radix-tree.o
CC fs/namei.o
CC net/ipv4/inet_hashtables.o
CC drivers/acpi/acpica/hwxfsleep.o
CC net/mac80211/wep.o
CC block/kyber-iosched.o
CC drivers/gpu/drm/virtio/virtgpu_trace_points.o
AR net/rfkill/built-in.a
CC fs/nfs/nfs3client.o
CC block/blk-mq-pci.o
CC kernel/time/timer_migration.o
CC drivers/gpu/drm/virtio/virtgpu_submit.o
CC net/xfrm/xfrm_algo.o
CC drivers/base/regmap/regmap-debugfs.o
AR drivers/macintosh/built-in.a
CC lib/ratelimit.o
CC mm/mprotect.o
CC arch/x86/kernel/probe_roms.o
CC drivers/gpu/drm/i915/i915_utils.o
CC fs/ext4/move_extent.o
AR drivers/gpu/drm/mxsfb/built-in.a
CC drivers/dma-buf/dma-fence.o
CC drivers/dma-buf/dma-fence-array.o
CC drivers/dma-buf/dma-fence-chain.o
CC drivers/tty/tty_port.o
CC net/sunrpc/auth_gss/trace.o
CC net/netfilter/nf_conntrack_proto_generic.o
CC drivers/acpi/proc.o
CC drivers/acpi/acpica/hwpci.o
CC drivers/acpi/acpica/nsaccess.o
CC kernel/trace/trace_event_perf.o
CC [M] sound/hda/trace.o
CC drivers/tty/tty_mutex.o
CC drivers/base/core.o
CC drivers/tty/tty_ldsem.o
CC kernel/time/vsyscall.o
CC fs/fcntl.o
CC net/wireless/nl80211.o
CC crypto/drbg.o
CC net/ethtool/module.o
CC net/9p/mod.o
CC mm/mremap.o
CC drivers/acpi/acpica/nsalloc.o
CC net/sunrpc/svc.o
CC lib/rbtree.o
CC arch/x86/kernel/sys_ia32.o
CC drivers/base/power/wakeup.o
AR drivers/gpu/drm/tiny/built-in.a
CC crypto/jitterentropy.o
CC drivers/gpu/drm/i915/intel_clock_gating.o
CC block/blk-mq-virtio.o
CC net/sunrpc/svcsock.o
AR drivers/base/regmap/built-in.a
CC net/ipv6/ip6_fib.o
CC fs/ioctl.o
AR drivers/gpu/drm/virtio/built-in.a
CC drivers/tty/tty_baudrate.o
CC net/9p/client.o
CC net/ethtool/cmis_fw_update.o
CC fs/readdir.o
CC drivers/dma-buf/dma-fence-unwrap.o
CC fs/ext4/namei.o
CC lib/seq_buf.o
CC block/blk-mq-debugfs.o
CC drivers/acpi/acpica/nsarguments.o
CC net/netlabel/netlabel_cipso_v4.o
CC fs/nfs/nfs3proc.o
CC net/ethtool/cmis_cdb.o
CC net/ethtool/pse-pd.o
CC net/xfrm/xfrm_user.o
CC kernel/trace/trace_events_filter.o
AR sound/xen/built-in.a
AR drivers/gpu/drm/xlnx/built-in.a
CC [M] sound/hda/hdac_component.o
CC net/netfilter/nf_conntrack_proto_tcp.o
CC net/netfilter/nf_conntrack_proto_udp.o
CC net/ethtool/plca.o
CC net/netlabel/netlabel_calipso.o
CC crypto/jitterentropy-kcapi.o
CC block/blk-pm.o
CC net/sunrpc/auth_gss/gss_krb5_mech.o
CC fs/ext4/page-io.o
CC drivers/acpi/acpica/nsconvert.o
CC arch/x86/kernel/ksysfs.o
CC drivers/dma-buf/dma-resv.o
CC kernel/sys.o
CC drivers/tty/tty_jobctrl.o
CC drivers/dma-buf/sync_file.o
CC lib/siphash.o
CC net/ipv4/inet_timewait_sock.o
CC kernel/time/timekeeping_debug.o
CC crypto/ghash-generic.o
CC mm/msync.o
CC fs/select.o
CC drivers/acpi/acpica/nsdump.o
CC drivers/base/bus.o
CC [M] sound/hda/hdac_i915.o
CC net/mac80211/aead_api.o
CC drivers/gpu/drm/i915/intel_device_info.o
CC lib/string.o
CC mm/page_vma_mapped.o
CC drivers/base/power/wakeup_stats.o
CC block/holder.o
CC kernel/time/namespace.o
CC fs/nfs/nfs3xdr.o
CC arch/x86/kernel/bootflag.o
CC kernel/umh.o
CC lib/timerqueue.o
CC lib/union_find.o
CC crypto/hash_info.o
CC net/dns_resolver/dns_key.o
CC drivers/acpi/acpica/nseval.o
CC net/ethtool/phy.o
CC crypto/rsapubkey.asn1.o
CC net/ipv6/ipv6_sockglue.o
CC net/sunrpc/auth_gss/gss_krb5_seal.o
CC crypto/rsaprivkey.asn1.o
CC drivers/tty/n_null.o
AR crypto/built-in.a
CC net/core/tso.o
AR net/netlabel/built-in.a
CC fs/dcache.o
AR drivers/dma-buf/built-in.a
CC drivers/base/dd.o
CC net/core/sock_reuseport.o
CC drivers/base/syscore.o
CC lib/vsprintf.o
AR sound/virtio/built-in.a
CC net/core/fib_notifier.o
CC fs/inode.o
CC net/dns_resolver/dns_query.o
CC fs/ext4/readpage.o
CC drivers/base/power/trace.o
CC net/9p/error.o
CC [M] sound/hda/intel-dsp-config.o
CC [M] sound/hda/intel-nhlt.o
CC drivers/acpi/acpica/nsinit.o
CC kernel/trace/trace_events_trigger.o
CC drivers/tty/pty.o
CC kernel/workqueue.o
AR block/built-in.a
CC arch/x86/kernel/e820.o
CC net/sunrpc/svcauth.o
CC net/wireless/mlme.o
CC drivers/acpi/bus.o
CC mm/pagewalk.o
CC sound/sound_core.o
AR drivers/scsi/pcmcia/built-in.a
CC drivers/scsi/scsi.o
AR kernel/time/built-in.a
CC net/ipv4/inet_connection_sock.o
CC net/netfilter/nf_conntrack_proto_icmp.o
CC net/ipv6/ndisc.o
CC drivers/gpu/drm/i915/intel_memory_region.o
CC net/9p/protocol.o
CC [M] sound/hda/intel-sdw-acpi.o
CC drivers/acpi/acpica/nsload.o
CC sound/last.o
CC fs/nfs/nfs3acl.o
LD [M] sound/hda/snd-hda-core.o
CC fs/ext4/resize.o
CC net/ipv6/udp.o
AR net/dns_resolver/built-in.a
AR drivers/base/power/built-in.a
AR drivers/gpu/drm/gud/built-in.a
CC net/handshake/alert.o
CC net/devres.o
CC net/mac80211/wpa.o
CC net/core/xdp.o
CC mm/pgtable-generic.o
CC net/sunrpc/auth_gss/gss_krb5_unseal.o
CC fs/attr.o
CC net/handshake/genl.o
AR net/ethtool/built-in.a
CC fs/ext4/super.o
CC net/socket.o
CC drivers/acpi/acpica/nsnames.o
CC drivers/acpi/acpica/nsobject.o
CC net/ipv6/udplite.o
LD [M] sound/hda/snd-intel-dspcfg.o
CC kernel/trace/trace_eprobe.o
LD [M] sound/hda/snd-intel-sdw-acpi.o
CC net/wireless/ibss.o
CC drivers/base/driver.o
AR sound/built-in.a
CC drivers/acpi/glue.o
CC fs/bad_inode.o
AR net/xfrm/built-in.a
CC drivers/acpi/scan.o
CC drivers/tty/tty_audit.o
CC net/ipv4/tcp.o
CC net/mac80211/scan.o
CC net/9p/trans_common.o
CC net/sunrpc/svcauth_unix.o
CC net/netfilter/nf_conntrack_extend.o
CC arch/x86/kernel/pci-dma.o
CC net/wireless/sme.o
CC drivers/acpi/acpica/nsparse.o
CC drivers/base/class.o
CC fs/file.o
CC net/sysctl_net.o
CC mm/rmap.o
CC drivers/gpu/drm/i915/intel_pcode.o
CC mm/vmalloc.o
CC fs/ext4/symlink.o
CC net/mac80211/offchannel.o
CC net/mac80211/ht.o
CC net/mac80211/agg-tx.o
CC net/mac80211/agg-rx.o
CC net/wireless/chan.o
CC drivers/scsi/hosts.o
CC net/mac80211/vht.o
CC net/mac80211/he.o
CC drivers/acpi/acpica/nspredef.o
CC net/mac80211/s1g.o
CC net/9p/trans_fd.o
CC drivers/tty/sysrq.o
CC arch/x86/kernel/quirks.o
CC net/sunrpc/auth_gss/gss_krb5_wrap.o
CC net/mac80211/ibss.o
CC net/netfilter/nf_conntrack_acct.o
CC drivers/base/platform.o
CC fs/nfs/nfs4proc.o
CC net/netfilter/nf_conntrack_seqadj.o
CC net/handshake/netlink.o
CC drivers/acpi/acpica/nsprepkg.o
CC net/wireless/ethtool.o
CC net/core/flow_offload.o
CC drivers/scsi/scsi_ioctl.o
CC kernel/trace/trace_kprobe.o
CC net/9p/trans_virtio.o
CC net/netfilter/nf_conntrack_proto_icmpv6.o
CC mm/vma.o
CC mm/process_vm_access.o
CC kernel/pid.o
CC drivers/gpu/drm/i915/intel_region_ttm.o
AR drivers/nvme/common/built-in.a
AR drivers/nvme/host/built-in.a
AR drivers/nvme/target/built-in.a
AR drivers/gpu/drm/solomon/built-in.a
AR drivers/nvme/built-in.a
CC [M] drivers/gpu/drm/scheduler/sched_main.o
CC drivers/acpi/acpica/nsrepair.o
CC drivers/ata/libata-core.o
CC lib/win_minmax.o
CC drivers/base/cpu.o
CC arch/x86/kernel/kdebugfs.o
CC net/sunrpc/auth_gss/gss_krb5_crypto.o
AR drivers/tty/built-in.a
CC net/ipv6/raw.o
CC net/mac80211/iface.o
CC drivers/acpi/acpica/nsrepair2.o
CC lib/xarray.o
CC drivers/acpi/mipi-disco-img.o
CC drivers/gpu/drm/i915/intel_runtime_pm.o
CC fs/ext4/sysfs.o
CC drivers/scsi/scsicam.o
CC mm/page_alloc.o
HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob
CC kernel/trace/error_report-traces.o
CC drivers/ata/libata-scsi.o
GEN xe_wa_oob.c xe_wa_oob.h
CC arch/x86/kernel/alternative.o
CC [M] drivers/gpu/drm/xe/xe_bb.o
CC drivers/ata/libata-eh.o
CC net/handshake/request.o
CC drivers/base/firmware.o
CC net/sunrpc/auth_gss/gss_krb5_keys.o
CC net/core/gro.o
CC drivers/acpi/acpica/nssearch.o
CC net/ipv4/tcp_input.o
CC net/wireless/mesh.o
CC drivers/scsi/scsi_error.o
AR net/9p/built-in.a
CC fs/ext4/xattr.o
CC drivers/base/init.o
CC net/netfilter/nf_conntrack_netlink.o
CC lib/lockref.o
CC arch/x86/kernel/i8253.o
AR drivers/net/phy/qcom/built-in.a
CC drivers/net/phy/mdio-boardinfo.o
AR drivers/net/pse-pd/built-in.a
CC fs/nfs/nfs4xdr.o
CC net/ipv6/icmp.o
CC drivers/acpi/acpica/nsutils.o
CC drivers/firewire/init_ohci1394_dma.o
CC net/ipv4/tcp_output.o
CC net/core/netdev-genl.o
CC [M] drivers/gpu/drm/xe/xe_bo.o
CC [M] drivers/gpu/drm/scheduler/sched_fence.o
CC net/netfilter/nf_conntrack_ftp.o
CC drivers/gpu/drm/drm_atomic.o
CC drivers/ata/libata-transport.o
CC fs/filesystems.o
CC kernel/trace/power-traces.o
CC drivers/gpu/drm/i915/intel_sbi.o
CC drivers/acpi/resource.o
CC net/core/netdev-genl-gen.o
CC lib/bcd.o
CC drivers/base/map.o
CC arch/x86/kernel/hw_breakpoint.o
CC lib/sort.o
CC net/ipv4/tcp_timer.o
CC drivers/acpi/acpica/nswalk.o
CC net/netfilter/nf_conntrack_irc.o
CC lib/parser.o
CC fs/ext4/xattr_hurd.o
CC kernel/task_work.o
CC [M] drivers/gpu/drm/scheduler/sched_entity.o
AR net/sunrpc/auth_gss/built-in.a
CC net/sunrpc/addr.o
CC mm/init-mm.o
CC drivers/net/phy/stubs.o
AR drivers/firewire/built-in.a
CC net/core/gso.o
CC drivers/scsi/scsi_lib.o
CC net/handshake/tlshd.o
CC drivers/base/devres.o
CC drivers/gpu/drm/drm_atomic_uapi.o
CC drivers/acpi/acpica/nsxfeval.o
CC net/wireless/ap.o
CC lib/debug_locks.o
CC drivers/ata/libata-trace.o
CC net/handshake/trace.o
CC mm/memblock.o
CC drivers/net/phy/mdio_devres.o
CC drivers/gpu/drm/drm_auth.o
CC net/mac80211/link.o
CC drivers/scsi/constants.o
CC lib/random32.o
CC fs/ext4/xattr_trusted.o
CC fs/nfs/nfs4state.o
CC fs/nfs/nfs4renewd.o
CC drivers/net/mdio/acpi_mdio.o
CC drivers/gpu/drm/i915/intel_step.o
CC fs/nfs/nfs4super.o
CC arch/x86/kernel/tsc.o
LD [M] drivers/gpu/drm/scheduler/gpu-sched.o
CC net/mac80211/rate.o
CC drivers/net/mdio/fwnode_mdio.o
CC drivers/acpi/acpica/nsxfname.o
CC fs/ext4/xattr_user.o
CC net/netfilter/nf_conntrack_sip.o
CC drivers/base/attribute_container.o
CC lib/bust_spinlocks.o
CC [M] drivers/gpu/drm/xe/xe_bo_evict.o
CC net/ipv6/mcast.o
CC net/wireless/trace.o
CC drivers/acpi/acpica/nsxfobj.o
CC net/sunrpc/rpcb_clnt.o
CC drivers/acpi/acpi_processor.o
CC drivers/scsi/scsi_lib_dma.o
CC fs/ext4/fast_commit.o
CC net/core/net-sysfs.o
CC fs/nfs/nfs4file.o
CC drivers/net/phy/phy.o
CC net/mac80211/michael.o
CC fs/namespace.o
CC net/netfilter/nf_nat_core.o
CC arch/x86/kernel/tsc_msr.o
CC drivers/ata/libata-sata.o
CC drivers/acpi/acpica/psargs.o
CC drivers/cdrom/cdrom.o
CC kernel/trace/rpm-traces.o
CC drivers/base/transport_class.o
AR drivers/auxdisplay/built-in.a
CC fs/nfs/delegation.o
CC net/ipv4/tcp_ipv4.o
CC fs/seq_file.o
CC lib/kasprintf.o
CC kernel/extable.o
AR drivers/net/pcs/built-in.a
CC drivers/scsi/scsi_scan.o
AR drivers/net/mdio/built-in.a
CC fs/nfs/nfs4idmap.o
CC drivers/gpu/drm/i915/intel_uncore.o
CC net/netfilter/nf_nat_proto.o
CC drivers/net/phy/phy-c45.o
CC [M] drivers/gpu/drm/xe/xe_devcoredump.o
CC net/sunrpc/timer.o
CC drivers/pcmcia/cs.o
CC drivers/pcmcia/socket_sysfs.o
CC arch/x86/kernel/io_delay.o
CC drivers/acpi/processor_core.o
CC mm/slub.o
CC fs/ext4/orphan.o
CC drivers/acpi/acpica/psloop.o
AR net/handshake/built-in.a
CC lib/bitmap.o
CC kernel/params.o
CC drivers/base/topology.o
CC net/wireless/ocb.o
CC mm/madvise.o
CC net/ipv6/reassembly.o
CC arch/x86/kernel/rtc.o
CC kernel/trace/trace_dynevent.o
CC net/netfilter/nf_nat_helper.o
CC drivers/acpi/acpica/psobject.o
CC drivers/acpi/processor_pdc.o
CC net/sunrpc/xdr.o
CC fs/xattr.o
CC drivers/ata/libata-sff.o
CC [M] drivers/gpu/drm/xe/xe_device.o
CC net/wireless/pmsr.o
CC drivers/base/container.o
CC net/mac80211/tkip.o
CC drivers/pcmcia/cardbus.o
CC net/ipv4/tcp_minisocks.o
CC net/ipv4/tcp_cong.o
CC lib/scatterlist.o
CC arch/x86/kernel/resource.o
CC drivers/acpi/acpica/psopcode.o
CC fs/ext4/acl.o
CC kernel/trace/trace_probe.o
GEN drivers/scsi/scsi_devinfo_tbl.c
CC drivers/scsi/scsi_devinfo.o
CC net/core/hotdata.o
CC net/ipv6/tcp_ipv6.o
CC drivers/net/phy/phy-core.o
CC drivers/gpu/drm/i915/intel_wakeref.o
AS arch/x86/kernel/irqflags.o
CC arch/x86/kernel/static_call.o
CC drivers/base/property.o
CC drivers/gpu/drm/drm_blend.o
CC drivers/net/phy/phy_device.o
CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o
CC drivers/usb/common/common.o
CC drivers/acpi/acpica/psopinfo.o
CC net/netfilter/nf_nat_masquerade.o
CC fs/nfs/callback.o
CC drivers/usb/core/usb.o
CC arch/x86/kernel/process.o
AR drivers/cdrom/built-in.a
CC fs/ext4/xattr_security.o
CC drivers/ata/libata-pmp.o
CC drivers/pcmcia/ds.o
AR drivers/usb/phy/built-in.a
CC drivers/gpu/drm/drm_bridge.o
CC lib/list_sort.o
CC drivers/usb/common/debug.o
CC drivers/gpu/drm/i915/vlv_sideband.o
CC kernel/kthread.o
CC drivers/net/phy/linkmode.o
CC drivers/acpi/acpica/psparse.o
CC [M] drivers/gpu/drm/xe/xe_dma_buf.o
CC drivers/usb/core/hub.o
CC net/mac80211/aes_cmac.o
CC drivers/acpi/ec.o
CC drivers/gpu/drm/drm_cache.o
CC net/core/netdev_rx_queue.o
CC drivers/scsi/scsi_sysctl.o
CC mm/page_io.o
CC drivers/pcmcia/pcmcia_resource.o
CC drivers/usb/core/hcd.o
CC drivers/net/phy/phy_link_topology.o
CC drivers/gpu/drm/drm_color_mgmt.o
CC mm/swap_state.o
AR drivers/usb/common/built-in.a
CC drivers/gpu/drm/i915/vlv_suspend.o
CC drivers/base/cacheinfo.o
CC lib/uuid.o
CC drivers/pcmcia/cistpl.o
CC drivers/acpi/acpica/psscope.o
CC drivers/acpi/dock.o
CC lib/iov_iter.o
CC net/mac80211/aes_gmac.o
CC net/ipv6/ping.o
GEN net/wireless/shipped-certs.c
CC drivers/ata/libata-acpi.o
AR drivers/net/ethernet/3com/built-in.a
CC drivers/net/ethernet/8390/ne2k-pci.o
CC fs/nfs/callback_xdr.o
CC fs/nfs/callback_proc.o
AR drivers/net/ethernet/adaptec/built-in.a
CC drivers/input/serio/serio.o
CC drivers/input/serio/i8042.o
CC net/mac80211/fils_aead.o
CC drivers/scsi/scsi_proc.o
CC drivers/acpi/acpica/pstree.o
AR drivers/net/wireless/admtek/built-in.a
CC kernel/trace/trace_uprobe.o
AR drivers/net/wireless/ath/built-in.a
AR drivers/net/wireless/atmel/built-in.a
CC [M] drivers/gpu/drm/xe/xe_drm_client.o
CC drivers/net/ethernet/8390/8390.o
AR drivers/net/wireless/broadcom/built-in.a
AR drivers/net/wireless/intel/built-in.a
CC net/mac80211/cfg.o
AR drivers/net/wireless/intersil/built-in.a
CC drivers/usb/core/urb.o
CC net/netfilter/nf_nat_ftp.o
AR drivers/net/wireless/marvell/built-in.a
AR drivers/net/wireless/mediatek/built-in.a
AR drivers/net/wireless/microchip/built-in.a
AR drivers/net/wireless/purelifi/built-in.a
CC fs/nfs/nfs4namespace.o
AR drivers/net/wireless/quantenna/built-in.a
AR drivers/net/wireless/ralink/built-in.a
AR drivers/net/wireless/realtek/built-in.a
AR drivers/net/wireless/rsi/built-in.a
CC net/mac80211/ethtool.o
CC net/ipv4/tcp_metrics.o
AR drivers/net/wireless/silabs/built-in.a
AR drivers/net/wireless/st/built-in.a
AR drivers/net/wireless/ti/built-in.a
CC drivers/net/phy/mdio_bus.o
AR drivers/net/wireless/zydas/built-in.a
CC net/core/net-procfs.o
AR drivers/net/wireless/virtual/built-in.a
AR drivers/net/wireless/built-in.a
CC net/netfilter/nf_nat_irc.o
CC net/wireless/shipped-certs.o
CC mm/swapfile.o
CC drivers/base/swnode.o
CC kernel/trace/rethook.o
CC drivers/acpi/acpica/psutils.o
CC drivers/scsi/scsi_debugfs.o
CC net/ipv6/exthdrs.o
CC arch/x86/kernel/ptrace.o
CC drivers/input/serio/serport.o
AR fs/ext4/built-in.a
CC [M] drivers/gpu/drm/xe/xe_exec.o
CC drivers/gpu/drm/i915/soc/intel_dram.o
AR drivers/net/usb/built-in.a
CC drivers/gpu/drm/drm_connector.o
CC drivers/ata/libata-pata-timings.o
CC arch/x86/kernel/tls.o
CC net/mac80211/rx.o
CC [M] drivers/gpu/drm/xe/xe_execlist.o
CC drivers/acpi/acpica/pswalk.o
CC drivers/base/auxiliary.o
CC fs/libfs.o
CC drivers/acpi/acpica/psxface.o
CC net/ipv4/tcp_fastopen.o
CC fs/nfs/nfs4getroot.o
CC drivers/net/mii.o
CC [M] drivers/gpu/drm/xe/xe_exec_queue.o
CC drivers/pcmcia/pcmcia_cis.o
AR drivers/net/ethernet/agere/built-in.a
CC net/core/netpoll.o
CC drivers/scsi/scsi_trace.o
CC fs/fs-writeback.o
CC drivers/acpi/acpica/rsaddr.o
CC drivers/net/phy/mdio_device.o
CC drivers/usb/mon/mon_main.o
CC drivers/input/keyboard/atkbd.o
AR drivers/net/ethernet/8390/built-in.a
AR drivers/net/ethernet/alacritech/built-in.a
CC mm/swap_slots.o
CC drivers/gpu/drm/i915/soc/intel_gmch.o
CC drivers/input/mouse/psmouse-base.o
AR drivers/net/ethernet/alteon/built-in.a
AR drivers/net/ethernet/amazon/built-in.a
AR drivers/net/ethernet/amd/built-in.a
AR drivers/net/ethernet/aquantia/built-in.a
AR drivers/net/ethernet/arc/built-in.a
CC drivers/acpi/pci_root.o
AR drivers/net/ethernet/asix/built-in.a
CC net/ipv4/tcp_rate.o
AR drivers/net/ethernet/atheros/built-in.a
CC net/sunrpc/sunrpc_syms.o
AR drivers/net/ethernet/cadence/built-in.a
CC drivers/input/serio/libps2.o
CC net/ipv4/tcp_recovery.o
CC drivers/net/ethernet/broadcom/bnx2.o
CC drivers/base/devtmpfs.o
CC kernel/sys_ni.o
CC net/netfilter/nf_nat_sip.o
CC net/ipv4/tcp_ulp.o
CC kernel/nsproxy.o
CC drivers/ata/ahci.o
CC drivers/acpi/acpica/rscalc.o
CC drivers/usb/mon/mon_stat.o
CC drivers/usb/core/message.o
CC arch/x86/kernel/step.o
CC fs/pnode.o
CC drivers/input/mouse/synaptics.o
CC drivers/gpu/drm/i915/soc/intel_pch.o
CC drivers/net/ethernet/broadcom/tg3.o
AR drivers/input/joystick/built-in.a
CC drivers/pcmcia/rsrc_mgr.o
AR drivers/net/ethernet/brocade/built-in.a
CC mm/dmapool.o
CC drivers/base/module.o
CC drivers/scsi/scsi_logging.o
CC drivers/scsi/scsi_pm.o
AR kernel/trace/built-in.a
CC drivers/gpu/drm/drm_crtc.o
CC lib/clz_ctz.o
CC drivers/acpi/acpica/rscreate.o
CC lib/bsearch.o
CC drivers/base/auxiliary_sysfs.o
CC fs/nfs/nfs4client.o
CC drivers/acpi/acpica/rsdumpinfo.o
CC fs/nfs/nfs4session.o
CC drivers/net/phy/swphy.o
AR drivers/input/serio/built-in.a
CC drivers/scsi/scsi_bsg.o
AR drivers/net/ethernet/cavium/common/built-in.a
CC drivers/usb/mon/mon_text.o
AR drivers/net/ethernet/cavium/thunder/built-in.a
CC net/ipv6/datagram.o
CC net/ipv4/tcp_offload.o
AR drivers/net/ethernet/cavium/liquidio/built-in.a
AR drivers/net/ethernet/cavium/octeon/built-in.a
AR drivers/net/ethernet/cavium/built-in.a
CC net/mac80211/spectmgmt.o
CC drivers/input/mouse/focaltech.o
CC drivers/gpu/drm/i915/soc/intel_rom.o
CC drivers/acpi/pci_link.o
AR drivers/input/keyboard/built-in.a
CC drivers/base/devcoredump.o
CC drivers/net/loopback.o
CC drivers/net/netconsole.o
CC arch/x86/kernel/i8237.o
CC drivers/acpi/acpica/rsinfo.o
CC [M] drivers/gpu/drm/xe/xe_force_wake.o
CC net/sunrpc/cache.o
CC drivers/base/platform-msi.o
CC drivers/usb/mon/mon_bin.o
CC drivers/usb/host/pci-quirks.o
CC drivers/pcmcia/rsrc_nonstatic.o
CC net/core/fib_rules.o
CC lib/find_bit.o
CC kernel/notifier.o
CC drivers/usb/core/driver.o
CC drivers/acpi/acpica/rsio.o
CC drivers/scsi/scsi_common.o
AR drivers/input/tablet/built-in.a
CC arch/x86/kernel/stacktrace.o
CC drivers/gpu/drm/i915/i915_memcpy.o
CC drivers/input/mouse/alps.o
CC mm/hugetlb.o
CC [M] drivers/gpu/drm/xe/xe_ggtt.o
CC drivers/rtc/lib.o
CC drivers/usb/core/config.o
CC drivers/net/virtio_net.o
CC drivers/usb/class/usblp.o
CC drivers/ata/libahci.o
CC lib/llist.o
CC drivers/acpi/acpica/rsirq.o
CC net/netfilter/x_tables.o
CC arch/x86/kernel/reboot.o
CC net/ipv4/tcp_plb.o
CC drivers/usb/host/ehci-hcd.o
CC drivers/pcmcia/yenta_socket.o
CC lib/lwq.o
CC lib/memweight.o
CC drivers/base/physical_location.o
CC drivers/net/phy/fixed_phy.o
CC fs/nfs/dns_resolve.o
CC net/core/net-traces.o
CC net/mac80211/tx.o
CC net/netfilter/xt_tcpudp.o
CC fs/nfs/nfs4trace.o
CC drivers/scsi/scsi_transport_spi.o
CC drivers/net/net_failover.o
CC lib/kfifo.o
CC drivers/acpi/acpica/rslist.o
CC fs/splice.o
CC drivers/input/mouse/byd.o
CC drivers/usb/storage/scsiglue.o
AR drivers/usb/misc/built-in.a
CC drivers/acpi/acpica/rsmemory.o
CC drivers/gpu/drm/i915/i915_mm.o
CC drivers/rtc/class.o
CC drivers/usb/storage/protocol.o
AR drivers/net/ethernet/chelsio/built-in.a
CC net/netfilter/xt_CONNSECMARK.o
CC drivers/usb/early/ehci-dbgp.o
CC drivers/base/trace.o
CC drivers/acpi/acpica/rsmisc.o
CC net/netfilter/xt_NFLOG.o
CC fs/sync.o
CC kernel/ksysfs.o
CC net/core/selftests.o
AR drivers/usb/mon/built-in.a
CC arch/x86/kernel/msr.o
CC net/sunrpc/rpc_pipe.o
CC drivers/acpi/pci_irq.o
CC drivers/usb/host/ehci-pci.o
CC [M] drivers/gpu/drm/xe/xe_gpu_scheduler.o
AR drivers/usb/class/built-in.a
CC drivers/usb/storage/transport.o
CC net/ipv6/ip6_flowlabel.o
CC drivers/usb/core/file.o
CC net/core/ptp_classifier.o
CC drivers/acpi/acpica/rsserial.o
CC drivers/gpu/drm/i915/i915_sw_fence.o
CC lib/percpu-refcount.o
AR drivers/input/touchscreen/built-in.a
CC drivers/net/phy/realtek.o
CC arch/x86/kernel/cpuid.o
CC drivers/gpu/drm/drm_displayid.o
CC drivers/rtc/interface.o
CC net/ipv4/datagram.o
CC [M] drivers/gpu/drm/xe/xe_gsc.o
CC lib/rhashtable.o
AR drivers/net/ethernet/cisco/built-in.a
CC drivers/scsi/virtio_scsi.o
CC kernel/cred.o
CC mm/mmu_notifier.o
AR drivers/base/built-in.a
AR drivers/pcmcia/built-in.a
CC drivers/acpi/acpica/rsutils.o
AR drivers/input/misc/built-in.a
CC lib/base64.o
CC drivers/acpi/acpi_apd.o
CC drivers/input/input.o
CC drivers/input/mouse/logips2pp.o
AR drivers/net/ethernet/cortina/built-in.a
CC fs/utimes.o
CC fs/nfs/nfs4sysctl.o
AR drivers/usb/early/built-in.a
CC drivers/acpi/acpica/rsxface.o
CC net/sunrpc/sysfs.o
AR drivers/net/ethernet/dec/tulip/built-in.a
CC drivers/usb/host/ohci-hcd.o
AR drivers/net/ethernet/dec/built-in.a
CC drivers/usb/core/buffer.o
CC drivers/i2c/algos/i2c-algo-bit.o
CC drivers/i2c/busses/i2c-i801.o
CC net/ipv4/raw.o
AR drivers/i3c/built-in.a
CC net/mac80211/key.o
CC net/sunrpc/svc_xprt.o
CC mm/migrate.o
CC drivers/ata/ata_piix.o
CC net/ipv4/udp.o
CC drivers/gpu/drm/i915/i915_sw_fence_work.o
CC arch/x86/kernel/early-quirks.o
CC net/netfilter/xt_SECMARK.o
CC drivers/input/mouse/lifebook.o
CC drivers/usb/core/sysfs.o
CC drivers/usb/storage/usb.o
CC net/ipv6/inet6_connection_sock.o
CC drivers/acpi/acpica/tbdata.o
CC kernel/reboot.o
CC drivers/rtc/nvmem.o
CC drivers/gpu/drm/drm_drv.o
CC drivers/gpu/drm/i915/i915_syncmap.o
CC net/mac80211/util.o
CC drivers/input/input-compat.o
CC arch/x86/kernel/smp.o
CC net/ipv4/udplite.o
CC [M] drivers/gpu/drm/xe/xe_gsc_debugfs.o
AR drivers/media/i2c/built-in.a
CC drivers/ata/pata_amd.o
AR drivers/net/phy/built-in.a
CC drivers/scsi/sd.o
CC drivers/rtc/dev.o
CC fs/d_path.o
AR drivers/media/tuners/built-in.a
CC net/core/netprio_cgroup.o
AR drivers/media/rc/keymaps/built-in.a
AR drivers/media/rc/built-in.a
CC lib/once.o
AR drivers/media/common/b2c2/built-in.a
AR drivers/media/common/saa7146/built-in.a
CC drivers/gpu/drm/i915/i915_user_extensions.o
AR drivers/media/common/siano/built-in.a
AR drivers/media/common/v4l2-tpg/built-in.a
AR drivers/media/common/videobuf2/built-in.a
AR drivers/media/common/built-in.a
AR drivers/media/platform/allegro-dvt/built-in.a
CC drivers/input/mouse/trackpoint.o
AR drivers/i2c/algos/built-in.a
CC lib/refcount.o
CC drivers/acpi/acpica/tbfadt.o
AR drivers/media/platform/amlogic/meson-ge2d/built-in.a
AR drivers/media/platform/amlogic/built-in.a
AR drivers/media/platform/amphion/built-in.a
CC mm/page_counter.o
AR drivers/media/platform/aspeed/built-in.a
AR drivers/media/platform/atmel/built-in.a
AR drivers/media/platform/broadcom/built-in.a
CC mm/hugetlb_cgroup.o
AR drivers/media/platform/cadence/built-in.a
AR drivers/pps/clients/built-in.a
AR drivers/pps/generators/built-in.a
AR drivers/media/platform/chips-media/coda/built-in.a
CC drivers/pps/pps.o
AR drivers/media/platform/chips-media/wave5/built-in.a
AR drivers/media/platform/chips-media/built-in.a
AR drivers/media/platform/imagination/built-in.a
CC drivers/ptp/ptp_clock.o
AR drivers/media/platform/intel/built-in.a
CC kernel/async.o
AR drivers/media/platform/marvell/built-in.a
CC drivers/input/mouse/cypress_ps2.o
CC kernel/range.o
CC drivers/power/supply/power_supply_core.o
AR drivers/media/platform/mediatek/jpeg/built-in.a
AR drivers/media/platform/microchip/built-in.a
AR drivers/media/platform/mediatek/mdp/built-in.a
CC net/netfilter/xt_TCPMSS.o
CC drivers/ata/pata_oldpiix.o
AR drivers/media/platform/mediatek/vcodec/common/built-in.a
CC drivers/gpu/drm/drm_dumb_buffers.o
AR drivers/media/platform/mediatek/vcodec/encoder/built-in.a
CC lib/rcuref.o
AR drivers/media/platform/mediatek/vcodec/decoder/built-in.a
AR drivers/i2c/busses/built-in.a
AR drivers/media/platform/mediatek/vcodec/built-in.a
AR drivers/i2c/muxes/built-in.a
CC drivers/i2c/i2c-boardinfo.o
AR drivers/media/platform/mediatek/vpu/built-in.a
AR drivers/media/platform/mediatek/mdp3/built-in.a
AR drivers/media/platform/mediatek/built-in.a
CC drivers/gpu/drm/i915/i915_debugfs.o
AR drivers/media/platform/nuvoton/built-in.a
CC drivers/acpi/acpica/tbfind.o
CC drivers/usb/core/endpoint.o
AR drivers/media/platform/nvidia/tegra-vde/built-in.a
AR drivers/media/platform/nvidia/built-in.a
CC drivers/usb/storage/initializers.o
CC drivers/pps/kapi.o
AR drivers/media/platform/nxp/dw100/built-in.a
AR drivers/media/platform/nxp/imx-jpeg/built-in.a
AR drivers/media/platform/nxp/imx8-isi/built-in.a
AR drivers/media/platform/nxp/built-in.a
AR drivers/media/platform/qcom/camss/built-in.a
AR drivers/media/platform/qcom/venus/built-in.a
AR drivers/media/platform/qcom/built-in.a
CC lib/usercopy.o
CC kernel/smpboot.o
AR drivers/media/platform/raspberrypi/pisp_be/built-in.a
AR drivers/media/platform/raspberrypi/built-in.a
CC drivers/gpu/drm/drm_edid.o
CC drivers/rtc/proc.o
AR drivers/media/platform/renesas/rcar-vin/built-in.a
CC drivers/scsi/sr.o
CC drivers/rtc/sysfs.o
AR drivers/media/platform/renesas/rzg2l-cru/built-in.a
CC arch/x86/kernel/smpboot.o
AR drivers/media/platform/renesas/vsp1/built-in.a
AR drivers/media/platform/renesas/built-in.a
CC net/ipv6/udp_offload.o
CC drivers/pps/sysfs.o
CC drivers/hwmon/hwmon.o
AR drivers/media/platform/rockchip/rga/built-in.a
AR drivers/media/platform/rockchip/rkisp1/built-in.a
AR drivers/media/platform/rockchip/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gsc_proxy.o
AR drivers/media/platform/samsung/exynos-gsc/built-in.a
AR drivers/media/platform/samsung/exynos4-is/built-in.a
AR drivers/media/platform/samsung/s3c-camif/built-in.a
AR drivers/thermal/broadcom/built-in.a
AR drivers/thermal/renesas/built-in.a
AR drivers/media/platform/samsung/s5p-g2d/built-in.a
AR drivers/thermal/samsung/built-in.a
AR drivers/media/platform/samsung/s5p-jpeg/built-in.a
CC net/netfilter/xt_conntrack.o
AR drivers/watchdog/built-in.a
AR drivers/media/platform/samsung/s5p-mfc/built-in.a
CC drivers/thermal/intel/intel_tcc.o
CC drivers/ptp/ptp_chardev.o
AR drivers/media/platform/samsung/built-in.a
AR drivers/media/pci/ttpci/built-in.a
CC drivers/acpi/acpica/tbinstal.o
AR drivers/media/pci/b2c2/built-in.a
AR drivers/media/platform/st/sti/bdisp/built-in.a
AR drivers/media/pci/pluto2/built-in.a
AR drivers/media/platform/st/sti/c8sectpfe/built-in.a
AR drivers/media/pci/dm1105/built-in.a
AR drivers/media/platform/st/sti/delta/built-in.a
AR drivers/media/pci/pt1/built-in.a
AR drivers/media/platform/sunxi/sun4i-csi/built-in.a
CC drivers/scsi/sr_ioctl.o
AR drivers/media/platform/st/sti/hva/built-in.a
AR drivers/media/pci/pt3/built-in.a
AR drivers/media/platform/ti/am437x/built-in.a
AR drivers/media/platform/sunxi/sun6i-csi/built-in.a
AR drivers/media/platform/st/stm32/built-in.a
AR drivers/media/pci/mantis/built-in.a
AR drivers/media/platform/st/built-in.a
AR drivers/media/platform/ti/cal/built-in.a
AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a
CC net/netfilter/xt_policy.o
AR drivers/media/pci/ngene/built-in.a
AR drivers/media/platform/ti/vpe/built-in.a
CC lib/errseq.o
AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a
AR drivers/media/platform/sunxi/sun8i-di/built-in.a
AR drivers/media/pci/ddbridge/built-in.a
AR drivers/media/platform/ti/davinci/built-in.a
AR drivers/media/pci/saa7146/built-in.a
CC net/ipv6/seg6.o
AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a
AR drivers/media/platform/ti/j721e-csi2rx/built-in.a
CC drivers/ptp/ptp_sysfs.o
AR drivers/media/pci/smipcie/built-in.a
AR drivers/media/platform/sunxi/built-in.a
AR drivers/media/platform/ti/omap/built-in.a
AR drivers/media/pci/netup_unidvb/built-in.a
CC net/netfilter/xt_state.o
AR drivers/media/platform/ti/omap3isp/built-in.a
AR drivers/media/platform/ti/built-in.a
AR drivers/media/pci/intel/ipu3/built-in.a
AR drivers/media/pci/intel/ivsc/built-in.a
AR drivers/media/platform/verisilicon/built-in.a
AR drivers/media/pci/intel/built-in.a
AR drivers/media/pci/built-in.a
AR drivers/media/platform/via/built-in.a
AR drivers/media/platform/xilinx/built-in.a
AR drivers/media/platform/built-in.a
CC net/mac80211/parse.o
CC [M] drivers/gpu/drm/xe/xe_gsc_submit.o
CC lib/bucket_locks.o
CC drivers/input/mouse/psmouse-smbus.o
AR drivers/media/usb/b2c2/built-in.a
CC drivers/thermal/intel/therm_throt.o
AR drivers/media/usb/dvb-usb/built-in.a
AR drivers/pps/built-in.a
CC net/sunrpc/xprtmultipath.o
AR drivers/media/usb/dvb-usb-v2/built-in.a
CC net/ipv4/udp_offload.o
CC drivers/usb/host/ohci-pci.o
AR drivers/media/usb/s2255/built-in.a
AR drivers/media/usb/siano/built-in.a
CC net/ipv6/fib6_notifier.o
AR drivers/media/usb/ttusb-budget/built-in.a
CC drivers/usb/storage/sierra_ms.o
AR drivers/media/usb/ttusb-dec/built-in.a
CC drivers/usb/core/devio.o
AR drivers/media/usb/built-in.a
CC drivers/power/supply/power_supply_sysfs.o
CC [M] drivers/gpu/drm/xe/xe_gt.o
AR drivers/media/mmc/siano/built-in.a
CC kernel/ucount.o
AR drivers/media/mmc/built-in.a
CC kernel/regset.o
CC drivers/i2c/i2c-core-base.o
CC drivers/ata/pata_sch.o
AR drivers/media/firewire/built-in.a
CC mm/early_ioremap.o
AR drivers/media/spi/built-in.a
AR drivers/media/test-drivers/built-in.a
CC drivers/acpi/acpica/tbprint.o
AR drivers/media/built-in.a
CC drivers/usb/storage/option_ms.o
AR fs/nfs/built-in.a
CC fs/stack.o
CC drivers/rtc/rtc-mc146818-lib.o
CC mm/secretmem.o
CC net/sunrpc/stats.o
AR drivers/net/ethernet/dlink/built-in.a
CC net/ipv4/arp.o
CC lib/generic-radix-tree.o
CC drivers/acpi/acpica/tbutils.o
CC drivers/usb/storage/usual-tables.o
CC drivers/gpu/drm/i915/i915_debugfs_params.o
CC drivers/power/supply/power_supply_leds.o
CC kernel/ksyms_common.o
CC net/ipv6/rpl.o
CC drivers/usb/core/notify.o
CC drivers/rtc/rtc-cmos.o
CC fs/fs_struct.o
AR drivers/net/ethernet/emulex/built-in.a
CC drivers/usb/host/uhci-hcd.o
CC mm/hmm.o
CC arch/x86/kernel/tsc_sync.o
CC drivers/ptp/ptp_vclock.o
CC net/sunrpc/sysctl.o
AR drivers/input/mouse/built-in.a
CC drivers/input/input-mt.o
CC drivers/acpi/acpica/tbxface.o
CC lib/bitmap-str.o
CC [M] net/netfilter/nf_log_syslog.o
CC kernel/groups.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o
CC drivers/ata/pata_mpiix.o
CC drivers/md/md.o
AR drivers/hwmon/built-in.a
CC drivers/acpi/acpica/tbxfload.o
CC drivers/md/md-bitmap.o
CC drivers/md/md-autodetect.o
CC drivers/md/dm.o
CC drivers/md/dm-table.o
CC drivers/acpi/acpi_platform.o
CC drivers/md/dm-target.o
CC drivers/power/supply/power_supply_hwmon.o
CC lib/string_helpers.o
CC drivers/acpi/acpica/tbxfroot.o
CC net/core/netclassid_cgroup.o
AR drivers/usb/storage/built-in.a
AR net/wireless/built-in.a
CC kernel/kcmp.o
CC drivers/cpufreq/cpufreq.o
CC drivers/acpi/acpi_pnp.o
CC drivers/acpi/acpica/utaddress.o
CC [M] drivers/gpu/drm/xe/xe_gt_ccs_mode.o
CC [M] drivers/gpu/drm/xe/xe_gt_clock.o
CC drivers/scsi/sr_vendor.o
CC drivers/cpufreq/freq_table.o
CC drivers/ata/ata_generic.o
CC [M] net/netfilter/xt_mark.o
CC fs/statfs.o
CC net/ipv6/ioam6.o
CC arch/x86/kernel/setup_percpu.o
AR drivers/thermal/st/built-in.a
CC drivers/ptp/ptp_kvm_x86.o
CC drivers/gpu/drm/drm_eld.o
CC drivers/md/dm-linear.o
CC drivers/scsi/sg.o
CC drivers/md/dm-stripe.o
AR drivers/power/supply/built-in.a
CC drivers/gpu/drm/i915/i915_pmu.o
AR drivers/power/built-in.a
CC drivers/input/input-poller.o
CC net/ipv6/sysctl_net_ipv6.o
CC drivers/i2c/i2c-core-smbus.o
CC drivers/acpi/acpica/utalloc.o
CC mm/memfd.o
AR drivers/thermal/intel/built-in.a
AR drivers/thermal/qcom/built-in.a
AR drivers/thermal/tegra/built-in.a
AR drivers/thermal/mediatek/built-in.a
CC drivers/thermal/thermal_core.o
CC drivers/cpufreq/cpufreq_performance.o
AR drivers/rtc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_freq.o
CC fs/fs_pin.o
CC lib/hexdump.o
CC drivers/gpu/drm/i915/gt/gen2_engine_cs.o
CC drivers/thermal/thermal_sysfs.o
CC drivers/usb/host/xhci.o
CC drivers/acpi/acpica/utascii.o
CC drivers/acpi/acpica/utbuffer.o
CC lib/kstrtox.o
CC kernel/freezer.o
CC drivers/usb/core/generic.o
CC drivers/cpuidle/cpuidle.o
CC drivers/cpuidle/governors/menu.o
CC drivers/acpi/acpica/utcksum.o
CC arch/x86/kernel/mpparse.o
CC drivers/cpuidle/driver.o
CC mm/ptdump.o
CC net/core/dst_cache.o
CC drivers/cpufreq/cpufreq_userspace.o
CC kernel/profile.o
AR drivers/ata/built-in.a
AR drivers/net/ethernet/engleder/built-in.a
CC drivers/gpu/drm/drm_encoder.o
CC drivers/ptp/ptp_kvm_common.o
CC drivers/i2c/i2c-core-acpi.o
CC drivers/cpuidle/governor.o
CC drivers/i2c/i2c-smbus.o
AR drivers/mmc/built-in.a
CC [M] net/netfilter/xt_nat.o
CC drivers/input/ff-core.o
CC [M] drivers/gpu/drm/xe/xe_gt_idle.o
CC fs/nsfs.o
CC net/ipv4/icmp.o
CC net/mac80211/wme.o
CC drivers/thermal/thermal_trip.o
CC drivers/thermal/thermal_helpers.o
CC drivers/acpi/acpica/utcopy.o
CC drivers/gpu/drm/i915/gt/gen6_engine_cs.o
CC lib/iomap.o
CC net/ipv6/xfrm6_policy.o
CC arch/x86/kernel/trace_clock.o
AR drivers/ufs/built-in.a
AR drivers/net/ethernet/ezchip/built-in.a
CC drivers/gpu/drm/drm_file.o
CC drivers/input/touchscreen.o
CC drivers/cpuidle/governors/haltpoll.o
CC [M] net/netfilter/xt_LOG.o
CC fs/fs_types.o
CC drivers/acpi/acpica/utexcep.o
CC net/ipv6/xfrm6_state.o
CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o
CC drivers/usb/core/quirks.o
CC mm/execmem.o
CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o
CC net/core/gro_cells.o
CC drivers/acpi/power.o
CC drivers/gpu/drm/i915/gt/gen6_ppgtt.o
CC fs/fs_context.o
CC kernel/stacktrace.o
CC net/ipv4/devinet.o
CC drivers/md/dm-ioctl.o
AR drivers/ptp/built-in.a
CC drivers/cpufreq/cpufreq_ondemand.o
CC lib/iomap_copy.o
CC lib/devres.o
AR net/sunrpc/built-in.a
CC drivers/acpi/acpica/utdebug.o
CC drivers/gpu/drm/i915/gt/gen7_renderclear.o
CC drivers/usb/core/devices.o
CC [M] net/netfilter/xt_MASQUERADE.o
CC arch/x86/kernel/trace.o
CC drivers/cpuidle/sysfs.o
CC drivers/acpi/acpica/utdecode.o
CC drivers/usb/host/xhci-mem.o
CC net/core/failover.o
CC kernel/dma.o
CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o
CC [M] net/netfilter/xt_addrtype.o
AR drivers/net/ethernet/fujitsu/built-in.a
CC drivers/usb/core/phy.o
CC drivers/gpu/drm/i915/gt/gen8_engine_cs.o
AR drivers/i2c/built-in.a
CC [M] drivers/gpu/drm/xe/xe_gt_throttle.o
CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o
CC drivers/input/ff-memless.o
CC lib/check_signature.o
CC drivers/usb/host/xhci-ext-caps.o
CC drivers/thermal/thermal_hwmon.o
CC drivers/scsi/scsi_sysfs.o
AR mm/built-in.a
CC arch/x86/kernel/rethook.o
CC net/mac80211/chan.o
CC net/mac80211/trace.o
CC drivers/input/sparse-keymap.o
CC kernel/smp.o
CC fs/fs_parser.o
CC drivers/gpu/drm/i915/gt/gen8_ppgtt.o
CC lib/interval_tree.o
CC drivers/acpi/acpica/utdelete.o
AR drivers/net/ethernet/fungible/built-in.a
CC drivers/gpu/drm/i915/gt/intel_breadcrumbs.o
CC drivers/input/vivaldi-fmap.o
CC drivers/thermal/gov_step_wise.o
CC net/ipv6/xfrm6_input.o
CC net/mac80211/mlme.o
CC lib/assoc_array.o
AR drivers/cpuidle/governors/built-in.a
CC lib/bitrev.o
CC drivers/cpuidle/poll_state.o
CC drivers/acpi/acpica/uterror.o
CC drivers/usb/core/port.o
CC drivers/acpi/event.o
CC drivers/acpi/acpica/uteval.o
CC drivers/cpufreq/cpufreq_governor.o
AR drivers/firmware/arm_ffa/built-in.a
AR drivers/firmware/arm_scmi/built-in.a
AR drivers/firmware/broadcom/built-in.a
CC net/ipv4/af_inet.o
AR drivers/firmware/cirrus/built-in.a
AR drivers/firmware/meson/built-in.a
CC drivers/usb/host/xhci-ring.o
AR drivers/firmware/microchip/built-in.a
CC drivers/thermal/gov_user_space.o
CC net/mac80211/tdls.o
CC drivers/acpi/acpica/utglobal.o
CC drivers/firmware/efi/efi-bgrt.o
CC drivers/firmware/efi/libstub/efi-stub-helper.o
CC drivers/input/input-leds.o
CC drivers/cpuidle/cpuidle-haltpoll.o
CC drivers/cpufreq/cpufreq_governor_attr_set.o
AR drivers/crypto/stm32/built-in.a
CC arch/x86/kernel/vmcore_info_32.o
AR drivers/crypto/xilinx/built-in.a
CC drivers/usb/core/hcd-pci.o
AR drivers/crypto/hisilicon/built-in.a
CC net/ipv4/igmp.o
AR drivers/crypto/intel/keembay/built-in.a
AR drivers/crypto/intel/ixp4xx/built-in.a
AR drivers/crypto/intel/built-in.a
CC fs/fsopen.o
CC kernel/uid16.o
AR drivers/crypto/starfive/built-in.a
AR drivers/crypto/built-in.a
CC drivers/usb/host/xhci-hub.o
CC drivers/clocksource/acpi_pm.o
CC drivers/usb/core/usb-acpi.o
CC drivers/md/dm-io.o
AR net/core/built-in.a
CC drivers/firmware/efi/efi.o
CC net/ipv4/fib_frontend.o
CC net/ipv6/xfrm6_output.o
CC lib/crc-ccitt.o
CC drivers/clocksource/i8253.o
CC [M] drivers/gpu/drm/xe/xe_gt_topology.o
CC drivers/acpi/acpica/uthex.o
AR drivers/thermal/built-in.a
CC drivers/gpu/drm/drm_fourcc.o
CC fs/init.o
CC drivers/hid/usbhid/hid-core.o
AR drivers/cpuidle/built-in.a
CC drivers/input/evdev.o
AR net/netfilter/built-in.a
CC net/ipv6/xfrm6_protocol.o
CC kernel/kallsyms.o
CC [M] drivers/gpu/drm/xe/xe_guc.o
CC drivers/cpufreq/acpi-cpufreq.o
AR drivers/net/ethernet/broadcom/built-in.a
CC lib/crc16.o
AR drivers/net/ethernet/google/built-in.a
CC drivers/gpu/drm/drm_framebuffer.o
AR drivers/net/ethernet/huawei/built-in.a
CC arch/x86/kernel/machine_kexec_32.o
CC drivers/usb/host/xhci-dbg.o
CC drivers/net/ethernet/intel/e1000/e1000_main.o
AR drivers/net/ethernet/i825xx/built-in.a
CC drivers/acpi/evged.o
AR drivers/net/ethernet/microsoft/built-in.a
CC drivers/cpufreq/amd-pstate.o
AR drivers/net/ethernet/litex/built-in.a
CC drivers/md/dm-kcopyd.o
CC drivers/acpi/acpica/utids.o
CC drivers/gpu/drm/drm_gem.o
AR drivers/scsi/built-in.a
CC drivers/hid/usbhid/hiddev.o
CC drivers/acpi/sysfs.o
CC drivers/hid/hid-core.o
CC drivers/cpufreq/amd-pstate-trace.o
CC [M] drivers/gpu/drm/xe/xe_guc_ads.o
AR drivers/clocksource/built-in.a
CC net/ipv4/fib_semantics.o
CC net/ipv6/netfilter.o
AR drivers/usb/core/built-in.a
CC drivers/acpi/acpica/utinit.o
CC drivers/firmware/efi/libstub/gop.o
HOSTCC lib/gen_crc32table
CC drivers/gpu/drm/i915/gt/intel_context.o
CC kernel/acct.o
CC [M] drivers/gpu/drm/xe/xe_guc_capture.o
CC drivers/hid/hid-input.o
CC lib/xxhash.o
CC drivers/hid/usbhid/hid-pidff.o
CC drivers/gpu/drm/i915/gt/intel_context_sseu.o
AR drivers/net/ethernet/marvell/octeon_ep/built-in.a
CC fs/kernel_read_file.o
CC drivers/md/dm-sysfs.o
AR drivers/net/ethernet/marvell/octeon_ep_vf/built-in.a
AR drivers/net/ethernet/marvell/octeontx2/built-in.a
AR drivers/net/ethernet/marvell/prestera/built-in.a
CC drivers/net/ethernet/marvell/sky2.o
CC drivers/net/ethernet/intel/e1000/e1000_hw.o
CC drivers/acpi/acpica/utlock.o
CC net/mac80211/ocb.o
CC kernel/vmcore_info.o
CC drivers/gpu/drm/drm_ioctl.o
AR drivers/firmware/imx/built-in.a
CC drivers/firmware/efi/libstub/secureboot.o
AS arch/x86/kernel/relocate_kernel_32.o
CC lib/genalloc.o
CC arch/x86/kernel/crash_dump_32.o
CC fs/mnt_idmapping.o
CC drivers/hid/hid-quirks.o
CC drivers/gpu/drm/i915/gt/intel_engine_cs.o
AR drivers/input/built-in.a
AR drivers/platform/x86/amd/built-in.a
AR drivers/platform/x86/intel/built-in.a
CC drivers/platform/x86/wmi.o
CC drivers/acpi/acpica/utmath.o
CC drivers/net/ethernet/intel/e1000e/82571.o
CC drivers/firmware/efi/libstub/tpm.o
CC kernel/elfcorehdr.o
CC drivers/platform/x86/wmi-bmof.o
CC drivers/acpi/acpica/utmisc.o
CC arch/x86/kernel/crash.o
CC net/mac80211/airtime.o
CC drivers/hid/hid-debug.o
AR drivers/platform/surface/built-in.a
CC drivers/cpufreq/intel_pstate.o
AR drivers/net/ethernet/mellanox/built-in.a
AR drivers/net/ethernet/meta/built-in.a
CC drivers/net/ethernet/intel/e1000/e1000_ethtool.o
CC arch/x86/kernel/module.o
CC arch/x86/kernel/doublefault_32.o
CC drivers/firmware/efi/libstub/file.o
CC net/ipv6/proc.o
CC [M] drivers/gpu/drm/xe/xe_guc_ct.o
CC drivers/net/ethernet/intel/e1000e/ich8lan.o
CC lib/percpu_counter.o
CC fs/remap_range.o
CC net/ipv6/syncookies.o
CC lib/audit.o
CC drivers/net/ethernet/intel/e1000/e1000_param.o
CC drivers/acpi/acpica/utmutex.o
CC drivers/firmware/efi/vars.o
CC drivers/hid/hidraw.o
CC drivers/acpi/property.o
CC drivers/platform/x86/eeepc-laptop.o
AR drivers/firmware/psci/built-in.a
CC drivers/net/ethernet/intel/e1000e/80003es2lan.o
CC net/ipv6/calipso.o
CC drivers/usb/host/xhci-trace.o
CC lib/syscall.o
CC drivers/net/ethernet/intel/e1000e/mac.o
CC kernel/crash_reserve.o
AR drivers/hid/usbhid/built-in.a
CC drivers/acpi/acpica/utnonansi.o
CC drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o
CC drivers/md/dm-stats.o
CC net/ipv4/fib_trie.o
CC drivers/firmware/efi/reboot.o
CC drivers/gpu/drm/i915/gt/intel_engine_pm.o
CC drivers/acpi/debugfs.o
CC drivers/firmware/efi/memattr.o
CC drivers/firmware/efi/tpm.o
CC drivers/firmware/efi/libstub/mem.o
CC drivers/md/dm-rq.o
CC drivers/gpu/drm/drm_lease.o
CC drivers/md/dm-io-rewind.o
AR drivers/firmware/qcom/built-in.a
CC drivers/net/ethernet/intel/e1000e/manage.o
CC drivers/platform/x86/p2sb.o
CC drivers/acpi/acpica/utobject.o
CC net/ipv6/ah6.o
CC arch/x86/kernel/early_printk.o
CC drivers/acpi/acpi_lpat.o
CC lib/errname.o
CC net/mac80211/eht.o
CC lib/nlattr.o
CC drivers/net/ethernet/intel/e100.o
CC drivers/firmware/efi/libstub/random.o
CC fs/pidfs.o
CC kernel/kexec_core.o
CC drivers/gpu/drm/drm_managed.o
CC drivers/acpi/acpi_pcc.o
CC arch/x86/kernel/hpet.o
CC net/mac80211/led.o
CC drivers/usb/host/xhci-debugfs.o
CC drivers/hid/hid-generic.o
AR drivers/firmware/smccc/built-in.a
CC lib/cpu_rmap.o
CC drivers/acpi/acpica/utosi.o
CC lib/dynamic_queue_limits.o
CC drivers/acpi/ac.o
CC arch/x86/kernel/amd_nb.o
CC lib/glob.o
CC drivers/md/dm-builtin.o
CC drivers/mailbox/mailbox.o
AR drivers/perf/built-in.a
CC drivers/firmware/efi/libstub/randomalloc.o
CC [M] drivers/gpu/drm/xe/xe_guc_db_mgr.o
AR drivers/platform/x86/built-in.a
AR drivers/platform/built-in.a
CC fs/buffer.o
CC drivers/acpi/acpica/utownerid.o
CC net/mac80211/pm.o
CC net/ipv4/fib_notifier.o
CC drivers/net/ethernet/intel/e1000e/nvm.o
CC kernel/crash_core.o
CC drivers/gpu/drm/i915/gt/intel_engine_user.o
CC arch/x86/kernel/kvm.o
CC drivers/md/dm-raid1.o
CC drivers/gpu/drm/drm_mm.o
CC lib/strncpy_from_user.o
CC net/mac80211/rc80211_minstrel_ht.o
AR drivers/hwtracing/intel_th/built-in.a
CC lib/strnlen_user.o
AR drivers/net/ethernet/micrel/built-in.a
AR drivers/firmware/tegra/built-in.a
CC drivers/firmware/efi/memmap.o
CC drivers/gpu/drm/i915/gt/intel_execlists_submission.o
CC drivers/hid/hid-a4tech.o
CC drivers/firmware/efi/capsule.o
CC drivers/usb/host/xhci-pci.o
AR drivers/firmware/xilinx/built-in.a
CC fs/mpage.o
AR drivers/android/built-in.a
CC drivers/hid/hid-apple.o
CC drivers/acpi/acpica/utpredef.o
CC drivers/net/ethernet/intel/e1000e/phy.o
AR drivers/net/ethernet/intel/e1000/built-in.a
CC drivers/firmware/efi/libstub/pci.o
CC drivers/mailbox/pcc.o
CC drivers/gpu/drm/i915/gt/intel_ggtt.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o
CC drivers/firmware/dmi_scan.o
CC lib/net_utils.o
AR drivers/cpufreq/built-in.a
CC kernel/kexec.o
CC net/mac80211/wbrf.o
AR drivers/net/ethernet/microchip/built-in.a
CC drivers/net/ethernet/intel/e1000e/param.o
CC drivers/acpi/button.o
CC drivers/gpu/drm/i915/gt/intel_gt.o
CC net/ipv6/esp6.o
CC drivers/firmware/efi/libstub/skip_spaces.o
CC fs/proc_namespace.o
AR drivers/net/ethernet/marvell/built-in.a
CC drivers/firmware/efi/esrt.o
CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o
CC drivers/firmware/dmi-id.o
CC drivers/firmware/efi/runtime-wrappers.o
CC drivers/acpi/acpica/utresdecode.o
CC fs/direct-io.o
CC drivers/firmware/efi/libstub/lib-cmdline.o
CC kernel/utsname.o
CC drivers/hid/hid-belkin.o
CC drivers/net/ethernet/intel/e1000e/ethtool.o
CC drivers/acpi/fan_core.o
CC net/ipv6/sit.o
CC drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o
CC drivers/firmware/memmap.o
CC [M] drivers/gpu/drm/xe/xe_guc_id_mgr.o
CC drivers/md/dm-log.o
CC drivers/acpi/acpica/utresrc.o
AR drivers/mailbox/built-in.a
CC drivers/firmware/efi/capsule-loader.o
AR drivers/nvmem/layouts/built-in.a
CC drivers/nvmem/core.o
CC lib/sg_pool.o
CC arch/x86/kernel/kvmclock.o
CC drivers/firmware/efi/libstub/lib-ctype.o
AR drivers/net/ethernet/mscc/built-in.a
CC fs/eventpoll.o
CC drivers/firmware/efi/libstub/alignedmem.o
AR drivers/net/ethernet/myricom/built-in.a
CC drivers/net/ethernet/intel/e1000e/netdev.o
CC drivers/acpi/fan_attr.o
CC drivers/net/ethernet/intel/e1000e/ptp.o
CC net/ipv4/inet_fragment.o
CC drivers/hid/hid-cherry.o
CC [M] drivers/gpu/drm/xe/xe_guc_klv_helpers.o
CC net/ipv6/addrconf_core.o
CC drivers/acpi/fan_hwmon.o
CC drivers/md/dm-region-hash.o
CC kernel/pid_namespace.o
CC drivers/gpu/drm/drm_mode_config.o
CC drivers/md/dm-zero.o
CC drivers/hid/hid-chicony.o
CC drivers/gpu/drm/i915/gt/intel_gt_ccs_mode.o
CC drivers/acpi/acpica/utstate.o
CC drivers/acpi/acpi_video.o
CC net/ipv6/exthdrs_core.o
CC lib/stackdepot.o
CC drivers/acpi/acpica/utstring.o
AR drivers/net/ethernet/natsemi/built-in.a
CC fs/anon_inodes.o
CC net/ipv6/ip6_checksum.o
CC kernel/stop_machine.o
CC drivers/firmware/efi/libstub/relocate.o
CC drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o
CC drivers/gpu/drm/drm_mode_object.o
CC drivers/gpu/drm/i915/gt/intel_gt_debugfs.o
CC kernel/audit.o
CC drivers/hid/hid-cypress.o
CC [M] drivers/gpu/drm/xe/xe_guc_log.o
CC arch/x86/kernel/paravirt.o
CC net/ipv4/ping.o
AR drivers/net/ethernet/neterion/built-in.a
CC lib/asn1_decoder.o
AR drivers/usb/host/built-in.a
CC drivers/gpu/drm/drm_modes.o
CC arch/x86/kernel/pvclock.o
CC drivers/firmware/efi/libstub/printk.o
AR drivers/usb/built-in.a
CC drivers/acpi/acpica/utstrsuppt.o
CC drivers/acpi/video_detect.o
CC drivers/firmware/efi/earlycon.o
CC [M] drivers/gpu/drm/xe/xe_guc_pc.o
AR drivers/net/ethernet/netronome/built-in.a
CC kernel/auditfilter.o
GEN lib/oid_registry_data.c
CC net/ipv6/ip6_icmp.o
CC drivers/gpu/drm/drm_modeset_lock.o
CC arch/x86/kernel/pcspeaker.o
CC fs/signalfd.o
CC drivers/firmware/efi/libstub/vsprintf.o
CC drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o
AR drivers/nvmem/built-in.a
CC drivers/hid/hid-ezkey.o
AR drivers/md/built-in.a
CC drivers/acpi/processor_driver.o
CC net/ipv4/ip_tunnel_core.o
CC fs/timerfd.o
CC drivers/gpu/drm/drm_plane.o
CC drivers/acpi/acpica/utstrtoul64.o
CC drivers/hid/hid-gyration.o
CC drivers/acpi/acpica/utxface.o
AR drivers/net/ethernet/ni/built-in.a
CC arch/x86/kernel/check.o
CC arch/x86/kernel/uprobes.o
CC arch/x86/kernel/perf_regs.o
CC lib/ucs2_string.o
CC arch/x86/kernel/tracepoint.o
CC drivers/firmware/efi/libstub/x86-stub.o
CC fs/eventfd.o
CC [M] drivers/gpu/drm/xe/xe_guc_submit.o
CC drivers/net/ethernet/nvidia/forcedeth.o
CC lib/sbitmap.o
CC drivers/acpi/acpica/utxfinit.o
CC net/ipv4/gre_offload.o
CC drivers/acpi/processor_thermal.o
CC drivers/hid/hid-ite.o
CC drivers/hid/hid-kensington.o
CC drivers/gpu/drm/drm_prime.o
AR drivers/net/ethernet/oki-semi/built-in.a
CC drivers/hid/hid-lg.o
CC fs/aio.o
CC drivers/acpi/processor_idle.o
CC kernel/auditsc.o
CC arch/x86/kernel/itmt.o
AR drivers/net/ethernet/packetengines/built-in.a
CC net/ipv6/output_core.o
CC drivers/firmware/efi/libstub/smbios.o
CC drivers/acpi/processor_throttling.o
CC [M] drivers/gpu/drm/xe/xe_heci_gsc.o
CC arch/x86/kernel/umip.o
CC drivers/gpu/drm/i915/gt/intel_gt_irq.o
CC net/ipv6/protocol.o
CC drivers/hid/hid-lgff.o
AR drivers/net/ethernet/qlogic/built-in.a
CC fs/locks.o
STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o
STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o
AR drivers/firmware/efi/built-in.a
CC [M] drivers/gpu/drm/xe/xe_hw_engine.o
STUBCPY drivers/firmware/efi/libstub/file.stub.o
CC drivers/gpu/drm/i915/gt/intel_gt_mcr.o
CC drivers/gpu/drm/drm_print.o
CC drivers/acpi/acpica/utxferror.o
AR drivers/net/ethernet/qualcomm/emac/built-in.a
AR drivers/net/ethernet/qualcomm/built-in.a
CC drivers/acpi/processor_perflib.o
CC arch/x86/kernel/unwind_frame.o
CC lib/group_cpus.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_class_sysfs.o
CC net/ipv4/metrics.o
STUBCPY drivers/firmware/efi/libstub/gop.stub.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm.o
CC kernel/audit_watch.o
CC drivers/gpu/drm/drm_property.o
CC drivers/acpi/acpica/utxfmutex.o
CC drivers/net/ethernet/realtek/8139too.o
AR drivers/net/ethernet/renesas/built-in.a
CC drivers/gpu/drm/drm_rect.o
CC [M] drivers/gpu/drm/xe/xe_hw_engine_group.o
STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o
CC net/ipv4/netlink.o
CC drivers/acpi/container.o
CC drivers/gpu/drm/drm_syncobj.o
AR drivers/net/ethernet/rdc/built-in.a
CC lib/fw_table.o
CC drivers/gpu/drm/drm_sysfs.o
STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o
STUBCPY drivers/firmware/efi/libstub/mem.stub.o
STUBCPY drivers/firmware/efi/libstub/pci.stub.o
STUBCPY drivers/firmware/efi/libstub/printk.stub.o
STUBCPY drivers/firmware/efi/libstub/random.stub.o
STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o
CC drivers/gpu/drm/drm_trace_points.o
STUBCPY drivers/firmware/efi/libstub/relocate.stub.o
STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o
STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o
CC drivers/gpu/drm/drm_vblank.o
STUBCPY drivers/firmware/efi/libstub/smbios.stub.o
STUBCPY drivers/firmware/efi/libstub/tpm.stub.o
STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o
STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o
CC drivers/acpi/thermal_lib.o
CC [M] drivers/gpu/drm/xe/xe_hw_fence.o
AR drivers/firmware/efi/libstub/lib.a
CC net/ipv6/ip6_offload.o
AR drivers/firmware/built-in.a
CC drivers/hid/hid-lg4ff.o
CC net/ipv4/nexthop.o
CC drivers/gpu/drm/drm_vblank_work.o
CC drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o
CC drivers/gpu/drm/drm_vma_manager.o
CC net/ipv4/udp_tunnel_stub.o
AR drivers/acpi/acpica/built-in.a
CC drivers/acpi/thermal.o
CC [M] drivers/gpu/drm/xe/xe_huc.o
CC drivers/hid/hid-lg-g15.o
CC kernel/audit_fsnotify.o
AR arch/x86/kernel/built-in.a
AR arch/x86/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gt_requests.o
CC drivers/acpi/nhlt.o
CC net/ipv4/ip_tunnel.o
CC fs/binfmt_misc.o
AR drivers/net/ethernet/rocker/built-in.a
CC [M] drivers/gpu/drm/xe/xe_irq.o
CC net/ipv4/sysctl_net_ipv4.o
CC drivers/net/ethernet/realtek/r8169_main.o
CC drivers/acpi/acpi_memhotplug.o
CC drivers/net/ethernet/realtek/r8169_firmware.o
CC kernel/audit_tree.o
AR lib/lib.a
GEN lib/crc32table.h
CC drivers/acpi/ioapic.o
CC lib/oid_registry.o
CC net/ipv6/tcpv6_offload.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs.o
CC fs/binfmt_script.o
CC drivers/acpi/battery.o
AR drivers/net/ethernet/samsung/built-in.a
CC drivers/acpi/bgrt.o
CC drivers/gpu/drm/drm_writeback.o
AR drivers/net/ethernet/seeq/built-in.a
CC net/ipv4/proc.o
CC drivers/acpi/spcr.o
CC drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o
CC net/ipv6/exthdrs_offload.o
CC fs/binfmt_elf.o
CC drivers/hid/hid-microsoft.o
CC fs/mbcache.o
CC net/ipv6/inet6_hashtables.o
CC drivers/hid/hid-monterey.o
CC [M] drivers/gpu/drm/xe/xe_lrc.o
CC lib/crc32.o
CC net/ipv4/fib_rules.o
CC drivers/net/ethernet/realtek/r8169_phy_config.o
AR net/mac80211/built-in.a
CC drivers/hid/hid-ntrig.o
AR drivers/net/ethernet/silan/built-in.a
CC drivers/gpu/drm/i915/gt/intel_gtt.o
CC [M] drivers/gpu/drm/xe/xe_migrate.o
CC fs/posix_acl.o
CC drivers/gpu/drm/drm_panel.o
CC drivers/gpu/drm/i915/gt/intel_llc.o
CC net/ipv4/ipmr.o
CC [M] drivers/gpu/drm/xe/xe_mmio.o
CC drivers/hid/hid-pl.o
CC net/ipv6/mcast_snoop.o
CC [M] drivers/gpu/drm/xe/xe_mocs.o
AR drivers/net/ethernet/sis/built-in.a
CC fs/coredump.o
CC drivers/gpu/drm/drm_pci.o
CC net/ipv4/ipmr_base.o
CC net/ipv4/syncookies.o
CC fs/drop_caches.o
CC drivers/hid/hid-petalynx.o
CC [M] drivers/gpu/drm/xe/xe_module.o
AR drivers/net/ethernet/sfc/built-in.a
CC kernel/kprobes.o
CC drivers/gpu/drm/i915/gt/intel_lrc.o
CC [M] drivers/gpu/drm/xe/xe_oa.o
CC drivers/gpu/drm/drm_debugfs.o
CC net/ipv4/tunnel4.o
CC drivers/hid/hid-redragon.o
AR lib/built-in.a
AR drivers/net/ethernet/smsc/built-in.a
CC [M] drivers/gpu/drm/xe/xe_observation.o
CC drivers/gpu/drm/drm_debugfs_crc.o
AR drivers/net/ethernet/socionext/built-in.a
CC drivers/gpu/drm/i915/gt/intel_migrate.o
CC kernel/seccomp.o
CC kernel/relay.o
CC [M] drivers/gpu/drm/xe/xe_pat.o
CC drivers/gpu/drm/drm_panel_orientation_quirks.o
CC drivers/gpu/drm/i915/gt/intel_mocs.o
AR drivers/acpi/built-in.a
AR drivers/net/ethernet/stmicro/built-in.a
AR drivers/net/ethernet/sun/built-in.a
CC net/ipv4/ipconfig.o
CC drivers/gpu/drm/drm_buddy.o
CC drivers/hid/hid-samsung.o
CC fs/sysctls.o
CC [M] drivers/gpu/drm/xe/xe_pci.o
CC drivers/gpu/drm/drm_gem_shmem_helper.o
CC drivers/gpu/drm/i915/gt/intel_ppgtt.o
CC [M] drivers/gpu/drm/xe/xe_pcode.o
CC [M] drivers/gpu/drm/xe/xe_pm.o
AR drivers/net/ethernet/tehuti/built-in.a
CC kernel/utsname_sysctl.o
AR drivers/net/ethernet/ti/built-in.a
CC drivers/hid/hid-sony.o
CC drivers/gpu/drm/i915/gt/intel_rc6.o
CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o
CC [M] drivers/gpu/drm/xe/xe_pt.o
CC net/ipv4/netfilter.o
CC drivers/gpu/drm/drm_atomic_helper.o
CC fs/fhandle.o
AR drivers/net/ethernet/nvidia/built-in.a
AR drivers/net/ethernet/vertexcom/built-in.a
AR drivers/net/ethernet/via/built-in.a
CC [M] drivers/gpu/drm/xe/xe_pt_walk.o
AR drivers/net/ethernet/wangxun/built-in.a
CC net/ipv4/tcp_cubic.o
CC drivers/hid/hid-sunplus.o
CC net/ipv4/tcp_sigpool.o
AR drivers/net/ethernet/intel/e1000e/built-in.a
AR drivers/net/ethernet/intel/built-in.a
CC net/ipv4/cipso_ipv4.o
CC [M] drivers/gpu/drm/xe/xe_query.o
CC drivers/hid/hid-topseed.o
CC [M] drivers/gpu/drm/xe/xe_range_fence.o
CC drivers/gpu/drm/i915/gt/intel_region_lmem.o
CC net/ipv4/xfrm4_policy.o
CC kernel/delayacct.o
CC drivers/gpu/drm/drm_atomic_state_helper.o
AR net/ipv6/built-in.a
CC [M] drivers/gpu/drm/xe/xe_reg_sr.o
AR drivers/net/ethernet/wiznet/built-in.a
CC drivers/gpu/drm/i915/gt/intel_renderstate.o
CC net/ipv4/xfrm4_state.o
CC kernel/taskstats.o
CC net/ipv4/xfrm4_input.o
CC kernel/tsacct.o
CC drivers/gpu/drm/i915/gt/intel_reset.o
CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o
AR drivers/net/ethernet/xilinx/built-in.a
CC drivers/gpu/drm/drm_crtc_helper.o
CC drivers/gpu/drm/drm_damage_helper.o
CC [M] drivers/gpu/drm/xe/xe_rtp.o
CC kernel/tracepoint.o
CC net/ipv4/xfrm4_output.o
CC drivers/gpu/drm/i915/gt/intel_ring.o
AR drivers/net/ethernet/xircom/built-in.a
CC drivers/gpu/drm/i915/gt/intel_ring_submission.o
AR drivers/net/ethernet/synopsys/built-in.a
CC kernel/irq_work.o
CC kernel/static_call.o
AR drivers/net/ethernet/pensando/built-in.a
CC drivers/gpu/drm/drm_encoder_slave.o
CC net/ipv4/xfrm4_protocol.o
CC drivers/gpu/drm/drm_flip_work.o
CC drivers/gpu/drm/i915/gt/intel_rps.o
CC [M] drivers/gpu/drm/xe/xe_ring_ops.o
CC [M] drivers/gpu/drm/xe/xe_sa.o
CC drivers/gpu/drm/i915/gt/intel_sa_media.o
CC drivers/gpu/drm/drm_format_helper.o
AR fs/built-in.a
CC [M] drivers/gpu/drm/xe/xe_sched_job.o
CC kernel/padata.o
CC drivers/gpu/drm/i915/gt/intel_sseu.o
CC drivers/gpu/drm/drm_gem_atomic_helper.o
CC drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_step.o
AR drivers/hid/built-in.a
CC drivers/gpu/drm/drm_gem_framebuffer_helper.o
CC [M] drivers/gpu/drm/xe/xe_sync.o
CC kernel/jump_label.o
CC drivers/gpu/drm/i915/gt/intel_timeline.o
CC [M] drivers/gpu/drm/xe/xe_tile.o
CC drivers/gpu/drm/i915/gt/intel_tlb.o
CC drivers/gpu/drm/drm_kms_helper_common.o
CC drivers/gpu/drm/i915/gt/intel_wopcm.o
CC kernel/context_tracking.o
CC drivers/gpu/drm/drm_modeset_helper.o
CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o
AR drivers/net/ethernet/realtek/built-in.a
AR drivers/net/ethernet/built-in.a
CC drivers/gpu/drm/i915/gt/intel_workarounds.o
CC kernel/iomem.o
CC [M] drivers/gpu/drm/xe/xe_trace.o
CC drivers/gpu/drm/drm_plane_helper.o
CC kernel/rseq.o
CC drivers/gpu/drm/i915/gt/shmem_utils.o
CC [M] drivers/gpu/drm/xe/xe_trace_bo.o
AR drivers/net/built-in.a
CC [M] drivers/gpu/drm/xe/xe_trace_guc.o
CC drivers/gpu/drm/drm_probe_helper.o
CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o
CC drivers/gpu/drm/i915/gt/sysfs_engines.o
CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o
CC drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o
CC drivers/gpu/drm/drm_self_refresh_helper.o
CC drivers/gpu/drm/drm_simple_kms_helper.o
CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o
CC drivers/gpu/drm/i915/gt/gen6_renderstate.o
CC drivers/gpu/drm/bridge/panel.o
CC [M] drivers/gpu/drm/xe/xe_tuning.o
CC drivers/gpu/drm/i915/gt/gen7_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_uc.o
CC drivers/gpu/drm/drm_mipi_dsi.o
CC drivers/gpu/drm/i915/gt/gen8_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_uc_fw.o
CC [M] drivers/gpu/drm/drm_exec.o
CC drivers/gpu/drm/i915/gt/gen9_renderstate.o
CC [M] drivers/gpu/drm/xe/xe_vm.o
CC [M] drivers/gpu/drm/drm_gpuvm.o
CC [M] drivers/gpu/drm/drm_suballoc.o
CC [M] drivers/gpu/drm/xe/xe_vram.o
CC drivers/gpu/drm/i915/gem/i915_gem_busy.o
CC [M] drivers/gpu/drm/xe/xe_vram_freq.o
CC drivers/gpu/drm/i915/gem/i915_gem_clflush.o
AR net/ipv4/built-in.a
AR net/built-in.a
CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o
CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o
CC drivers/gpu/drm/i915/gem/i915_gem_context.o
CC [M] drivers/gpu/drm/xe/xe_wa.o
CC drivers/gpu/drm/i915/gem/i915_gem_create.o
CC [M] drivers/gpu/drm/xe/xe_wopcm.o
CC [M] drivers/gpu/drm/xe/xe_hmm.o
CC [M] drivers/gpu/drm/xe/xe_hwmon.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf.o
CC drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o
CC [M] drivers/gpu/drm/xe/xe_guc_relay.o
CC drivers/gpu/drm/i915/gem/i915_gem_domain.o
CC drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o
CC drivers/gpu/drm/i915/gem/i915_gem_internal.o
CC drivers/gpu/drm/i915/gem/i915_gem_lmem.o
CC [M] drivers/gpu/drm/xe/xe_memirq.o
CC drivers/gpu/drm/i915/gem/i915_gem_mman.o
CC [M] drivers/gpu/drm/xe/xe_sriov.o
CC drivers/gpu/drm/i915/gem/i915_gem_object.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o
CC drivers/gpu/drm/i915/gem/i915_gem_pages.o
CC drivers/gpu/drm/i915/gem/i915_gem_phys.o
CC [M] drivers/gpu/drm/xe/display/ext/i915_utils.o
AR kernel/built-in.a
CC drivers/gpu/drm/i915/gem/i915_gem_pm.o
CC [M] drivers/gpu/drm/xe/display/intel_bo.o
CC drivers/gpu/drm/i915/gem/i915_gem_region.o
CC [M] drivers/gpu/drm/xe/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/gem/i915_gem_shmem.o
CC drivers/gpu/drm/i915/gem/i915_gem_shrinker.o
CC drivers/gpu/drm/i915/gem/i915_gem_stolen.o
CC [M] drivers/gpu/drm/xe/display/intel_fbdev_fb.o
LD [M] drivers/gpu/drm/drm_suballoc_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_throttle.o
CC [M] drivers/gpu/drm/xe/display/xe_display.o
CC drivers/gpu/drm/i915/gem/i915_gem_tiling.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm.o
CC [M] drivers/gpu/drm/xe/display/xe_display_misc.o
LD [M] drivers/gpu/drm/drm_ttm_helper.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o
CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o
CC [M] drivers/gpu/drm/xe/display/xe_display_wa.o
CC [M] drivers/gpu/drm/xe/display/xe_dsb_buffer.o
CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o
CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o
CC drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o
CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o
CC drivers/gpu/drm/i915/gem/i915_gem_userptr.o
CC [M] drivers/gpu/drm/xe/display/xe_tdf.o
CC drivers/gpu/drm/i915/gem/i915_gem_wait.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o
CC [M] drivers/gpu/drm/xe/i915-soc/intel_rom.o
CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_alpm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o
CC drivers/gpu/drm/i915/gem/i915_gemfs.o
CC drivers/gpu/drm/i915/i915_active.o
CC drivers/gpu/drm/i915/i915_cmd_parser.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o
CC drivers/gpu/drm/i915/i915_deps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o
CC drivers/gpu/drm/i915/i915_gem.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o
CC drivers/gpu/drm/i915/i915_gem_evict.o
CC drivers/gpu/drm/i915/i915_gem_gtt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o
CC drivers/gpu/drm/i915/i915_gem_ww.o
CC drivers/gpu/drm/i915/i915_query.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o
CC drivers/gpu/drm/i915/i915_request.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o
CC drivers/gpu/drm/i915/i915_scheduler.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o
CC drivers/gpu/drm/i915/i915_trace_points.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o
CC drivers/gpu/drm/i915/i915_ttm_buddy_manager.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o
CC drivers/gpu/drm/i915/i915_vma.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/i915_vma_resource.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o
CC drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_params.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_test.o
CC drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o
CC drivers/gpu/drm/i915/gt/intel_gsc.o
CC drivers/gpu/drm/i915/i915_hwmon.o
CC drivers/gpu/drm/i915/display/hsw_ips.o
CC drivers/gpu/drm/i915/display/i9xx_plane.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o
CC drivers/gpu/drm/i915/display/i9xx_wm.o
CC drivers/gpu/drm/i915/display/intel_alpm.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt_common.o
CC drivers/gpu/drm/i915/display/intel_atomic.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o
CC drivers/gpu/drm/i915/display/intel_atomic_plane.o
CC drivers/gpu/drm/i915/display/intel_audio.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_bios.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_bo.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o
CC drivers/gpu/drm/i915/display/intel_bw.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o
CC drivers/gpu/drm/i915/display/intel_cdclk.o
CC drivers/gpu/drm/i915/display/intel_color.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o
CC drivers/gpu/drm/i915/display/intel_combo_phy.o
CC drivers/gpu/drm/i915/display/intel_connector.o
CC drivers/gpu/drm/i915/display/intel_crtc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o
CC drivers/gpu/drm/i915/display/intel_crtc_state_dump.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o
CC drivers/gpu/drm/i915/display/intel_cursor.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_display.o
CC drivers/gpu/drm/i915/display/intel_display_driver.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp_gsc_message.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_display_irq.o
CC drivers/gpu/drm/i915/display/intel_display_params.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_link_bw.o
CC drivers/gpu/drm/i915/display/intel_display_power.o
CC drivers/gpu/drm/i915/display/intel_display_power_map.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o
CC drivers/gpu/drm/i915/display/intel_display_power_well.o
CC drivers/gpu/drm/i915/display/intel_display_reset.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/display/intel_display_rps.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o
CC drivers/gpu/drm/i915/display/intel_display_snapshot.o
CC drivers/gpu/drm/i915/display/intel_display_wa.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_dmc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_dpio_phy.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_dpll.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o
CC drivers/gpu/drm/i915/display/intel_dpll_mgr.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc_wl.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o
CC drivers/gpu/drm/i915/display/intel_dpt.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/intel_dpt_common.o
CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_drrs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_dsb.o
CC [M] drivers/gpu/drm/xe/xe_debugfs.o
CC drivers/gpu/drm/i915/display/intel_dsb_buffer.o
CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_gt_sriov_vf_debugfs.o
CC drivers/gpu/drm/i915/display/intel_fb.o
CC drivers/gpu/drm/i915/display/intel_fb_bo.o
CC drivers/gpu/drm/i915/display/intel_fb_pin.o
CC [M] drivers/gpu/drm/xe/xe_gt_stats.o
CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o
CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_fbc.o
CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o
CC drivers/gpu/drm/i915/display/intel_fdi.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_fifo_underrun.o
CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/intel_frontbuffer.o
CC drivers/gpu/drm/i915/display/intel_global_state.o
CC drivers/gpu/drm/i915/display/intel_hdcp.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc.o
CC drivers/gpu/drm/i915/display/intel_hdcp_gsc_message.o
CC drivers/gpu/drm/i915/display/intel_hotplug.o
CC drivers/gpu/drm/i915/display/intel_hotplug_irq.o
CC drivers/gpu/drm/i915/display/intel_hti.o
CC drivers/gpu/drm/i915/display/intel_link_bw.o
CC drivers/gpu/drm/i915/display/intel_load_detect.o
CC drivers/gpu/drm/i915/display/intel_lpe_audio.o
CC drivers/gpu/drm/i915/display/intel_modeset_lock.o
CC drivers/gpu/drm/i915/display/intel_modeset_setup.o
CC drivers/gpu/drm/i915/display/intel_modeset_verify.o
CC drivers/gpu/drm/i915/display/intel_overlay.o
CC drivers/gpu/drm/i915/display/intel_pch_display.o
CC drivers/gpu/drm/i915/display/intel_pch_refclk.o
CC drivers/gpu/drm/i915/display/intel_plane_initial.o
CC drivers/gpu/drm/i915/display/intel_pmdemand.o
CC drivers/gpu/drm/i915/display/intel_psr.o
CC drivers/gpu/drm/i915/display/intel_quirks.o
CC drivers/gpu/drm/i915/display/intel_sprite.o
CC drivers/gpu/drm/i915/display/intel_sprite_uapi.o
CC drivers/gpu/drm/i915/display/intel_tc.o
CC drivers/gpu/drm/i915/display/intel_vblank.o
CC drivers/gpu/drm/i915/display/intel_vga.o
CC drivers/gpu/drm/i915/display/intel_wm.o
CC drivers/gpu/drm/i915/display/skl_scaler.o
CC drivers/gpu/drm/i915/display/skl_universal_plane.o
CC drivers/gpu/drm/i915/display/skl_watermark.o
CC drivers/gpu/drm/i915/display/intel_acpi.o
CC drivers/gpu/drm/i915/display/intel_opregion.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs.o
CC drivers/gpu/drm/i915/display/intel_display_debugfs_params.o
CC drivers/gpu/drm/i915/display/intel_pipe_crc.o
CC drivers/gpu/drm/i915/display/dvo_ch7017.o
CC drivers/gpu/drm/i915/display/dvo_ch7xxx.o
CC drivers/gpu/drm/i915/display/dvo_ivch.o
CC drivers/gpu/drm/i915/display/dvo_ns2501.o
CC drivers/gpu/drm/i915/display/dvo_sil164.o
CC drivers/gpu/drm/i915/display/dvo_tfp410.o
CC drivers/gpu/drm/i915/display/g4x_dp.o
CC drivers/gpu/drm/i915/display/g4x_hdmi.o
CC drivers/gpu/drm/i915/display/icl_dsi.o
CC drivers/gpu/drm/i915/display/intel_backlight.o
CC drivers/gpu/drm/i915/display/intel_crt.o
CC drivers/gpu/drm/i915/display/intel_cx0_phy.o
CC drivers/gpu/drm/i915/display/intel_ddi.o
CC drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o
CC drivers/gpu/drm/i915/display/intel_display_device.o
CC drivers/gpu/drm/i915/display/intel_display_trace.o
CC drivers/gpu/drm/i915/display/intel_dkl_phy.o
CC drivers/gpu/drm/i915/display/intel_dp.o
CC drivers/gpu/drm/i915/display/intel_dp_aux.o
CC drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o
CC drivers/gpu/drm/i915/display/intel_dp_hdcp.o
CC drivers/gpu/drm/i915/display/intel_dp_link_training.o
CC drivers/gpu/drm/i915/display/intel_dp_mst.o
CC drivers/gpu/drm/i915/display/intel_dp_test.o
CC drivers/gpu/drm/i915/display/intel_dsi.o
CC drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o
CC drivers/gpu/drm/i915/display/intel_dsi_vbt.o
CC drivers/gpu/drm/i915/display/intel_dvo.o
CC drivers/gpu/drm/i915/display/intel_encoder.o
CC drivers/gpu/drm/i915/display/intel_gmbus.o
CC drivers/gpu/drm/i915/display/intel_hdmi.o
CC drivers/gpu/drm/i915/display/intel_lspcon.o
CC drivers/gpu/drm/i915/display/intel_lvds.o
CC drivers/gpu/drm/i915/display/intel_panel.o
LD [M] drivers/gpu/drm/xe/xe.o
CC drivers/gpu/drm/i915/display/intel_pps.o
CC drivers/gpu/drm/i915/display/intel_qp_tables.o
CC drivers/gpu/drm/i915/display/intel_sdvo.o
CC drivers/gpu/drm/i915/display/intel_snps_phy.o
CC drivers/gpu/drm/i915/display/intel_tv.o
CC drivers/gpu/drm/i915/display/intel_vdsc.o
CC drivers/gpu/drm/i915/display/intel_vrr.o
CC drivers/gpu/drm/i915/display/vlv_dsi.o
CC drivers/gpu/drm/i915/display/vlv_dsi_pll.o
CC drivers/gpu/drm/i915/i915_perf.o
CC drivers/gpu/drm/i915/pxp/intel_pxp.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_huc.o
CC drivers/gpu/drm/i915/pxp/intel_pxp_tee.o
CC drivers/gpu/drm/i915/i915_gpu_error.o
CC drivers/gpu/drm/i915/i915_vgpu.o
AR drivers/gpu/drm/i915/built-in.a
AR drivers/gpu/drm/built-in.a
AR drivers/gpu/built-in.a
AR drivers/built-in.a
AR built-in.a
AR vmlinux.a
LD vmlinux.o
OBJCOPY modules.builtin.modinfo
GEN modules.builtin
MODPOST Module.symvers
CC .vmlinux.export.o
CC [M] fs/efivarfs/efivarfs.mod.o
CC [M] .module-common.o
CC [M] drivers/gpu/drm/drm_exec.mod.o
CC [M] drivers/gpu/drm/drm_gpuvm.mod.o
CC [M] drivers/gpu/drm/drm_suballoc_helper.mod.o
CC [M] drivers/gpu/drm/drm_ttm_helper.mod.o
CC [M] drivers/gpu/drm/scheduler/gpu-sched.mod.o
CC [M] drivers/gpu/drm/xe/xe.mod.o
CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.mod.o
CC [M] sound/core/snd-hwdep.mod.o
CC [M] sound/core/snd-pcm.mod.o
CC [M] sound/pci/hda/snd-hda-codec.mod.o
CC [M] sound/pci/hda/snd-hda-codec-hdmi.mod.o
CC [M] sound/pci/hda/snd-hda-intel.mod.o
CC [M] sound/hda/snd-hda-core.mod.o
CC [M] sound/hda/snd-intel-dspcfg.mod.o
CC [M] sound/hda/snd-intel-sdw-acpi.mod.o
CC [M] net/netfilter/nf_log_syslog.mod.o
CC [M] net/netfilter/xt_mark.mod.o
CC [M] net/netfilter/xt_nat.mod.o
CC [M] net/netfilter/xt_LOG.mod.o
CC [M] net/netfilter/xt_MASQUERADE.mod.o
CC [M] net/netfilter/xt_addrtype.mod.o
CC [M] net/ipv4/netfilter/iptable_nat.mod.o
LD [M] drivers/gpu/drm/drm_gpuvm.ko
LD [M] fs/efivarfs/efivarfs.ko
LD [M] drivers/gpu/drm/drm_exec.ko
LD [M] drivers/gpu/drm/drm_suballoc_helper.ko
LD [M] drivers/gpu/drm/drm_ttm_helper.ko
LD [M] sound/core/snd-hwdep.ko
LD [M] net/netfilter/nf_log_syslog.ko
LD [M] sound/core/snd-pcm.ko
LD [M] sound/hda/snd-intel-sdw-acpi.ko
LD [M] net/netfilter/xt_nat.ko
LD [M] drivers/thermal/intel/x86_pkg_temp_thermal.ko
LD [M] net/netfilter/xt_addrtype.ko
LD [M] sound/pci/hda/snd-hda-codec-hdmi.ko
LD [M] sound/hda/snd-intel-dspcfg.ko
LD [M] net/netfilter/xt_LOG.ko
LD [M] net/netfilter/xt_MASQUERADE.ko
LD [M] sound/pci/hda/snd-hda-codec.ko
LD [M] sound/pci/hda/snd-hda-intel.ko
LD [M] sound/hda/snd-hda-core.ko
LD [M] drivers/gpu/drm/xe/xe.ko
LD [M] drivers/gpu/drm/scheduler/gpu-sched.ko
LD [M] net/netfilter/xt_mark.ko
LD [M] net/ipv4/netfilter/iptable_nat.ko
UPD include/generated/utsversion.h
CC init/version-timestamp.o
KSYMS .tmp_vmlinux0.kallsyms.S
AS .tmp_vmlinux0.kallsyms.o
LD .tmp_vmlinux1
NM .tmp_vmlinux1.syms
KSYMS .tmp_vmlinux1.kallsyms.S
AS .tmp_vmlinux1.kallsyms.o
LD .tmp_vmlinux2
NM .tmp_vmlinux2.syms
KSYMS .tmp_vmlinux2.kallsyms.S
AS .tmp_vmlinux2.kallsyms.o
LD vmlinux
NM System.map
SORTTAB vmlinux
RELOCS arch/x86/boot/compressed/vmlinux.relocs
RSTRIP vmlinux
CC arch/x86/boot/a20.o
AS arch/x86/boot/bioscall.o
CC arch/x86/boot/cmdline.o
HOSTCC arch/x86/boot/mkcpustr
AS arch/x86/boot/copy.o
CC arch/x86/boot/cpuflags.o
CC arch/x86/boot/cpucheck.o
CC arch/x86/boot/early_serial_console.o
CC arch/x86/boot/edd.o
CC arch/x86/boot/main.o
CC arch/x86/boot/memory.o
CC arch/x86/boot/pm.o
AS arch/x86/boot/pmjump.o
CC arch/x86/boot/printf.o
CC arch/x86/boot/regs.o
CC arch/x86/boot/string.o
CC arch/x86/boot/tty.o
CC arch/x86/boot/video.o
CC arch/x86/boot/video-mode.o
CC arch/x86/boot/version.o
CC arch/x86/boot/video-vga.o
CC arch/x86/boot/video-vesa.o
CC arch/x86/boot/video-bios.o
HOSTCC arch/x86/boot/tools/build
CPUSTR arch/x86/boot/cpustr.h
LDS arch/x86/boot/compressed/vmlinux.lds
CC arch/x86/boot/cpu.o
AS arch/x86/boot/compressed/kernel_info.o
AS arch/x86/boot/compressed/head_32.o
VOFFSET arch/x86/boot/compressed/../voffset.h
CC arch/x86/boot/compressed/string.o
CC arch/x86/boot/compressed/cmdline.o
CC arch/x86/boot/compressed/error.o
OBJCOPY arch/x86/boot/compressed/vmlinux.bin
HOSTCC arch/x86/boot/compressed/mkpiggy
CC arch/x86/boot/compressed/cpuflags.o
CC arch/x86/boot/compressed/early_serial_console.o
CC arch/x86/boot/compressed/kaslr.o
CC arch/x86/boot/compressed/acpi.o
CC arch/x86/boot/compressed/efi.o
GZIP arch/x86/boot/compressed/vmlinux.bin.gz
CC arch/x86/boot/compressed/misc.o
MKPIGGY arch/x86/boot/compressed/piggy.S
AS arch/x86/boot/compressed/piggy.o
LD arch/x86/boot/compressed/vmlinux
ZOFFSET arch/x86/boot/zoffset.h
OBJCOPY arch/x86/boot/vmlinux.bin
AS arch/x86/boot/header.o
LD arch/x86/boot/setup.elf
OBJCOPY arch/x86/boot/setup.bin
BUILD arch/x86/boot/bzImage
Kernel: arch/x86/boot/bzImage is ready (#1)
run-parts: executing /workspace/ci/hooks/20-kernel-doc
+ SRC_DIR=/workspace/kernel
+ cd /workspace/kernel
+ find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*'
+ xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h
date: invalid date ‘+%s’
All hooks done
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ CI.checksparse: warning for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (15 preceding siblings ...)
2024-10-22 17:30 ` ✓ CI.Hooks: " Patchwork
@ 2024-10-22 17:31 ` Patchwork
2024-10-22 17:51 ` ✓ CI.BAT: success " Patchwork
2024-10-22 21:22 ` ✗ CI.FULL: failure " Patchwork
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:31 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : warning
== Summary ==
+ trap cleanup EXIT
+ KERNEL=/kernel
+ MT=/root/linux/maintainer-tools
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools /root/linux/maintainer-tools
Cloning into '/root/linux/maintainer-tools'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ make -C /root/linux/maintainer-tools
make: Entering directory '/root/linux/maintainer-tools'
cc -O2 -g -Wextra -o remap-log remap-log.c
make: Leaving directory '/root/linux/maintainer-tools'
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ /root/linux/maintainer-tools/dim sparse --fast 26b9d5af7030484e831dd7335a08ec0c3a22f553
/root/linux/maintainer-tools/dim: line 2068: sparse: command not found
Sparse version:
Fast mode used, each commit won't be checked separately.
+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel
^ permalink raw reply [flat|nested] 31+ messages in thread* ✓ CI.BAT: success for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (16 preceding siblings ...)
2024-10-22 17:31 ` ✗ CI.checksparse: warning " Patchwork
@ 2024-10-22 17:51 ` Patchwork
2024-10-22 21:22 ` ✗ CI.FULL: failure " Patchwork
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 17:51 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 2683 bytes --]
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : success
== Summary ==
CI Bug Log - changes from xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52_BAT -> xe-pw-140323v1_BAT
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (9 -> 9)
------------------------------
No changes in participating hosts
Known issues
------------
Here are the changes found in xe-pw-140323v1_BAT that come from known issues:
### IGT changes ###
#### Possible fixes ####
* igt@kms_addfb_basic@bad-pitch-0:
- bat-adlp-7: [DMESG-WARN][1] ([Intel XE#2496]) -> [PASS][2] +31 other tests pass
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/bat-adlp-7/igt@kms_addfb_basic@bad-pitch-0.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/bat-adlp-7/igt@kms_addfb_basic@bad-pitch-0.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlp-7: [FAIL][3] ([Intel XE#1861]) -> [PASS][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/bat-adlp-7/igt@kms_frontbuffer_tracking@basic.html
* igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate:
- bat-lnl-2: [FAIL][5] ([Intel XE#2754]) -> [PASS][6]
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/bat-lnl-2/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/bat-lnl-2/igt@xe_exec_compute_mode@twice-bindexecqueue-userptr-invalidate.html
[Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
[Intel XE#2496]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2496
[Intel XE#2754]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2754
Build changes
-------------
* IGT: IGT_8081 -> IGT_8082
* Linux: xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52 -> xe-pw-140323v1
IGT_8081: 9b8c0f6da8898f760bfaa2113455eb84b68a69f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8082: c8379ec8b26f3c21bae5473706b23da78bd26ffa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52: beaeaccd284ba3b69b6dbfdc18bb89441fc99a52
xe-pw-140323v1: 140323v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/index.html
[-- Attachment #2: Type: text/html, Size: 3321 bytes --]
^ permalink raw reply [flat|nested] 31+ messages in thread* ✗ CI.FULL: failure for drm/i915/display: bunch of struct intel_display conversions
2024-10-22 15:57 [PATCH 00/11] drm/i915/display: bunch of struct intel_display conversions Jani Nikula
` (17 preceding siblings ...)
2024-10-22 17:51 ` ✓ CI.BAT: success " Patchwork
@ 2024-10-22 21:22 ` Patchwork
18 siblings, 0 replies; 31+ messages in thread
From: Patchwork @ 2024-10-22 21:22 UTC (permalink / raw)
To: Jani Nikula; +Cc: intel-xe
[-- Attachment #1: Type: text/plain, Size: 87696 bytes --]
== Series Details ==
Series: drm/i915/display: bunch of struct intel_display conversions
URL : https://patchwork.freedesktop.org/series/140323/
State : failure
== Summary ==
CI Bug Log - changes from xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52_full -> xe-pw-140323v1_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with xe-pw-140323v1_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in xe-pw-140323v1_full, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (4 -> 4)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in xe-pw-140323v1_full:
### IGT changes ###
#### Possible regressions ####
* igt@core_hotunplug@hotreplug-lateclose:
- shard-lnl: [PASS][1] -> [DMESG-WARN][2]
[1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-1/igt@core_hotunplug@hotreplug-lateclose.html
[2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@core_hotunplug@hotreplug-lateclose.html
* igt@kms_cursor_legacy@cursor-vs-flip-legacy:
- shard-bmg: [PASS][3] -> [INCOMPLETE][4]
[3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-4/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
[4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_cursor_legacy@cursor-vs-flip-legacy.html
* igt@kms_psr@psr2-cursor-render@edp-1:
- shard-lnl: [PASS][5] -> [FAIL][6] +3 other tests fail
[5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-3/igt@kms_psr@psr2-cursor-render@edp-1.html
[6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@kms_psr@psr2-cursor-render@edp-1.html
* igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
- shard-dg2-set2: [PASS][7] -> [DMESG-WARN][8] +2 other tests dmesg-warn
[7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
[8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
Known issues
------------
Here are the changes found in xe-pw-140323v1_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@intel_hwmon@hwmon-write:
- shard-bmg: [PASS][9] -> [SKIP][10] ([Intel XE#2231] / [Intel XE#2890])
[9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@intel_hwmon@hwmon-write.html
[10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@intel_hwmon@hwmon-write.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1:
- shard-adlp: [PASS][11] -> [DMESG-FAIL][12] ([Intel XE#1033] / [Intel XE#1727]) +1 other test dmesg-fail
[11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html
[12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-b-hdmi-a-1.html
* igt@kms_atomic@atomic-invalid-params:
- shard-dg2-set2: [PASS][13] -> [SKIP][14] ([Intel XE#2423] / [i915#2575]) +15 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@kms_atomic@atomic-invalid-params.html
[14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_atomic@atomic-invalid-params.html
* igt@kms_atomic_transition@modeset-transition-nonblocking:
- shard-lnl: [PASS][15] -> [FAIL][16] ([Intel XE#1701]) +1 other test fail
[15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-5/igt@kms_atomic_transition@modeset-transition-nonblocking.html
[16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@kms_atomic_transition@modeset-transition-nonblocking.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-270:
- shard-dg2-set2: NOTRUN -> [SKIP][17] ([Intel XE#316]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
- shard-bmg: NOTRUN -> [SKIP][18] ([Intel XE#2327])
[18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_big_fb@4-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-adlp: NOTRUN -> [SKIP][19] ([Intel XE#1124])
[19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-bmg: [PASS][20] -> [SKIP][21] ([Intel XE#2231])
[20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-5/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
[21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@x-tiled-16bpp-rotate-180:
- shard-lnl: [PASS][22] -> [FAIL][23] ([Intel XE#1874])
[22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-4/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
[23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@kms_big_fb@x-tiled-16bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip:
- shard-adlp: NOTRUN -> [FAIL][24] ([Intel XE#1874])
[24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip.html
* igt@kms_big_fb@y-tiled-64bpp-rotate-90:
- shard-bmg: NOTRUN -> [SKIP][25] ([Intel XE#1124]) +1 other test skip
[25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-8/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
- shard-adlp: [PASS][26] -> [FAIL][27] ([Intel XE#1204])
[26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
[27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-64bpp-rotate-180:
- shard-dg2-set2: NOTRUN -> [SKIP][28] ([Intel XE#1124]) +4 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_big_fb@yf-tiled-64bpp-rotate-180.html
* igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p:
- shard-dg2-set2: NOTRUN -> [SKIP][29] ([Intel XE#367])
[29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_bw@connected-linear-tiling-1-displays-2560x1440p.html
* igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p:
- shard-bmg: NOTRUN -> [SKIP][30] ([Intel XE#2314] / [Intel XE#2894])
[30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
- shard-dg2-set2: NOTRUN -> [SKIP][31] ([Intel XE#2191])
[31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_bw@connected-linear-tiling-3-displays-2160x1440p.html
* igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p:
- shard-lnl: NOTRUN -> [SKIP][32] ([Intel XE#1512])
[32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-8/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
- shard-adlp: NOTRUN -> [SKIP][33] ([Intel XE#2191])
[33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_bw@connected-linear-tiling-4-displays-1920x1080p.html
* igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs:
- shard-dg2-set2: NOTRUN -> [SKIP][34] ([Intel XE#2907])
[34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-434/igt@kms_ccs@crc-sprite-planes-basic-4-tiled-bmg-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs:
- shard-bmg: NOTRUN -> [SKIP][35] ([Intel XE#2887]) +2 other tests skip
[35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs.html
* igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6:
- shard-dg2-set2: NOTRUN -> [SKIP][36] ([Intel XE#787]) +34 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_ccs@missing-ccs-buffer-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-6.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][37] ([Intel XE#787]) +2 other tests skip
[37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-1.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-dp-4:
- shard-dg2-set2: NOTRUN -> [SKIP][38] ([Intel XE#455] / [Intel XE#787]) +8 other tests skip
[38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-dp-4.html
* igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1:
- shard-adlp: NOTRUN -> [SKIP][39] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
[39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_ccs@random-ccs-data-y-tiled-gen12-rc-ccs@pipe-d-hdmi-a-1.html
* igt@kms_chamelium_edid@dp-edid-change-during-suspend:
- shard-lnl: NOTRUN -> [SKIP][40] ([Intel XE#373]) +1 other test skip
[40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-4/igt@kms_chamelium_edid@dp-edid-change-during-suspend.html
* igt@kms_chamelium_frames@hdmi-crc-planes-random:
- shard-dg2-set2: NOTRUN -> [SKIP][41] ([Intel XE#2423] / [i915#2575])
[41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_chamelium_frames@hdmi-crc-planes-random.html
* igt@kms_chamelium_hpd@hdmi-hpd-after-suspend:
- shard-adlp: NOTRUN -> [SKIP][42] ([Intel XE#373]) +2 other tests skip
[42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_chamelium_hpd@hdmi-hpd-after-suspend.html
* igt@kms_chamelium_hpd@vga-hpd:
- shard-dg2-set2: NOTRUN -> [SKIP][43] ([Intel XE#373]) +1 other test skip
[43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_chamelium_hpd@vga-hpd.html
* igt@kms_color@ctm-0-50@pipe-b-edp-1:
- shard-lnl: [PASS][44] -> [DMESG-WARN][45] ([Intel XE#2929]) +1 other test dmesg-warn
[44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-2/igt@kms_color@ctm-0-50@pipe-b-edp-1.html
[45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@kms_color@ctm-0-50@pipe-b-edp-1.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-bmg: NOTRUN -> [SKIP][46] ([Intel XE#2390])
[46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-adlp: NOTRUN -> [SKIP][47] ([Intel XE#307])
[47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-6/igt@kms_content_protection@dp-mst-lic-type-1.html
- shard-dg2-set2: NOTRUN -> [SKIP][48] ([Intel XE#307])
[48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2-set2: NOTRUN -> [SKIP][49] ([Intel XE#323])
[49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@torture-bo@pipe-a:
- shard-dg2-set2: [PASS][50] -> [DMESG-WARN][51] ([Intel XE#2932]) +1 other test dmesg-warn
[50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_cursor_legacy@torture-bo@pipe-a.html
[51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_cursor_legacy@torture-bo@pipe-a.html
* igt@kms_feature_discovery@psr2:
- shard-adlp: NOTRUN -> [SKIP][52] ([Intel XE#1135])
[52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-1/igt@kms_feature_discovery@psr2.html
* igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset:
- shard-adlp: NOTRUN -> [SKIP][53] ([Intel XE#310])
[53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_flip@2x-flip-vs-dpms-off-vs-modeset.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3:
- shard-bmg: [PASS][54] -> [FAIL][55] ([Intel XE#301]) +1 other test fail
[54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
[55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bd-dp2-hdmi-a3.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][56] -> [FAIL][57] ([Intel XE#301]) +6 other tests fail
[56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
[57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@cd-hdmi-a6-dp4.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@bd-hdmi-a6-dp4:
- shard-dg2-set2: [PASS][58] -> [INCOMPLETE][59] ([Intel XE#1195]) +1 other test incomplete
[58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@bd-hdmi-a6-dp4.html
[59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-434/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible@bd-hdmi-a6-dp4.html
* igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
- shard-lnl: [PASS][60] -> [FAIL][61] ([Intel XE#3149] / [Intel XE#886])
[60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-7/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
[61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-4/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank@b-edp1:
- shard-lnl: [PASS][62] -> [FAIL][63] ([Intel XE#301]) +1 other test fail
[62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
[63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-7/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html
* igt@kms_flip@nonexisting-fb:
- shard-bmg: [PASS][64] -> [SKIP][65] ([Intel XE#3007]) +14 other tests skip
[64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_flip@nonexisting-fb.html
[65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_flip@nonexisting-fb.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1:
- shard-lnl: [PASS][66] -> [FAIL][67] ([Intel XE#886]) +7 other tests fail
[66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-1/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
[67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-6/igt@kms_flip@plain-flip-fb-recreate-interruptible@a-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode:
- shard-adlp: [PASS][68] -> [DMESG-FAIL][69] ([Intel XE#3194]) +1 other test dmesg-fail
[68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-6/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
[69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-4/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
- shard-dg2-set2: NOTRUN -> [SKIP][70] ([Intel XE#455]) +4 other tests skip
[70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x:
- shard-adlp: [PASS][71] -> [FAIL][72] ([Intel XE#1874]) +2 other tests fail
[71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
[72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-x.html
* igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt:
- shard-lnl: NOTRUN -> [SKIP][73] ([Intel XE#656])
[73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-8/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-spr-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render:
- shard-dg2-set2: NOTRUN -> [SKIP][74] ([Intel XE#651]) +14 other tests skip
[74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt:
- shard-bmg: NOTRUN -> [SKIP][75] ([Intel XE#2311]) +6 other tests skip
[75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-scndscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-dg2-set2: [PASS][76] -> [SKIP][77] ([Intel XE#2890]) +2 other tests skip
[76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
[77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render:
- shard-bmg: NOTRUN -> [FAIL][78] ([Intel XE#2333]) +1 other test fail
[78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary:
- shard-adlp: [PASS][79] -> [FAIL][80] ([Intel XE#1861])
[79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
[80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_frontbuffer_tracking@fbc-shrfb-scaledprimary.html
* igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt:
- shard-adlp: NOTRUN -> [SKIP][81] ([Intel XE#651]) +1 other test skip
[81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-indfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render:
- shard-adlp: NOTRUN -> [SKIP][82] ([Intel XE#656]) +2 other tests skip
[82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-9/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
- shard-bmg: NOTRUN -> [SKIP][83] ([Intel XE#2313]) +5 other tests skip
[83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc:
- shard-dg2-set2: NOTRUN -> [SKIP][84] ([Intel XE#653]) +11 other tests skip
[84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-pri-shrfb-draw-mmap-wc.html
* igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt:
- shard-adlp: NOTRUN -> [SKIP][85] ([Intel XE#653])
[85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_frontbuffer_tracking@psr-rgb101010-draw-blt.html
* igt@kms_hdr@static-toggle-dpms:
- shard-lnl: NOTRUN -> [SKIP][86] ([Intel XE#1503] / [Intel XE#599])
[86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-7/igt@kms_hdr@static-toggle-dpms.html
- shard-adlp: NOTRUN -> [SKIP][87] ([Intel XE#455])
[87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_joiner@invalid-modeset-ultra-joiner:
- shard-dg2-set2: NOTRUN -> [SKIP][88] ([Intel XE#2927])
[88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-434/igt@kms_joiner@invalid-modeset-ultra-joiner.html
- shard-bmg: NOTRUN -> [SKIP][89] ([Intel XE#2927])
[89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_joiner@invalid-modeset-ultra-joiner.html
* igt@kms_pm_dc@dc5-psr:
- shard-bmg: NOTRUN -> [SKIP][90] ([Intel XE#2392])
[90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_pm_dc@dc5-psr.html
- shard-dg2-set2: NOTRUN -> [SKIP][91] ([Intel XE#1129])
[91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_pm_dc@dc5-psr.html
* igt@kms_pm_rpm@cursor-dpms:
- shard-adlp: [PASS][92] -> [DMESG-WARN][93] ([Intel XE#1033] / [Intel XE#1727])
[92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_pm_rpm@cursor-dpms.html
[93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-6/igt@kms_pm_rpm@cursor-dpms.html
* igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][94] ([Intel XE#2890]) +1 other test skip
[94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area:
- shard-dg2-set2: NOTRUN -> [SKIP][95] ([Intel XE#1489]) +1 other test skip
[95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
- shard-bmg: NOTRUN -> [SKIP][96] ([Intel XE#1489])
[96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-8/igt@kms_psr2_sf@pr-overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-dg2-set2: NOTRUN -> [SKIP][97] ([Intel XE#1122])
[97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-464/igt@kms_psr2_su@page_flip-nv12.html
- shard-bmg: NOTRUN -> [SKIP][98] ([Intel XE#2387])
[98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-1/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@pr-sprite-blt:
- shard-dg2-set2: NOTRUN -> [SKIP][99] ([Intel XE#2850] / [Intel XE#929]) +5 other tests skip
[99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@kms_psr@pr-sprite-blt.html
* igt@kms_psr@psr-cursor-blt:
- shard-bmg: NOTRUN -> [SKIP][100] ([Intel XE#2234] / [Intel XE#2850]) +2 other tests skip
[100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-1/igt@kms_psr@psr-cursor-blt.html
* igt@kms_psr@psr2-cursor-plane-onoff:
- shard-lnl: [PASS][101] -> [FAIL][102] ([Intel XE#2948]) +3 other tests fail
[101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-2/igt@kms_psr@psr2-cursor-plane-onoff.html
[102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-8/igt@kms_psr@psr2-cursor-plane-onoff.html
* igt@kms_psr_stress_test@invalidate-primary-flip-overlay:
- shard-bmg: NOTRUN -> [SKIP][103] ([Intel XE#2414])
[103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
- shard-dg2-set2: NOTRUN -> [SKIP][104] ([Intel XE#2939])
[104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html
* igt@kms_rotation_crc@bad-tiling:
- shard-dg2-set2: NOTRUN -> [SKIP][105] ([Intel XE#327])
[105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_rotation_crc@bad-tiling.html
* igt@kms_vrr@flip-basic-fastset:
- shard-lnl: [PASS][106] -> [FAIL][107] ([Intel XE#2443]) +1 other test fail
[106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-5/igt@kms_vrr@flip-basic-fastset.html
[107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-4/igt@kms_vrr@flip-basic-fastset.html
* igt@xe_copy_basic@mem-set-linear-0xfffe:
- shard-dg2-set2: NOTRUN -> [SKIP][108] ([Intel XE#1126]) +1 other test skip
[108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_copy_basic@mem-set-linear-0xfffe.html
- shard-adlp: NOTRUN -> [SKIP][109] ([Intel XE#1126])
[109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-4/igt@xe_copy_basic@mem-set-linear-0xfffe.html
* igt@xe_create@create-invalid-size:
- shard-adlp: [PASS][110] -> [TIMEOUT][111] ([Intel XE#1033] / [Intel XE#1727]) +2 other tests timeout
[110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-1/igt@xe_create@create-invalid-size.html
[111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-6/igt@xe_create@create-invalid-size.html
* igt@xe_eudebug@basic-vm-bind-ufence:
- shard-bmg: NOTRUN -> [SKIP][112] ([Intel XE#2905])
[112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@xe_eudebug@basic-vm-bind-ufence.html
* igt@xe_eudebug@multigpu-basic-client-many:
- shard-dg2-set2: NOTRUN -> [SKIP][113] ([Intel XE#2905]) +1 other test skip
[113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-464/igt@xe_eudebug@multigpu-basic-client-many.html
* igt@xe_evict@evict-beng-cm-threads-large:
- shard-adlp: NOTRUN -> [SKIP][114] ([Intel XE#261] / [Intel XE#688]) +1 other test skip
[114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-4/igt@xe_evict@evict-beng-cm-threads-large.html
* igt@xe_evict@evict-mixed-many-threads-large:
- shard-bmg: NOTRUN -> [INCOMPLETE][115] ([Intel XE#1473])
[115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@xe_evict@evict-mixed-many-threads-large.html
- shard-dg2-set2: NOTRUN -> [INCOMPLETE][116] ([Intel XE#1195] / [Intel XE#1473])
[116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_evict@evict-mixed-many-threads-large.html
* igt@xe_evict@evict-mixed-threads-large:
- shard-bmg: [PASS][117] -> [INCOMPLETE][118] ([Intel XE#1473])
[117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@xe_evict@evict-mixed-threads-large.html
[118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@xe_evict@evict-mixed-threads-large.html
* igt@xe_exec_basic@many-bindexecqueue-rebind:
- shard-bmg: [PASS][119] -> [SKIP][120] ([Intel XE#1130]) +21 other tests skip
[119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@xe_exec_basic@many-bindexecqueue-rebind.html
[120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_exec_basic@many-bindexecqueue-rebind.html
* igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind:
- shard-lnl: NOTRUN -> [SKIP][121] ([Intel XE#1392])
[121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-rebind.html
* igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap:
- shard-adlp: NOTRUN -> [SKIP][122] ([Intel XE#1392])
[122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@xe_exec_basic@multigpu-no-exec-null-defer-mmap.html
* igt@xe_exec_basic@multigpu-once-basic-defer-bind:
- shard-bmg: NOTRUN -> [SKIP][123] ([Intel XE#2322]) +1 other test skip
[123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@xe_exec_basic@multigpu-once-basic-defer-bind.html
* igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate:
- shard-lnl: [PASS][124] -> [DMESG-WARN][125] ([Intel XE#2687])
[124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-1/igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate.html
[125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-5/igt@xe_exec_compute_mode@many-bindexecqueue-userptr-invalidate.html
* igt@xe_exec_compute_mode@many-execqueues-basic:
- shard-dg2-set2: [PASS][126] -> [SKIP][127] ([Intel XE#1130]) +18 other tests skip
[126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@xe_exec_compute_mode@many-execqueues-basic.html
[127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_exec_compute_mode@many-execqueues-basic.html
* igt@xe_exec_compute_mode@twice-userptr-invalidate-race:
- shard-lnl: [PASS][128] -> [FAIL][129] ([Intel XE#1630])
[128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-2/igt@xe_exec_compute_mode@twice-userptr-invalidate-race.html
[129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@xe_exec_compute_mode@twice-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@once-userptr-invalidate-race:
- shard-dg2-set2: NOTRUN -> [SKIP][130] ([Intel XE#288]) +8 other tests skip
[130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@xe_exec_fault_mode@once-userptr-invalidate-race.html
* igt@xe_exec_fault_mode@twice-userptr:
- shard-adlp: NOTRUN -> [SKIP][131] ([Intel XE#288]) +1 other test skip
[131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@xe_exec_fault_mode@twice-userptr.html
* igt@xe_gt_freq@freq_reset_multiple:
- shard-lnl: [PASS][132] -> [DMESG-WARN][133] ([Intel XE#3184])
[132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-8/igt@xe_gt_freq@freq_reset_multiple.html
[133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@xe_gt_freq@freq_reset_multiple.html
* igt@xe_module_load@many-reload:
- shard-lnl: [PASS][134] -> [DMESG-WARN][135] ([Intel XE#2910])
[134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-8/igt@xe_module_load@many-reload.html
[135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-5/igt@xe_module_load@many-reload.html
* igt@xe_oa@whitelisted-registers-userspace-config:
- shard-dg2-set2: NOTRUN -> [SKIP][136] ([Intel XE#2541]) +1 other test skip
[136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_oa@whitelisted-registers-userspace-config.html
* igt@xe_pm@d3cold-multiple-execs:
- shard-dg2-set2: NOTRUN -> [SKIP][137] ([Intel XE#2284] / [Intel XE#366])
[137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@xe_pm@d3cold-multiple-execs.html
* igt@xe_pm@s4-d3hot-basic-exec:
- shard-adlp: [PASS][138] -> [ABORT][139] ([Intel XE#1358] / [Intel XE#1607])
[138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-6/igt@xe_pm@s4-d3hot-basic-exec.html
[139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-9/igt@xe_pm@s4-d3hot-basic-exec.html
* igt@xe_pm@vram-d3cold-threshold:
- shard-dg2-set2: NOTRUN -> [SKIP][140] ([Intel XE#579])
[140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-434/igt@xe_pm@vram-d3cold-threshold.html
* igt@xe_query@multigpu-query-mem-usage:
- shard-dg2-set2: NOTRUN -> [SKIP][141] ([Intel XE#944])
[141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@xe_query@multigpu-query-mem-usage.html
* igt@xe_vm@large-split-misaligned-binds-4194304:
- shard-dg2-set2: NOTRUN -> [SKIP][142] ([Intel XE#1130])
[142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_vm@large-split-misaligned-binds-4194304.html
#### Possible fixes ####
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1:
- shard-adlp: [FAIL][143] ([Intel XE#827]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
[144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-hdmi-a-1.html
* igt@kms_async_flips@async-flip-with-page-flip-events:
- shard-adlp: [DMESG-WARN][145] ([Intel XE#3194]) -> [PASS][146] +3 other tests pass
[145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-3/igt@kms_async_flips@async-flip-with-page-flip-events.html
[146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-9/igt@kms_async_flips@async-flip-with-page-flip-events.html
* igt@kms_atomic_transition@plane-all-modeset-transition:
- shard-adlp: [INCOMPLETE][147] -> [PASS][148] +1 other test pass
[147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-3/igt@kms_atomic_transition@plane-all-modeset-transition.html
[148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_atomic_transition@plane-all-modeset-transition.html
* igt@kms_big_fb@linear-64bpp-rotate-0:
- shard-dg2-set2: [DMESG-WARN][149] ([Intel XE#877]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@kms_big_fb@linear-64bpp-rotate-0.html
[150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_big_fb@linear-64bpp-rotate-0.html
* igt@kms_big_fb@x-tiled-64bpp-rotate-180:
- shard-bmg: [SKIP][151] ([Intel XE#2231] / [Intel XE#2890]) -> [PASS][152] +1 other test pass
[151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
- shard-dg2-set2: [SKIP][153] ([Intel XE#2890]) -> [PASS][154] +1 other test pass
[153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
[154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_big_fb@x-tiled-64bpp-rotate-180.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [DMESG-FAIL][155] -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-adlp: [FAIL][157] ([Intel XE#1204]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-adlp: [FAIL][159] ([Intel XE#1231] / [Intel XE#1242]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-4/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_color@deep-color:
- shard-lnl: [DMESG-WARN][161] ([Intel XE#2929]) -> [PASS][162]
[161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-6/igt@kms_color@deep-color.html
[162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-6/igt@kms_color@deep-color.html
* igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy:
- shard-dg2-set2: [SKIP][163] ([Intel XE#2423] / [i915#2575]) -> [PASS][164] +2 other tests pass
[163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
[164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_cursor_legacy@flip-vs-cursor-crc-legacy.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3:
- shard-bmg: [FAIL][165] ([Intel XE#301]) -> [PASS][166] +1 other test pass
[165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
[166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible@bc-dp2-hdmi-a3.html
* igt@kms_flip@2x-plain-flip-fb-recreate:
- shard-dg2-set2: [INCOMPLETE][167] ([Intel XE#1195]) -> [PASS][168] +1 other test pass
[167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@kms_flip@2x-plain-flip-fb-recreate.html
[168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@kms_flip@2x-plain-flip-fb-recreate.html
* igt@kms_flip@blocking-wf_vblank:
- shard-dg2-set2: [FAIL][169] ([Intel XE#2882]) -> [PASS][170]
[169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@kms_flip@blocking-wf_vblank.html
[170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@kms_flip@blocking-wf_vblank.html
* igt@kms_flip@blocking-wf_vblank@a-hdmi-a6:
- shard-dg2-set2: [FAIL][171] -> [PASS][172]
[171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@kms_flip@blocking-wf_vblank@a-hdmi-a6.html
[172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@kms_flip@blocking-wf_vblank@a-hdmi-a6.html
* igt@kms_flip@flip-vs-absolute-wf_vblank:
- shard-lnl: [FAIL][173] ([Intel XE#886]) -> [PASS][174] +5 other tests pass
[173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-8/igt@kms_flip@flip-vs-absolute-wf_vblank.html
[174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-lnl: [FAIL][175] ([Intel XE#301]) -> [PASS][176] +1 other test pass
[175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-6/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-5/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6:
- shard-dg2-set2: [FAIL][177] ([Intel XE#301]) -> [PASS][178] +1 other test pass
[177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
[178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank@b-hdmi-a6.html
* igt@kms_flip@flip-vs-suspend:
- shard-dg2-set2: [INCOMPLETE][179] ([Intel XE#1195] / [Intel XE#2049] / [Intel XE#2597]) -> [PASS][180]
[179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_flip@flip-vs-suspend.html
[180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_flip@flip-vs-suspend.html
* igt@kms_flip@flip-vs-suspend@d-dp4:
- shard-dg2-set2: [INCOMPLETE][181] ([Intel XE#1195] / [Intel XE#2049]) -> [PASS][182]
[181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_flip@flip-vs-suspend@d-dp4.html
[182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_flip@flip-vs-suspend@d-dp4.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode:
- shard-adlp: [DMESG-FAIL][183] ([Intel XE#3194]) -> [PASS][184] +5 other tests pass
[183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
[184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-3/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling@pipe-a-valid-mode.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-a-edp-1-4-rc-ccs-to-linear:
- shard-lnl: [FAIL][185] ([Intel XE#1491]) -> [PASS][186] +2 other tests pass
[185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-2/igt@kms_flip_tiling@flip-change-tiling@pipe-a-edp-1-4-rc-ccs-to-linear.html
[186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-2/igt@kms_flip_tiling@flip-change-tiling@pipe-a-edp-1-4-rc-ccs-to-linear.html
* igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x:
- shard-adlp: [FAIL][187] ([Intel XE#1874]) -> [PASS][188] +5 other tests pass
[187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
[188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-y-to-x.html
* igt@kms_force_connector_basic@force-edid:
- shard-adlp: [DMESG-WARN][189] -> [PASS][190] +1 other test pass
[189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-9/igt@kms_force_connector_basic@force-edid.html
[190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-1/igt@kms_force_connector_basic@force-edid.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff:
- shard-lnl: [DMESG-WARN][191] -> [PASS][192] +2 other tests pass
[191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
[192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-onoff.html
* igt@kms_plane@pixel-format-source-clamping:
- shard-bmg: [DMESG-WARN][193] ([Intel XE#2566] / [Intel XE#877]) -> [PASS][194]
[193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-4/igt@kms_plane@pixel-format-source-clamping.html
[194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@kms_plane@pixel-format-source-clamping.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-3:
- shard-bmg: [DMESG-WARN][195] ([Intel XE#877]) -> [PASS][196]
[195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-4/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-3.html
[196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@kms_plane@pixel-format-source-clamping@pipe-b-plane-3.html
* igt@kms_plane_lowres@tiling-none:
- shard-bmg: [SKIP][197] ([Intel XE#3007]) -> [PASS][198] +2 other tests pass
[197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_plane_lowres@tiling-none.html
[198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-2/igt@kms_plane_lowres@tiling-none.html
* igt@kms_rotation_crc@primary-rotation-180:
- shard-lnl: [DMESG-WARN][199] ([Intel XE#2055]) -> [PASS][200]
[199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-7/igt@kms_rotation_crc@primary-rotation-180.html
[200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-6/igt@kms_rotation_crc@primary-rotation-180.html
* igt@kms_universal_plane@cursor-fb-leak:
- shard-lnl: [FAIL][201] ([Intel XE#899]) -> [PASS][202] +1 other test pass
[201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-6/igt@kms_universal_plane@cursor-fb-leak.html
[202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@kms_universal_plane@cursor-fb-leak.html
* igt@kms_vrr@cmrr@pipe-a-edp-1:
- shard-lnl: [FAIL][203] -> [PASS][204] +1 other test pass
[203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
[204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@kms_vrr@cmrr@pipe-a-edp-1.html
* igt@kms_vrr@flip-basic:
- shard-lnl: [FAIL][205] ([Intel XE#2443]) -> [PASS][206] +1 other test pass
[205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-4/igt@kms_vrr@flip-basic.html
[206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-2/igt@kms_vrr@flip-basic.html
* igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue:
- shard-lnl: [FAIL][207] ([Intel XE#2667]) -> [PASS][208]
[207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-3/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
[208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-1/igt@xe_drm_fdinfo@utilization-single-full-load-destroy-queue.html
* igt@xe_evict@evict-beng-mixed-many-threads-small:
- shard-dg2-set2: [TIMEOUT][209] ([Intel XE#1473] / [Intel XE#402]) -> [PASS][210]
[209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@xe_evict@evict-beng-mixed-many-threads-small.html
[210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@xe_evict@evict-beng-mixed-many-threads-small.html
* igt@xe_evict@evict-small-external-cm:
- shard-bmg: [SKIP][211] ([Intel XE#1130]) -> [PASS][212] +1 other test pass
[211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@xe_evict@evict-small-external-cm.html
[212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@xe_evict@evict-small-external-cm.html
* igt@xe_evict@evict-threads-large:
- shard-dg2-set2: [TIMEOUT][213] ([Intel XE#1473]) -> [PASS][214]
[213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@xe_evict@evict-threads-large.html
[214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-464/igt@xe_evict@evict-threads-large.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-bmg: [ABORT][215] -> [PASS][216]
[215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@xe_exec_reset@parallel-gt-reset.html
[216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-7/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_gpgpu_fill@basic:
- shard-dg2-set2: [SKIP][217] ([Intel XE#1130]) -> [PASS][218] +1 other test pass
[217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@xe_gpgpu_fill@basic.html
[218]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@xe_gpgpu_fill@basic.html
* igt@xe_module_load@many-reload:
- shard-bmg: [FAIL][219] ([Intel XE#2136]) -> [PASS][220]
[219]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-4/igt@xe_module_load@many-reload.html
[220]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-8/igt@xe_module_load@many-reload.html
- shard-dg2-set2: [FAIL][221] ([Intel XE#2136]) -> [PASS][222]
[221]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@xe_module_load@many-reload.html
[222]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-436/igt@xe_module_load@many-reload.html
* igt@xe_oa@mmio-triggered-reports:
- shard-bmg: [FAIL][223] ([Intel XE#2249]) -> [PASS][224] +1 other test pass
[223]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-4/igt@xe_oa@mmio-triggered-reports.html
[224]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-8/igt@xe_oa@mmio-triggered-reports.html
- shard-lnl: [FAIL][225] ([Intel XE#2249]) -> [PASS][226]
[225]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-3/igt@xe_oa@mmio-triggered-reports.html
[226]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-4/igt@xe_oa@mmio-triggered-reports.html
* igt@xe_pm@s4-mocs:
- shard-adlp: [ABORT][227] ([Intel XE#1794]) -> [PASS][228]
[227]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-9/igt@xe_pm@s4-mocs.html
[228]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-6/igt@xe_pm@s4-mocs.html
* igt@xe_pm@s4-multiple-execs:
- shard-adlp: [ABORT][229] ([Intel XE#1358] / [Intel XE#1607] / [Intel XE#1794]) -> [PASS][230]
[229]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-9/igt@xe_pm@s4-multiple-execs.html
[230]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@xe_pm@s4-multiple-execs.html
- shard-lnl: [ABORT][231] ([Intel XE#1358] / [Intel XE#1607] / [Intel XE#1794]) -> [PASS][232]
[231]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-lnl-2/igt@xe_pm@s4-multiple-execs.html
[232]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-lnl-3/igt@xe_pm@s4-multiple-execs.html
#### Warnings ####
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-adlp: [FAIL][233] ([Intel XE#827]) -> [DMESG-FAIL][234] ([Intel XE#1033] / [Intel XE#1727])
[233]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-2/igt@kms_async_flips@alternate-sync-async-flip.html
[234]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-8/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@y-tiled-32bpp-rotate-180:
- shard-bmg: [SKIP][235] ([Intel XE#1124]) -> [SKIP][236] ([Intel XE#2231])
[235]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
[236]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
- shard-dg2-set2: [SKIP][237] ([Intel XE#1124]) -> [SKIP][238] ([Intel XE#2890])
[237]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
[238]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_big_fb@y-tiled-32bpp-rotate-180.html
* igt@kms_big_fb@y-tiled-addfb:
- shard-bmg: [SKIP][239] ([Intel XE#2328]) -> [SKIP][240] ([Intel XE#2231])
[239]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_big_fb@y-tiled-addfb.html
[240]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_big_fb@y-tiled-addfb.html
- shard-dg2-set2: [SKIP][241] ([Intel XE#619]) -> [SKIP][242] ([Intel XE#2351] / [Intel XE#2890])
[241]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_big_fb@y-tiled-addfb.html
[242]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_big_fb@y-tiled-addfb.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-adlp: [FAIL][243] ([Intel XE#1231] / [Intel XE#1242]) -> [DMESG-FAIL][244] ([Intel XE#3194]) +2 other tests dmesg-fail
[243]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[244]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-2/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_bw@linear-tiling-2-displays-1920x1080p:
- shard-bmg: [SKIP][245] ([Intel XE#3007]) -> [SKIP][246] ([Intel XE#367])
[245]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
[246]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-1/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
- shard-dg2-set2: [SKIP][247] ([Intel XE#2423] / [i915#2575]) -> [SKIP][248] ([Intel XE#367])
[247]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
[248]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-464/igt@kms_bw@linear-tiling-2-displays-1920x1080p.html
* igt@kms_bw@linear-tiling-4-displays-3840x2160p:
- shard-bmg: [SKIP][249] ([Intel XE#367]) -> [SKIP][250] ([Intel XE#3007])
[249]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-8/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
[250]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
- shard-dg2-set2: [SKIP][251] ([Intel XE#367]) -> [SKIP][252] ([Intel XE#2423] / [i915#2575])
[251]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
[252]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_bw@linear-tiling-4-displays-3840x2160p.html
* igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs:
- shard-bmg: [SKIP][253] ([Intel XE#2887]) -> [SKIP][254] ([Intel XE#2231] / [Intel XE#2890])
[253]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
[254]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
- shard-dg2-set2: [SKIP][255] ([Intel XE#455] / [Intel XE#787]) -> [SKIP][256] ([Intel XE#2351] / [Intel XE#2890])
[255]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
[256]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_ccs@missing-ccs-buffer-yf-tiled-ccs.html
* igt@kms_ccs@random-ccs-data-y-tiled-ccs:
- shard-dg2-set2: [SKIP][257] ([Intel XE#2890]) -> [SKIP][258] ([Intel XE#455] / [Intel XE#787])
[257]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
[258]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
- shard-bmg: [SKIP][259] ([Intel XE#2231]) -> [SKIP][260] ([Intel XE#2887])
[259]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
[260]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_ccs@random-ccs-data-y-tiled-ccs.html
* igt@kms_chamelium_edid@dp-edid-change-during-hibernate:
- shard-bmg: [SKIP][261] ([Intel XE#2252]) -> [SKIP][262] ([Intel XE#3007]) +1 other test skip
[261]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
[262]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
- shard-dg2-set2: [SKIP][263] ([Intel XE#373]) -> [SKIP][264] ([Intel XE#2423] / [i915#2575])
[263]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-435/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
[264]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_chamelium_edid@dp-edid-change-during-hibernate.html
* igt@kms_content_protection@lic-type-1:
- shard-dg2-set2: [SKIP][265] ([Intel XE#455]) -> [SKIP][266] ([Intel XE#2423] / [i915#2575])
[265]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@kms_content_protection@lic-type-1.html
[266]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_content_protection@lic-type-1.html
- shard-bmg: [SKIP][267] ([Intel XE#2341]) -> [SKIP][268] ([Intel XE#3007])
[267]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@kms_content_protection@lic-type-1.html
[268]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_content_protection@lic-type-1.html
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size:
- shard-bmg: [DMESG-WARN][269] ([Intel XE#2791]) -> [DMESG-WARN][270] ([Intel XE#2791] / [Intel XE#877])
[269]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
[270]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions-varying-size.html
* igt@kms_dsc@dsc-with-output-formats-with-bpc:
- shard-dg2-set2: [SKIP][271] ([Intel XE#455]) -> [SKIP][272] ([Intel XE#2890])
[271]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[272]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
- shard-bmg: [SKIP][273] ([Intel XE#2244]) -> [SKIP][274] ([Intel XE#2231] / [Intel XE#2890])
[273]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
[274]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_dsc@dsc-with-output-formats-with-bpc.html
* igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render:
- shard-bmg: [SKIP][275] ([Intel XE#2311]) -> [SKIP][276] ([Intel XE#2231]) +1 other test skip
[275]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-8/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
[276]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
- shard-dg2-set2: [SKIP][277] ([Intel XE#651]) -> [SKIP][278] ([Intel XE#2890]) +2 other tests skip
[277]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
[278]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_frontbuffer_tracking@drrs-rgb565-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render:
- shard-adlp: [FAIL][279] ([Intel XE#1861]) -> [TIMEOUT][280] ([Intel XE#1033] / [Intel XE#1727])
[279]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-adlp-9/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
[280]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-adlp-6/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render:
- shard-bmg: [FAIL][281] ([Intel XE#2333]) -> [SKIP][282] ([Intel XE#2231])
[281]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
[282]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-render.html
* igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt:
- shard-bmg: [SKIP][283] ([Intel XE#2311]) -> [SKIP][284] ([Intel XE#2231] / [Intel XE#2890])
[283]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt.html
[284]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-bmg: [SKIP][285] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][286] ([Intel XE#2313])
[285]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html
[286]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt:
- shard-dg2-set2: [SKIP][287] ([Intel XE#653]) -> [SKIP][288] ([Intel XE#2890]) +1 other test skip
[287]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-464/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
[288]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-shrfb-draw-blt.html
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][289] ([Intel XE#2313]) -> [SKIP][290] ([Intel XE#2231]) +1 other test skip
[289]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-5/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
[290]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
- shard-bmg: [SKIP][291] ([Intel XE#2231]) -> [SKIP][292] ([Intel XE#2313])
[291]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[292]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
- shard-dg2-set2: [SKIP][293] ([Intel XE#2890]) -> [SKIP][294] ([Intel XE#653]) +1 other test skip
[293]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
[294]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt:
- shard-dg2-set2: [SKIP][295] ([Intel XE#653]) -> [SKIP][296] ([Intel XE#2351] / [Intel XE#2890])
[295]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-464/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
[296]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_frontbuffer_tracking@psr-2p-primscrn-shrfb-msflip-blt.html
* igt@kms_frontbuffer_tracking@psr-rgb565-draw-render:
- shard-bmg: [SKIP][297] ([Intel XE#2313]) -> [SKIP][298] ([Intel XE#2231] / [Intel XE#2890]) +1 other test skip
[297]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
[298]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_frontbuffer_tracking@psr-rgb565-draw-render.html
* igt@kms_getfb@getfb2-accept-ccs:
- shard-bmg: [SKIP][299] ([Intel XE#2340]) -> [SKIP][300] ([Intel XE#3007])
[299]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-8/igt@kms_getfb@getfb2-accept-ccs.html
[300]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_getfb@getfb2-accept-ccs.html
* igt@kms_joiner@invalid-modeset-big-joiner:
- shard-bmg: [SKIP][301] ([Intel XE#346]) -> [SKIP][302] ([Intel XE#2231])
[301]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@kms_joiner@invalid-modeset-big-joiner.html
[302]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_joiner@invalid-modeset-big-joiner.html
- shard-dg2-set2: [SKIP][303] ([Intel XE#346]) -> [SKIP][304] ([Intel XE#2890])
[303]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@kms_joiner@invalid-modeset-big-joiner.html
[304]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_joiner@invalid-modeset-big-joiner.html
* igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf:
- shard-bmg: [SKIP][305] ([Intel XE#1489]) -> [SKIP][306] ([Intel XE#2231]) +1 other test skip
[305]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
[306]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
- shard-dg2-set2: [SKIP][307] ([Intel XE#1489]) -> [SKIP][308] ([Intel XE#2890])
[307]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-436/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
[308]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_psr2_sf@psr2-overlay-plane-update-continuous-sf.html
* igt@kms_psr@fbc-pr-primary-render:
- shard-bmg: [SKIP][309] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][310] ([Intel XE#2231])
[309]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@kms_psr@fbc-pr-primary-render.html
[310]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_psr@fbc-pr-primary-render.html
- shard-dg2-set2: [SKIP][311] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][312] ([Intel XE#2351] / [Intel XE#2890])
[311]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@kms_psr@fbc-pr-primary-render.html
[312]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_psr@fbc-pr-primary-render.html
* igt@kms_psr@fbc-psr-sprite-plane-move:
- shard-dg2-set2: [SKIP][313] ([Intel XE#2351] / [Intel XE#2890]) -> [SKIP][314] ([Intel XE#2850] / [Intel XE#929])
[313]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_psr@fbc-psr-sprite-plane-move.html
[314]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-435/igt@kms_psr@fbc-psr-sprite-plane-move.html
- shard-bmg: [SKIP][315] ([Intel XE#2231] / [Intel XE#2890]) -> [SKIP][316] ([Intel XE#2234] / [Intel XE#2850])
[315]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_psr@fbc-psr-sprite-plane-move.html
[316]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_psr@fbc-psr-sprite-plane-move.html
* igt@kms_psr@pr-no-drrs:
- shard-bmg: [SKIP][317] ([Intel XE#2234] / [Intel XE#2850]) -> [SKIP][318] ([Intel XE#2231] / [Intel XE#2890])
[317]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-8/igt@kms_psr@pr-no-drrs.html
[318]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@kms_psr@pr-no-drrs.html
- shard-dg2-set2: [SKIP][319] ([Intel XE#2850] / [Intel XE#929]) -> [SKIP][320] ([Intel XE#2890])
[319]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_psr@pr-no-drrs.html
[320]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@kms_psr@pr-no-drrs.html
* igt@kms_scaling_modes@scaling-mode-full-aspect:
- shard-dg2-set2: [SKIP][321] ([Intel XE#2423] / [i915#2575]) -> [SKIP][322] ([Intel XE#455])
[321]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-466/igt@kms_scaling_modes@scaling-mode-full-aspect.html
[322]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-466/igt@kms_scaling_modes@scaling-mode-full-aspect.html
- shard-bmg: [SKIP][323] ([Intel XE#3007]) -> [SKIP][324] ([Intel XE#2413])
[323]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-1/igt@kms_scaling_modes@scaling-mode-full-aspect.html
[324]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-5/igt@kms_scaling_modes@scaling-mode-full-aspect.html
* igt@kms_tiled_display@basic-test-pattern:
- shard-bmg: [SKIP][325] ([Intel XE#2426]) -> [FAIL][326] ([Intel XE#1729])
[325]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@kms_tiled_display@basic-test-pattern.html
[326]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-1/igt@kms_tiled_display@basic-test-pattern.html
- shard-dg2-set2: [SKIP][327] ([Intel XE#362]) -> [FAIL][328] ([Intel XE#1729])
[327]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@kms_tiled_display@basic-test-pattern.html
[328]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-464/igt@kms_tiled_display@basic-test-pattern.html
* igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram:
- shard-dg2-set2: [SKIP][329] ([Intel XE#2905]) -> [SKIP][330] ([Intel XE#1130])
[329]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram.html
[330]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram.html
- shard-bmg: [SKIP][331] ([Intel XE#2905]) -> [SKIP][332] ([Intel XE#1130])
[331]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram.html
[332]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_eudebug_online@writes-caching-vram-bb-sram-target-sram.html
* igt@xe_exec_basic@multigpu-no-exec-userptr-rebind:
- shard-bmg: [SKIP][333] ([Intel XE#2322]) -> [SKIP][334] ([Intel XE#1130])
[333]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-5/igt@xe_exec_basic@multigpu-no-exec-userptr-rebind.html
[334]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_exec_basic@multigpu-no-exec-userptr-rebind.html
* igt@xe_exec_fault_mode@many-userptr-imm:
- shard-dg2-set2: [SKIP][335] ([Intel XE#288]) -> [SKIP][336] ([Intel XE#1130]) +3 other tests skip
[335]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-463/igt@xe_exec_fault_mode@many-userptr-imm.html
[336]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_exec_fault_mode@many-userptr-imm.html
* igt@xe_exec_reset@parallel-gt-reset:
- shard-dg2-set2: [ABORT][337] -> [TIMEOUT][338] ([Intel XE#2105])
[337]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html
[338]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-433/igt@xe_exec_reset@parallel-gt-reset.html
* igt@xe_pat@pat-index-xelp:
- shard-bmg: [SKIP][339] ([Intel XE#2237] / [Intel XE#2245]) -> [SKIP][340] ([Intel XE#1130])
[339]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-2/igt@xe_pat@pat-index-xelp.html
[340]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_pat@pat-index-xelp.html
* igt@xe_pm@d3cold-mocs:
- shard-bmg: [SKIP][341] ([Intel XE#2284]) -> [SKIP][342] ([Intel XE#1130])
[341]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@xe_pm@d3cold-mocs.html
[342]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_pm@d3cold-mocs.html
- shard-dg2-set2: [SKIP][343] ([Intel XE#2284]) -> [SKIP][344] ([Intel XE#1130])
[343]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-435/igt@xe_pm@d3cold-mocs.html
[344]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_pm@d3cold-mocs.html
* igt@xe_query@multigpu-query-uc-fw-version-guc:
- shard-dg2-set2: [SKIP][345] ([Intel XE#944]) -> [SKIP][346] ([Intel XE#1130])
[345]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-dg2-434/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[346]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-dg2-463/igt@xe_query@multigpu-query-uc-fw-version-guc.html
- shard-bmg: [SKIP][347] ([Intel XE#944]) -> [SKIP][348] ([Intel XE#1130])
[347]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52/shard-bmg-7/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[348]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/shard-bmg-4/igt@xe_query@multigpu-query-uc-fw-version-guc.html
[Intel XE#1033]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1033
[Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
[Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
[Intel XE#1126]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1126
[Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
[Intel XE#1130]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1130
[Intel XE#1135]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1135
[Intel XE#1195]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1195
[Intel XE#1204]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1204
[Intel XE#1231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1231
[Intel XE#1242]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1242
[Intel XE#1358]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1358
[Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
[Intel XE#1473]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1473
[Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
[Intel XE#1491]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1491
[Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
[Intel XE#1512]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1512
[Intel XE#1607]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1607
[Intel XE#1630]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1630
[Intel XE#1701]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1701
[Intel XE#1727]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1727
[Intel XE#1729]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1729
[Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
[Intel XE#1861]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1861
[Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
[Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
[Intel XE#2055]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2055
[Intel XE#2105]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2105
[Intel XE#2136]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2136
[Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
[Intel XE#2231]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2231
[Intel XE#2234]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2234
[Intel XE#2237]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2237
[Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
[Intel XE#2245]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2245
[Intel XE#2249]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2249
[Intel XE#2252]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2252
[Intel XE#2284]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2284
[Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
[Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
[Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
[Intel XE#2322]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2322
[Intel XE#2327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2327
[Intel XE#2328]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2328
[Intel XE#2333]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2333
[Intel XE#2340]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2340
[Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
[Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
[Intel XE#2387]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2387
[Intel XE#2390]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2390
[Intel XE#2392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2392
[Intel XE#2413]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2413
[Intel XE#2414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2414
[Intel XE#2423]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2423
[Intel XE#2426]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2426
[Intel XE#2443]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2443
[Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
[Intel XE#2566]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2566
[Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
[Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
[Intel XE#2667]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2667
[Intel XE#2687]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2687
[Intel XE#2791]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2791
[Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
[Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
[Intel XE#2882]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2882
[Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
[Intel XE#2890]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2890
[Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
[Intel XE#2905]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2905
[Intel XE#2907]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2907
[Intel XE#2910]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2910
[Intel XE#2927]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2927
[Intel XE#2929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2929
[Intel XE#2932]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2932
[Intel XE#2939]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2939
[Intel XE#2948]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2948
[Intel XE#3007]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3007
[Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
[Intel XE#307]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/307
[Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
[Intel XE#3149]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3149
[Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
[Intel XE#3184]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3184
[Intel XE#3194]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3194
[Intel XE#323]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/323
[Intel XE#327]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/327
[Intel XE#346]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/346
[Intel XE#362]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/362
[Intel XE#366]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/366
[Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
[Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
[Intel XE#402]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/402
[Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
[Intel XE#579]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/579
[Intel XE#599]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/599
[Intel XE#619]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/619
[Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
[Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
[Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
[Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
[Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
[Intel XE#827]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/827
[Intel XE#877]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/877
[Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
[Intel XE#899]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/899
[Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
[Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
[i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575
Build changes
-------------
* IGT: IGT_8081 -> IGT_8082
* Linux: xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52 -> xe-pw-140323v1
IGT_8081: 9b8c0f6da8898f760bfaa2113455eb84b68a69f4 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
IGT_8082: c8379ec8b26f3c21bae5473706b23da78bd26ffa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
xe-2107-beaeaccd284ba3b69b6dbfdc18bb89441fc99a52: beaeaccd284ba3b69b6dbfdc18bb89441fc99a52
xe-pw-140323v1: 140323v1
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-140323v1/index.html
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