Re: [PATCH 03/15] drm/i915/display: convert HAS_4TILE() to struct intel_display

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Mon, Nov 04, 2024 at 07:19:17PM +0200, Jani Nikula wrote:
> Convert HAS_4TILE() to struct intel_display. Do minimal drive-by
> conversions to struct intel_display in the callers while at it.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  .../gpu/drm/i915/display/intel_display_device.h    |  2 +-
>  drivers/gpu/drm/i915/display/skl_universal_plane.c | 14 ++++++++------
>  2 files changed, 9 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display_device.h b/drivers/gpu/drm/i915/display/intel_display_device.h
> index e45ba21166d3..70d1beebbf8f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_device.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_device.h
> @@ -138,7 +138,7 @@ struct intel_display_platforms {
>  	func(overlay_needs_physical); \
>  	func(supports_tv);
>  
> -#define HAS_4TILE(i915)			(IS_DG2(i915) || DISPLAY_VER(i915) >= 14)
> +#define HAS_4TILE(__display)		((__display)->platform.dg2 || DISPLAY_VER(__display) >= 14)
>  #define HAS_ASYNC_FLIPS(i915)		(DISPLAY_VER(i915) >= 5)
>  #define HAS_BIGJOINER(i915)		(DISPLAY_VER(i915) >= 11 && HAS_DSC(i915))
>  #define HAS_CDCLK_CRAWL(i915)		(DISPLAY_INFO(i915)->has_cdclk_crawl)
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c6e464d70cc7..28f7f2405ef3 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -2550,13 +2550,14 @@ static bool tgl_plane_has_mc_ccs(struct drm_i915_private *i915,
>  static u8 skl_get_plane_caps(struct drm_i915_private *i915,
>  			     enum pipe pipe, enum plane_id plane_id)
>  {
> +	struct intel_display *display = &i915->display;
>  	u8 caps = INTEL_PLANE_CAP_TILING_X;
>  
> -	if (DISPLAY_VER(i915) < 13 || IS_ALDERLAKE_P(i915))
> +	if (DISPLAY_VER(display) < 13 || display->platform.alderlake_p)
>  		caps |= INTEL_PLANE_CAP_TILING_Y;
> -	if (DISPLAY_VER(i915) < 12)
> +	if (DISPLAY_VER(display) < 12)
>  		caps |= INTEL_PLANE_CAP_TILING_Yf;
> -	if (HAS_4TILE(i915))
> +	if (HAS_4TILE(display))
>  		caps |= INTEL_PLANE_CAP_TILING_4;
>  
>  	if (!IS_ENABLED(I915) && !HAS_FLAT_CCS(i915))
> @@ -2564,14 +2565,14 @@ static u8 skl_get_plane_caps(struct drm_i915_private *i915,
>  
>  	if (skl_plane_has_rc_ccs(i915, pipe, plane_id)) {
>  		caps |= INTEL_PLANE_CAP_CCS_RC;
> -		if (DISPLAY_VER(i915) >= 12)
> +		if (DISPLAY_VER(display) >= 12)
>  			caps |= INTEL_PLANE_CAP_CCS_RC_CC;
>  	}
>  
>  	if (tgl_plane_has_mc_ccs(i915, plane_id))
>  		caps |= INTEL_PLANE_CAP_CCS_MC;
>  
> -	if (DISPLAY_VER(i915) >= 14 && IS_DGFX(i915))
> +	if (DISPLAY_VER(display) >= 14 && display->platform.dgfx)
>  		caps |= INTEL_PLANE_CAP_NEED64K_PHYS;
>  
>  	return caps;
> @@ -2745,6 +2746,7 @@ void
>  skl_get_initial_plane_config(struct intel_crtc *crtc,
>  			     struct intel_initial_plane_config *plane_config)
>  {
> +	struct intel_display *display = to_intel_display(crtc);
>  	struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
>  	struct drm_device *dev = crtc->base.dev;
>  	struct drm_i915_private *dev_priv = to_i915(dev);
> @@ -2826,7 +2828,7 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>  			fb->modifier = I915_FORMAT_MOD_Y_TILED;
>  		break;
>  	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> -		if (HAS_4TILE(dev_priv)) {
> +		if (HAS_4TILE(display)) {
>  			u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
>  				      PLANE_CTL_CLEAR_COLOR_DISABLE;
>  
> -- 
> 2.39.5
>