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(Ankit) > > --v3: > - Write registers at compute config. > - Update condition for write. > > --v4: > - Address issue with state checker. > > Signed-off-by: Mitul Golani Reviewed-by: Ankit Nautiyal > --- > drivers/gpu/drm/i915/display/intel_vrr.c | 26 ++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index dcaae7631b0a..b2348ae10a1a 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -627,6 +627,23 @@ void intel_vrr_enable(const struct intel_crtc_state *crtc_state) > VRR_CTL_VRR_ENABLE | trans_vrr_ctl(crtc_state)); > } > } > + > + if (crtc_state->vrr.dc_balance.enable) { > + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), > + crtc_state->vrr.dc_balance.vmin - 1); > + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), > + crtc_state->vrr.dc_balance.vmax - 1); > + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), > + crtc_state->vrr.dc_balance.max_increase); > + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), > + crtc_state->vrr.dc_balance.max_decrease); > + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), > + crtc_state->vrr.dc_balance.guardband); > + intel_de_write(display, PIPEDMC_DCB_SLOPE(pipe), > + crtc_state->vrr.dc_balance.slope); > + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), > + crtc_state->vrr.dc_balance.vblank_target); > + } > } > > void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > @@ -637,6 +654,15 @@ void intel_vrr_disable(const struct intel_crtc_state *old_crtc_state) > if (!old_crtc_state->vrr.enable) > return; > > + if (old_crtc_state->vrr.dc_balance.enable) { > + intel_de_write(display, PIPEDMC_DCB_VMIN(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_VMAX(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_MAX_INCREASE(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_MAX_DECREASE(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_GUARDBAND(pipe), 0); > + intel_de_write(display, PIPEDMC_DCB_VBLANK(pipe), 0); > + } > + > if (!intel_vrr_always_use_vrr_tg(display)) { > intel_de_write(display, TRANS_VRR_CTL(display, cpu_transcoder), > trans_vrr_ctl(old_crtc_state));