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From: Michal Wajdeczko <michal.wajdeczko@intel.com>
To: Matthew Brost <matthew.brost@intel.com>
Cc: intel-xe@lists.freedesktop.org,
	"Michał Winiarski" <michal.winiarski@intel.com>,
	"Piotr Piórkowski" <piotr.piorkowski@intel.com>
Subject: Re: [PATCH 3/3] drm/xe/pf: Invalidate LMTT after completing changes
Date: Thu, 3 Jul 2025 16:03:28 +0200	[thread overview]
Message-ID: <a22f999a-6d73-4f3b-8b49-6124482d7ed6@intel.com> (raw)
In-Reply-To: <aGW1poOpWmu2qa8P@lstrano-desk.jf.intel.com>



On 03.07.2025 00:41, Matthew Brost wrote:
> On Thu, Jul 03, 2025 at 12:30:41AM +0200, Michal Wajdeczko wrote:
>> Once we finish populating all leaf pages in the VF's LMTT we should
>> make sure that hardware will not access any stale data. Explicitly
>> force LMTT invalidation (as it was already planned in the past).
>>
>> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com>
>> Cc: Michał Winiarski <michal.winiarski@intel.com>
>> Cc: Piotr Piórkowski <piotr.piorkowski@intel.com>
>> ---
>>  drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c | 12 +++++++++++-
>>  1 file changed, 11 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> index a75ef4007a1e..a1b916e80fdd 100644
>> --- a/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> +++ b/drivers/gpu/drm/xe/xe_gt_sriov_pf_config.c
>> @@ -1327,7 +1327,17 @@ static int pf_distribute_config_lmem(struct xe_gt *gt, unsigned int vfid, u64 si
>>  
>>  static void pf_force_lmtt_invalidate(struct xe_device *xe)
>>  {
>> -	/* TODO */
>> +	struct xe_lmtt *lmtt;
>> +	struct xe_tile *tile;
>> +	unsigned int tid;
>> +
>> +	xe_assert(xe, xe_device_has_lmtt(xe));
>> +	xe_assert(xe, IS_SRIOV_PF(xe));
>> +
>> +	for_each_tile(tile, xe, tid) {
>> +		lmtt = &tile->sriov.pf.lmtt;
>> +		xe_lmtt_invalidate_hw(lmtt);
> 
> If this is a critical path, you may want to consider issuing all TLB
> invalidations across all GTs/tiles, then waiting on all fences to
> pipeline these - we do this the VM code which is certainly a critical
> path. If this is not-so-critical here, maybe this is ok.

no, it's not on any critical path right now and btw I already have some
hybrid solution: first I'm sending TLBINVAL to all GTs per tile and then
waiting for those fences, as this was more self contained from the LMTT
SW component POV (since it's per-tile)

> 
> Matt
> 
>> +	}
>>  }
>>  
>>  static void pf_reset_vf_lmtt(struct xe_device *xe, unsigned int vfid)
>> -- 
>> 2.47.1
>>


  reply	other threads:[~2025-07-03 14:03 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-02 22:30 [PATCH 0/3] LMTT invalidation Michal Wajdeczko
2025-07-02 22:30 ` [PATCH 1/3] drm/xe/pf: Force GuC virtualization mode Michal Wajdeczko
2025-07-02 22:30 ` [PATCH 2/3] drm/xe/pf: Invalidate LMTT during LMEM unprovisioning Michal Wajdeczko
2025-07-03  9:10   ` [PATCH v2 " Michal Wajdeczko
2025-07-03 14:18   ` [PATCH v3 " Michal Wajdeczko
2025-07-03 17:31   ` [PATCH " Matthew Brost
2025-07-03 17:42     ` Michal Wajdeczko
2025-07-03 17:56       ` Matthew Brost
2025-07-02 22:30 ` [PATCH 3/3] drm/xe/pf: Invalidate LMTT after completing changes Michal Wajdeczko
2025-07-02 22:41   ` Matthew Brost
2025-07-03 14:03     ` Michal Wajdeczko [this message]
2025-07-02 22:52 ` ✗ CI.checkpatch: warning for LMTT invalidation Patchwork
2025-07-02 22:53 ` ✓ CI.KUnit: success " Patchwork
2025-07-03 14:23 ` ✗ CI.checkpatch: warning for LMTT invalidation (rev3) Patchwork
2025-07-03 14:24 ` ✓ CI.KUnit: success " Patchwork
2025-07-03 15:01 ` ✗ Xe.CI.BAT: failure " Patchwork
2025-07-05  3:01 ` ✗ Xe.CI.Full: " Patchwork

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