From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A47D8CCFA04 for ; Mon, 3 Nov 2025 10:01:57 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6383210E1B6; Mon, 3 Nov 2025 10:01:57 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="MQvTAoEm"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.15]) by gabe.freedesktop.org (Postfix) with ESMTPS id 113A510E39E; Mon, 3 Nov 2025 10:01:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1762164116; x=1793700116; h=from:to:cc:subject:in-reply-to:references:date: message-id:mime-version; bh=1ZjdTmEX/WDy0WGwI5onotg3H2UUFSYMbez/BCAlHAw=; b=MQvTAoEmbduxcd1URMlqLUkoKd4/6MZZPJBUDYWwprTdyN5Rq1f3+JS6 d1Kqs9DywiUnowcKm4VgLG4xl9jDVUU49XQ8BpiCtsxWy+6CDbJeM+d5Q Jgg8MCdGKgU1Le6ZRDaAqXKYa81PDfXuMb4cvxjmVLrNQSCtLVgfn+FjP hhGmpP86oUDHM8mPF5tEnxm6Ca3Q65twpzNdLui/pbd+sch4Bz+Twa9bL p2BHG4xkSSamzYggIdBmMCbHGgfQa22744nKMqfKnv9MS8a+FKYEi20Ze eJ6JflF0DbiXd787OOD9tRTZS6k9kuhf+qq79SqanSV9lzRm2lt44PM9D A==; X-CSE-ConnectionGUID: lFD3Jl5uRxiTstGXIvPUeQ== X-CSE-MsgGUID: T4GmCmC7TBq3/K5Bl2zvfw== X-IronPort-AV: E=McAfee;i="6800,10657,11601"; a="64332516" X-IronPort-AV: E=Sophos;i="6.19,275,1754982000"; d="scan'208";a="64332516" Received: from orviesa004.jf.intel.com ([10.64.159.144]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2025 02:01:56 -0800 X-CSE-ConnectionGUID: 7m3dFuWTRX6BVgdwUrll4g== X-CSE-MsgGUID: XU7Aep7cTiiCMK1kOncA3A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.19,275,1754982000"; d="scan'208";a="191167935" Received: from krybak-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.246.127]) by orviesa004-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Nov 2025 02:01:53 -0800 From: Jani Nikula To: Mitul Golani , intel-gfx@lists.freedesktop.org Cc: intel-xe@lists.freedesktop.org, mitulkumar.ajitkumar.golani@intel.com, ankit.k.nautiyal@intel.com, uma.shankar@intel.com, ville.syrjala@linux.intel.com Subject: Re: [RESEND, 09/22] drm/i915/vrr: Increment DC balance flip count on every flip In-Reply-To: <20251103053002.3002695-10-mitulkumar.ajitkumar.golani@intel.com> Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo References: <20251103053002.3002695-1-mitulkumar.ajitkumar.golani@intel.com> <20251103053002.3002695-10-mitulkumar.ajitkumar.golani@intel.com> Date: Mon, 03 Nov 2025 12:01:49 +0200 Message-ID: MIME-Version: 1.0 Content-Type: text/plain X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Mon, 03 Nov 2025, Mitul Golani wrote: > Increment DC Balance Flip count before every send push to indicate > DMC firmware about new flip occurrence. This is tracked separately > from legacy FLIP_COUNT register. > > Signed-off-by: Mitul Golani > --- > drivers/gpu/drm/i915/display/intel_color.c | 1 + > drivers/gpu/drm/i915/display/intel_display.c | 1 + > drivers/gpu/drm/i915/display/intel_vrr.c | 15 +++++++++++++++ > drivers/gpu/drm/i915/display/intel_vrr.h | 3 +++ > 4 files changed, 20 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c > index 1e97020e7304..47a732ae2448 100644 > --- a/drivers/gpu/drm/i915/display/intel_color.c > +++ b/drivers/gpu/drm/i915/display/intel_color.c > @@ -2012,6 +2012,7 @@ void intel_color_prepare_commit(struct intel_atomic_state *state, > display->funcs.color->load_luts(crtc_state); > > if (crtc_state->use_dsb && intel_color_uses_chained_dsb(crtc_state)) { > + intel_vrr_dcb_increment_flip_count(crtc_state, crtc); > intel_vrr_send_push(crtc_state->dsb_color, crtc_state); > intel_dsb_wait_for_delayed_vblank(state, crtc_state->dsb_color); > intel_vrr_check_push_sent(crtc_state->dsb_color, crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c > index a00625f882e8..1a3e7a6e4ab7 100644 > --- a/drivers/gpu/drm/i915/display/intel_display.c > +++ b/drivers/gpu/drm/i915/display/intel_display.c > @@ -7366,6 +7366,7 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state, > if (new_crtc_state->use_dsb && !intel_color_uses_chained_dsb(new_crtc_state)) { > intel_dsb_wait_vblanks(new_crtc_state->dsb_commit, 1); > > + intel_vrr_dcb_increment_flip_count(new_crtc_state, crtc); > intel_vrr_send_push(new_crtc_state->dsb_commit, new_crtc_state); > intel_dsb_wait_for_delayed_vblank(state, new_crtc_state->dsb_commit); > intel_vrr_check_push_sent(new_crtc_state->dsb_commit, > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c > index 2948abc90c69..87bd722aa32d 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.c > +++ b/drivers/gpu/drm/i915/display/intel_vrr.c > @@ -14,6 +14,7 @@ > #include "intel_psr.h" > #include "intel_vrr.h" > #include "intel_vrr_regs.h" > +#include "intel_dmc_regs.h" Please keep includes sorted. > #include "skl_prefill.h" > #include "skl_watermark.h" > > @@ -612,6 +613,20 @@ void intel_vrr_set_transcoder_timings(const struct intel_crtc_state *crtc_state) > EMP_AS_SDP_DB_TL(crtc_state->vrr.vsync_start)); > } > > +void > +intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc) > +{ > + struct intel_display *display = to_intel_display(crtc_state); > + enum pipe pipe = crtc->pipe; > + > + if (!crtc_state->vrr.dc_balance.enable) > + return; > + > + intel_de_write(display, PIPEDMC_DCB_FLIP_COUNT(pipe), > + ++crtc->dc_balance.flip_count); > +} > + > void intel_vrr_send_push(struct intel_dsb *dsb, > const struct intel_crtc_state *crtc_state) > { > diff --git a/drivers/gpu/drm/i915/display/intel_vrr.h b/drivers/gpu/drm/i915/display/intel_vrr.h > index 66fb9ad846f2..eebc7be309db 100644 > --- a/drivers/gpu/drm/i915/display/intel_vrr.h > +++ b/drivers/gpu/drm/i915/display/intel_vrr.h > @@ -14,6 +14,7 @@ struct intel_connector; > struct intel_crtc_state; > struct intel_dsb; > struct intel_display; > +struct intel_crtc; Please keep forward declarations sorted. > > bool intel_vrr_is_capable(struct intel_connector *connector); > bool intel_vrr_is_in_range(struct intel_connector *connector, int vrefresh); > @@ -39,6 +40,8 @@ bool intel_vrr_is_fixed_rr(const struct intel_crtc_state *crtc_state); > void intel_vrr_transcoder_enable(const struct intel_crtc_state *crtc_state); > void intel_vrr_transcoder_disable(const struct intel_crtc_state *crtc_state); > void intel_vrr_set_fixed_rr_timings(const struct intel_crtc_state *crtc_state); > +void intel_vrr_dcb_increment_flip_count(struct intel_crtc_state *crtc_state, > + struct intel_crtc *crtc); > bool intel_vrr_always_use_vrr_tg(struct intel_display *display); > int intel_vrr_safe_window_start(const struct intel_crtc_state *crtc_state); > int intel_vrr_vmin_safe_window_end(const struct intel_crtc_state *crtc_state); -- Jani Nikula, Intel