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From: Raag Jadav <raag.jadav@intel.com>
To: Riana Tauro <riana.tauro@intel.com>
Cc: lucas.demarchi@intel.com, rodrigo.vivi@intel.com,
	intel-xe@lists.freedesktop.org, anshuman.gupta@intel.com,
	badal.nilawar@intel.com
Subject: Re: [PATCH v2 2/3] drm/xe: Expose PCIe Gen4 downspeed attributes
Date: Thu, 17 Apr 2025 10:48:09 +0300	[thread overview]
Message-ID: <aACyOW5u9Hof1vaP@black.fi.intel.com> (raw)
In-Reply-To: <6ef5b3b0-cf8c-4882-a686-9b9c7f6679c1@intel.com>

On Thu, Apr 17, 2025 at 10:47:19AM +0530, Riana Tauro wrote:
> On 4/16/2025 8:56 PM, Raag Jadav wrote:
> > On Wed, Apr 16, 2025 at 08:22:38PM +0530, Riana Tauro wrote:
> > > On 4/16/2025 4:28 PM, Raag Jadav wrote:
> > > > On Wed, Apr 16, 2025 at 03:36:55PM +0530, Riana Tauro wrote:
> > > > > Hi Raag
> > > > > 
> > > > > On 4/3/2025 11:17 PM, Raag Jadav wrote:
> > > > > > Expose sysfs attributes for PCIe Gen4 downspeed capability and status.
> > 
> > ...
> > 
> > > > > > +static ssize_t
> > > > > > +pcie_gen4_downspeed_status_show(struct device *dev, struct device_attribute *attr, char *buf)
> > > > > > +{
> > > > > > +	struct pci_dev *pdev = to_pci_dev(dev);
> > > > > > +	struct xe_device *xe = pdev_to_xe_device(pdev);
> > > > > > +	u32 val;
> > > > > > +	int ret;
> > > > > > +
> > > > > > +	xe_pm_runtime_get(xe);
> > > > > > +	ret = xe_pcode_read(xe_device_get_root_tile(xe), PCODE_MBOX(DGFX_PCODE_STATUS,
> > > > > > +			    DGFX_GET_INIT_STATUS, 0), &val, NULL);
> > > > > indentation
> > > > 
> > > > Can you please elaborate? Shouldn't it follow the parentheses?
> > > yeah it should. DGFX_GET_INIT_STATUS should follow PCODE_MBOX parenthesis
> > > 
> > > or align PCODE_MBOX instead
> > > 
> > > ret = xe_pcode_read(xe_device_get_root_tile(xe),
> > >                      PCODE_MBOX...

This'll warrant a third line which we can easily avoid here.

> > Which means we should change it in hwmon as well?
> Not sure about hwmon. checkpatch is also mentioning the same
> 
> -:89: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
> #89: FILE: drivers/gpu/drm/xe/xe_device_sysfs.c:130:
> 	ret = xe_pcode_read(xe_device_get_root_tile(xe),
> PCODE_MBOX(DGFX_PCODE_STATUS,
> 			    DGFX_GET_INIT_STATUS, 0), &val, NULL);

Yes, it complains about a lot of things but it's referred as a general
guidance than a hard rule.

https://lore.kernel.org/all/CAHk-=wgfzPOao+Rbq4aSitQ2gPaZ9PPGbR290X4BikD_W8ZcUg@mail.gmail.com/

Raag

  reply	other threads:[~2025-04-17  7:48 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-03 17:47 [PATCH v2 0/3] BMG PCIe Gen4 downspeed attributes and usage Raag Jadav
2025-04-03 17:47 ` [PATCH v2 1/3] drm/xe: Move xe_device_sysfs_init() to xe_pci_probe() Raag Jadav
2025-04-16  7:55   ` Riana Tauro
2025-04-16 10:04     ` Riana Tauro
2025-04-16 10:49       ` Raag Jadav
2025-04-16 14:45         ` Riana Tauro
2025-04-16 16:37           ` Raag Jadav
2025-04-17  5:22             ` Riana Tauro
2025-04-17  7:54               ` Raag Jadav
2025-04-03 17:47 ` [PATCH v2 2/3] drm/xe: Expose PCIe Gen4 downspeed attributes Raag Jadav
2025-04-16 10:06   ` Riana Tauro
2025-04-16 10:58     ` Raag Jadav
2025-04-16 14:52       ` Riana Tauro
2025-04-16 15:26         ` Raag Jadav
2025-04-17  5:17           ` Riana Tauro
2025-04-17  7:48             ` Raag Jadav [this message]
2025-04-03 17:47 ` [PATCH v2 3/3] drm/xe/doc: Wire up PCIe Gen5 update limitations Raag Jadav
2025-04-03 23:39 ` ✓ CI.Patch_applied: success for BMG PCIe Gen4 downspeed attributes and usage Patchwork
2025-04-03 23:39 ` ✗ CI.checkpatch: warning " Patchwork
2025-04-03 23:40 ` ✓ CI.KUnit: success " Patchwork
2025-04-03 23:57 ` ✓ CI.Build: " Patchwork
2025-04-03 23:59 ` ✓ CI.Hooks: " Patchwork
2025-04-04  0:00 ` ✓ CI.checksparse: " Patchwork
2025-04-04  0:18 ` ✓ Xe.CI.BAT: " Patchwork
2025-04-04  9:19 ` ✗ Xe.CI.Full: failure " Patchwork

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