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Are we aware of > something that would be wired to bit 16 that would prevent us from doing > that? Not sure if a register bit is not used, unless it's defined as reserved. For pre-Xe3 (pre-PTL) bits 16-17 are not defined as reserved. > I remember something similar was done to other register fields in the > past. Some examples I found: > > 3fe856180c94 ("drm/i915/xe3lpd: Add new bit range of MAX swing setup") > 247bdac958fc ("drm/i915/adl_p: Add ddb allocation support") > d7e449a858ec ("drm/i915: Just use icl+ definition for PLANE_WM blocks field") > > -- > Gustavo Sousa > > >+#define XELPDP_DDI_CLOCK_SELECT_MASK(display) (DISPLAY_VER(display) >= 30 ? \ > >+ _XE3_DDI_CLOCK_SELECT_MASK : _XELPDP_DDI_CLOCK_SELECT_MASK) > >+#define XELPDP_DDI_CLOCK_SELECT_PREP(display, val) (DISPLAY_VER(display) >= 30 ? \ > >+ REG_FIELD_PREP(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ > >+ REG_FIELD_PREP(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) > >+#define XELPDP_DDI_CLOCK_SELECT_GET(display, val) (DISPLAY_VER(display) >= 30 ? \ > >+ REG_FIELD_GET(_XE3_DDI_CLOCK_SELECT_MASK, (val)) : \ > >+ REG_FIELD_GET(_XELPDP_DDI_CLOCK_SELECT_MASK, (val))) > >+ > > #define XELPDP_DDI_CLOCK_SELECT_NONE 0x0 > > #define XELPDP_DDI_CLOCK_SELECT_MAXPCLK 0x8 > > #define XELPDP_DDI_CLOCK_SELECT_DIV18CLK 0x9 > >-- > >2.44.2 > >