From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 6F431C54F32 for ; Sat, 24 May 2025 10:01:56 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9827F10E148; Sat, 24 May 2025 10:01:55 +0000 (UTC) Authentication-Results: gabe.freedesktop.org; dkim=pass (2048-bit key; unprotected) header.d=intel.com header.i=@intel.com header.b="emV46PVg"; dkim-atps=neutral Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.9]) by gabe.freedesktop.org (Postfix) with ESMTPS id B86C010E010; Sat, 24 May 2025 10:01:53 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1748080914; x=1779616914; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=8Z1S/hNWZ9pEp/mNhwra4+VgljiQYHC4PHrsvJbhuBA=; b=emV46PVgrR3hkzOENDnOVHm0p9GcjuvvL3+gcztVi9esJ76z/SUe/lFS EzGjiHyW673y0t5fmkf73o6qIYY51kF+8AHI9f2seE9NxG9RKMj1uBRLM ODDKmDPlje3TaAMxdhtJvnR/R2lAFT8R6vCZmN6o3cK31zLPJAcuqXyWr KL3eNfFJOdVZrrkCWFAEvfaVpVvvEg1pqUKsYNASxFoPabJtgbjsARG5b ucuGuFn874nl3eHR1+i6xa4aF9a87Oxm5L6/T/JnD4939HYfOJAPVhdEd Ey0Z3MwYw65Z7qPqNrRGe0N1mLjj7kb7QMijrEPUdzDE2wZfaqJZWag/q A==; X-CSE-ConnectionGUID: smB2eY5aT2q2i/WJzwnW3Q== X-CSE-MsgGUID: CflhWdiNSUa0pviPBlUL/g== X-IronPort-AV: E=McAfee;i="6700,10204,11441"; a="60778846" X-IronPort-AV: E=Sophos;i="6.15,311,1739865600"; d="scan'208";a="60778846" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2025 03:01:53 -0700 X-CSE-ConnectionGUID: Gsn2aVMxTheSeNn7uAZ8ig== X-CSE-MsgGUID: x09pD8gQTg284T1blC2gRw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.15,311,1739865600"; d="scan'208";a="142063527" Received: from black.fi.intel.com ([10.237.72.28]) by orviesa007.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 May 2025 03:01:47 -0700 Date: Sat, 24 May 2025 13:01:44 +0300 From: Raag Jadav To: Alexander Usyskin Cc: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa , Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, intel-xe@lists.freedesktop.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v10 05/10] mtd: intel-dg: align 64bit read and write Message-ID: References: <20250515133345.2805031-1-alexander.usyskin@intel.com> <20250515133345.2805031-6-alexander.usyskin@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250515133345.2805031-6-alexander.usyskin@intel.com> X-BeenThere: intel-xe@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Intel Xe graphics driver List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-xe-bounces@lists.freedesktop.org Sender: "Intel-xe" On Thu, May 15, 2025 at 04:33:40PM +0300, Alexander Usyskin wrote: > GSC NVM controller HW errors on quad access overlapping 1K border. > Align 64bit read and write to avoid readq/writeq over 1K border. > > Acked-by: Miquel Raynal > Signed-off-by: Alexander Usyskin > --- > drivers/mtd/devices/mtd_intel_dg.c | 35 ++++++++++++++++++++++++++++++ > 1 file changed, 35 insertions(+) > > diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_intel_dg.c > index eedc0974bb5b..2f32ed311ffd 100644 > --- a/drivers/mtd/devices/mtd_intel_dg.c > +++ b/drivers/mtd/devices/mtd_intel_dg.c > @@ -246,6 +246,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 region, > len_s -= to_shift; > } > > + if (!IS_ALIGNED(to, sizeof(u64)) && > + ((to ^ (to + len_s)) & GENMASK(31, 10))) { > + /* > + * Workaround reads/writes across 1k-aligned addresses > + * (start u32 before 1k, end u32 after) > + * as this fails on hardware. If there's a spec definition, we usually mention workarounds with Wa_ID:platform so that they're easy to track. intel_workarounds.c is good reference for it. > + */ > + u32 data; > + > + memcpy(&data, &buf[0], sizeof(u32)); > + idg_nvm_write32(nvm, to, data); > + if (idg_nvm_error(nvm)) > + return -EIO; > + buf += sizeof(u32); > + to += sizeof(u32); > + len_s -= sizeof(u32); > + } > + > len8 = ALIGN_DOWN(len_s, sizeof(u64)); > for (i = 0; i < len8; i += sizeof(u64)) { > u64 data; > @@ -303,6 +321,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 region, > from += from_shift; > } > > + if (!IS_ALIGNED(from, sizeof(u64)) && > + ((from ^ (from + len_s)) & GENMASK(31, 10))) { > + /* > + * Workaround reads/writes across 1k-aligned addresses > + * (start u32 before 1k, end u32 after) > + * as this fails on hardware. > + */ > + u32 data = idg_nvm_read32(nvm, from); > + > + if (idg_nvm_error(nvm)) > + return -EIO; > + memcpy(&buf[0], &data, sizeof(data)); > + len_s -= sizeof(u32); > + buf += sizeof(u32); > + from += sizeof(u32); > + } > + > len8 = ALIGN_DOWN(len_s, sizeof(u64)); > for (i = 0; i < len8; i += sizeof(u64)) { > u64 data = idg_nvm_read64(nvm, from + i); > -- > 2.43.0 >