Re: [PATCH v4 3/4] drm/xe/pm: Wire up suspend/resume for I2C controller

[Raag Jadav <raag.jadav@intel.com>]

On Fri, Jun 27, 2025 at 03:58:00PM +0300, Heikki Krogerus wrote:
> On Fri, Jun 27, 2025 at 03:45:28PM +0300, Raag Jadav wrote:
> > Hi Heikki,
> > 
> > Thanks for picking this up.
> > 
> > On Thu, Jun 26, 2025 at 04:56:08PM +0300, Heikki Krogerus wrote:
> > > From: Raag Jadav <raag.jadav@intel.com>
> > > 
> > > Wire up suspend/resume handles for I2C controller to match its power
> > > state with SGUnit.
> > 
> > ...
> > 
> > > diff --git a/drivers/gpu/drm/xe/xe_i2c.c b/drivers/gpu/drm/xe/xe_i2c.c
> > > index bfbfe1de7f77..0227fcba2168 100644
> > > --- a/drivers/gpu/drm/xe/xe_i2c.c
> > > +++ b/drivers/gpu/drm/xe/xe_i2c.c
> > > @@ -227,6 +227,31 @@ static const struct regmap_config i2c_regmap_config = {
> > >  	.fast_io = true,
> > >  };
> > >  
> > > +void xe_i2c_pm_suspend(struct xe_device *xe)
> > > +{
> > > +	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> > > +
> > > +	if (!xe->i2c || xe->i2c->ep.cookie != XE_I2C_EP_COOKIE_DEVICE)
> > > +		return;
> > > +
> > > +	xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, PCI_D3hot);
> > 
> > I just realized the power modes will need (__force u32) casting to make
> > sparse happy. If you're planning another version, can you please include
> > it? If not, we can have a quick fix later on.
> 
> I can include the casting, np. Is it enough to cast PCI_D3hot?

Looking at some of the existing code, it seems should be good enough.

Raag

> > > +	drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));
> > > +}
> > > +
> > > +void xe_i2c_pm_resume(struct xe_device *xe, bool d3cold)
> > > +{
> > > +	struct xe_mmio *mmio = xe_root_tile_mmio(xe);
> > > +
> > > +	if (!xe->i2c || xe->i2c->ep.cookie != XE_I2C_EP_COOKIE_DEVICE)
> > > +		return;
> > > +
> > > +	if (d3cold)
> > > +		xe_mmio_rmw32(mmio, I2C_CONFIG_CMD, 0, PCI_COMMAND_MEMORY);
> > > +
> > > +	xe_mmio_rmw32(mmio, I2C_CONFIG_PMCSR, PCI_PM_CTRL_STATE_MASK, PCI_D0);
> > 
> > Ditto.
> > 
> > > +	drm_dbg(&xe->drm, "pmcsr: 0x%08x\n", xe_mmio_read32(mmio, I2C_CONFIG_PMCSR));