[PATCH 00/16] drm/i915/display: make all global state opaque

[PATCH 00/16] drm/i915/display: make all global state opaque

[Jani Nikula]

Hide all the structs that "derive" from struct intel_global_state inside
their respective implementation files.

Jani Nikula (16):
  drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()
  drm/i915/wm: add more accessors to dbuf state
  drm/i915/wm: make struct intel_dbuf_state opaque type
  drm/i915/bw: abstract intel_bw_pmdemand_needs_update()
  drm/i915/bw: relocate intel_can_enable_sagv() and rename to
    intel_bw_can_enable_sagv()
  drm/i915: move icl_sagv_{pre,post}_plane_update() to intel_bw.c
  drm/i915/bw: abstract intel_bw_qgv_point_peakbw()
  drm/i915/bw: make struct intel_bw_state opaque
  drm/i915/cdclk: abstract intel_cdclk_logical()
  drm/i915/cdclk: abstract intel_cdclk_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()
  drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()
  drm/i915/cdclk: abstract intel_cdclk_read_hw()
  drm/i915/cdclk: abstract intel_cdclk_actual() and
    intel_cdclk_actual_voltage_level()
  drm/i915/cdclk: make struct intel_cdclk_state opaque

 drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
 .../gpu/drm/i915/display/intel_atomic_plane.c |   4 +-
 drivers/gpu/drm/i915/display/intel_audio.c    |   2 +-
 drivers/gpu/drm/i915/display/intel_bw.c       | 153 ++++++++++++++++--
 drivers/gpu/drm/i915/display/intel_bw.h       |  53 ++----
 drivers/gpu/drm/i915/display/intel_cdclk.c    |  93 +++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  50 ++----
 drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
 .../drm/i915/display/intel_display_driver.c   |   8 +-
 drivers/gpu/drm/i915/display/intel_fbc.c      |   2 +-
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  41 ++---
 drivers/gpu/drm/i915/display/skl_watermark.c  | 134 +++++++--------
 drivers/gpu/drm/i915/display/skl_watermark.h  |  33 +---
 13 files changed, 336 insertions(+), 241 deletions(-)

-- 
2.39.5

[PATCH 01/16] drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()

[Jani Nikula]

Add intel_dbuf_pmdemand_needs_update() helper to avoid looking at struct
intel_dbuf_state internals outside of skl_watermark.c.

With this, we can also move to_intel_dbuf_state(),
intel_atomic_get_old_dbuf_state(), and intel_atomic_get_new_dbuf_state()
inside skl_watermark.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 14 +--------
 drivers/gpu/drm/i915/display/skl_watermark.c  | 30 +++++++++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h  | 10 ++-----
 3 files changed, 33 insertions(+), 21 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 93d5ee36fff1..0f1501c456df 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,11 +294,9 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	struct intel_display *display = to_intel_display(state);
 	const struct intel_bw_state *new_bw_state, *old_bw_state;
 	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
-	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
 	struct intel_crtc *crtc;
 	int i;
 
@@ -308,19 +306,9 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 	    old_bw_state->qgv_point_peakbw)
 		return true;
 
-	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
-	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
-	if (new_dbuf_state &&
-	    new_dbuf_state->active_pipes != old_dbuf_state->active_pipes)
+	if (intel_dbuf_pmdemand_needs_update(state))
 		return true;
 
-	if (DISPLAY_VER(display) < 30) {
-		if (new_dbuf_state &&
-		    new_dbuf_state->enabled_slices !=
-		    old_dbuf_state->enabled_slices)
-			return true;
-	}
-
 	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
 	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
 	if (new_cdclk_state &&
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 2c2371574d6f..55280d16f9f7 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -38,6 +38,14 @@
  */
 #define DSB_EXE_TIME 100
 
+#define to_intel_dbuf_state(global_state) \
+	container_of_const((global_state), struct intel_dbuf_state, base)
+
+#define intel_atomic_get_old_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
+#define intel_atomic_get_new_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
+
 static void skl_sagv_disable(struct intel_display *display);
 
 /* Stores plane specific WM parameters */
@@ -3693,6 +3701,28 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 	gen9_dbuf_slices_update(display, new_slices);
 }
 
+bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_dbuf_state *new_dbuf_state, *old_dbuf_state;
+
+	new_dbuf_state = intel_atomic_get_new_dbuf_state(state);
+	old_dbuf_state = intel_atomic_get_old_dbuf_state(state);
+
+	if (new_dbuf_state &&
+	    new_dbuf_state->active_pipes != old_dbuf_state->active_pipes)
+		return true;
+
+	if (DISPLAY_VER(display) < 30) {
+		if (new_dbuf_state &&
+		    new_dbuf_state->enabled_slices !=
+		    old_dbuf_state->enabled_slices)
+			return true;
+	}
+
+	return false;
+}
+
 static void skl_mbus_sanitize(struct intel_display *display)
 {
 	struct intel_dbuf_state *dbuf_state =
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 95b0b599d5c3..3b9a0b254cff 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,14 +78,6 @@ struct intel_dbuf_state {
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
-#define to_intel_dbuf_state(global_state) \
-	container_of_const((global_state), struct intel_dbuf_state, base)
-
-#define intel_atomic_get_old_dbuf_state(state) \
-	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
-#define intel_atomic_get_new_dbuf_state(state) \
-	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))
-
 int intel_dbuf_init(struct intel_display *display);
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
 					   int ratio);
@@ -98,5 +90,7 @@ void intel_dbuf_mbus_pre_ddb_update(struct intel_atomic_state *state);
 void intel_dbuf_mbus_post_ddb_update(struct intel_atomic_state *state);
 void intel_program_dpkgc_latency(struct intel_atomic_state *state);
 
+bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state);
+
 #endif /* __SKL_WATERMARK_H__ */
 
-- 
2.39.5

[PATCH 02/16] drm/i915/wm: add more accessors to dbuf state

[Jani Nikula]

Add intel_dbuf_num_enabled_slices() and intel_dbuf_num_active_pipes()
helpers to avoid looking at struct intel_dbuf_state internals outside of
skl_watermark.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  6 +++---
 drivers/gpu/drm/i915/display/skl_watermark.c  | 10 ++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h  |  3 +++
 3 files changed, 16 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 0f1501c456df..eeb88f9fc92d 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -358,12 +358,12 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 
 	if (DISPLAY_VER(display) < 30) {
 		new_pmdemand_state->params.active_dbufs =
-			min_t(u8, hweight8(new_dbuf_state->enabled_slices), 3);
+			min_t(u8, intel_dbuf_num_enabled_slices(new_dbuf_state), 3);
 		new_pmdemand_state->params.active_pipes =
-			min_t(u8, hweight8(new_dbuf_state->active_pipes), 3);
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), 3);
 	} else {
 		new_pmdemand_state->params.active_pipes =
-			min_t(u8, hweight8(new_dbuf_state->active_pipes), INTEL_NUM_PIPES(display));
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));
 	}
 
 	new_cdclk_state = intel_atomic_get_cdclk_state(state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 55280d16f9f7..f35f2603d543 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -3701,6 +3701,16 @@ void intel_dbuf_post_plane_update(struct intel_atomic_state *state)
 	gen9_dbuf_slices_update(display, new_slices);
 }
 
+int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state)
+{
+	return hweight8(dbuf_state->enabled_slices);
+}
+
+int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state)
+{
+	return hweight8(dbuf_state->active_pipes);
+}
+
 bool intel_dbuf_pmdemand_needs_update(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 3b9a0b254cff..a1993ded034a 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -78,6 +78,9 @@ struct intel_dbuf_state {
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
+int intel_dbuf_num_enabled_slices(const struct intel_dbuf_state *dbuf_state);
+int intel_dbuf_num_active_pipes(const struct intel_dbuf_state *dbuf_state);
+
 int intel_dbuf_init(struct intel_display *display);
 int intel_dbuf_state_set_mdclk_cdclk_ratio(struct intel_atomic_state *state,
 					   int ratio);
-- 
2.39.5

[PATCH 03/16] drm/i915/wm: make struct intel_dbuf_state opaque type

[Jani Nikula]

With all the code touching struct intel_dbuf_state moved inside
skl_watermark.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from skl_watermark.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/skl_watermark.c | 12 ++++++++++++
 drivers/gpu/drm/i915/display/skl_watermark.h | 19 +++----------------
 2 files changed, 15 insertions(+), 16 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index f35f2603d543..34726895075b 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -38,6 +38,18 @@
  */
 #define DSB_EXE_TIME 100
 
+struct intel_dbuf_state {
+	struct intel_global_state base;
+
+	struct skl_ddb_entry ddb[I915_MAX_PIPES];
+	unsigned int weight[I915_MAX_PIPES];
+	u8 slices[I915_MAX_PIPES];
+	u8 enabled_slices;
+	u8 active_pipes;
+	u8 mdclk_cdclk_ratio;
+	bool joined_mbus;
+};
+
 #define to_intel_dbuf_state(global_state) \
 	container_of_const((global_state), struct intel_dbuf_state, base)
 
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index a1993ded034a..87d052b640b3 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -8,17 +8,16 @@
 
 #include <linux/types.h>
 
-#include "intel_display_limits.h"
-#include "intel_global_state.h"
-#include "intel_wm_types.h"
-
+enum plane_id;
 struct intel_atomic_state;
 struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
+struct intel_dbuf_state;
 struct intel_display;
 struct intel_plane;
 struct intel_plane_state;
+struct skl_ddb_entry;
 struct skl_pipe_wm;
 struct skl_wm_level;
 
@@ -63,18 +62,6 @@ unsigned int skl_plane_relative_data_rate(const struct intel_crtc_state *crtc_st
 					  struct intel_plane *plane, int width,
 					  int height, int cpp);
 
-struct intel_dbuf_state {
-	struct intel_global_state base;
-
-	struct skl_ddb_entry ddb[I915_MAX_PIPES];
-	unsigned int weight[I915_MAX_PIPES];
-	u8 slices[I915_MAX_PIPES];
-	u8 enabled_slices;
-	u8 active_pipes;
-	u8 mdclk_cdclk_ratio;
-	bool joined_mbus;
-};
-
 struct intel_dbuf_state *
 intel_atomic_get_dbuf_state(struct intel_atomic_state *state);
 
-- 
2.39.5

[PATCH 04/16] drm/i915/bw: abstract intel_bw_pmdemand_needs_update()

[Jani Nikula]

Add intel_bw_pmdemand_needs_update() helper to avoid looking at struct
intel_bw_state internals outside of intel_bw.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 14 ++++++++++++++
 drivers/gpu/drm/i915/display/intel_bw.h       |  2 ++
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  6 +-----
 3 files changed, 17 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 6c2ab2e0dc91..c077ab05eb61 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1644,3 +1644,17 @@ int intel_bw_init(struct intel_display *display)
 
 	return 0;
 }
+
+bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	const struct intel_bw_state *new_bw_state, *old_bw_state;
+
+	new_bw_state = intel_atomic_get_new_bw_state(state);
+	old_bw_state = intel_atomic_get_old_bw_state(state);
+
+	if (new_bw_state &&
+	    new_bw_state->qgv_point_peakbw != old_bw_state->qgv_point_peakbw)
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index eb2cc883e9c1..0acc6f19c981 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -76,4 +76,6 @@ int intel_bw_min_cdclk(struct intel_display *display,
 void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
+bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
+
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index eeb88f9fc92d..8334744a2e23 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,16 +294,12 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	const struct intel_bw_state *new_bw_state, *old_bw_state;
 	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
 
-	new_bw_state = intel_atomic_get_new_bw_state(state);
-	old_bw_state = intel_atomic_get_old_bw_state(state);
-	if (new_bw_state && new_bw_state->qgv_point_peakbw !=
-	    old_bw_state->qgv_point_peakbw)
+	if (intel_bw_pmdemand_needs_update(state))
 		return true;
 
 	if (intel_dbuf_pmdemand_needs_update(state))
-- 
2.39.5

[PATCH 05/16] drm/i915/bw: relocate intel_can_enable_sagv() and rename to intel_bw_can_enable_sagv()

[Jani Nikula]

Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move intel_can_enable_sagv() there, and
rename to intel_bw_can_enable_sagv() to have consistent naming.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c      | 22 ++++++++++++++------
 drivers/gpu/drm/i915/display/intel_bw.h      |  2 ++
 drivers/gpu/drm/i915/display/skl_watermark.c | 16 +++-----------
 drivers/gpu/drm/i915/display/skl_watermark.h |  3 ---
 4 files changed, 21 insertions(+), 22 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index c077ab05eb61..2e801ef313c8 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -994,7 +994,7 @@ static int mtl_find_qgv_points(struct intel_display *display,
 	 * for qgv peak bw in PM Demand request. So assign UINT_MAX if SAGV is
 	 * not enabled. PM Demand code will clamp the value for the register
 	 */
-	if (!intel_can_enable_sagv(display, new_bw_state)) {
+	if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
 		new_bw_state->qgv_point_peakbw = U16_MAX;
 		drm_dbg_kms(display->drm, "No SAGV, use UINT_MAX as peak bw.");
 		return 0;
@@ -1107,7 +1107,7 @@ static int icl_find_qgv_points(struct intel_display *display,
 	 * we can't enable SAGV due to the increased memory latency it may
 	 * cause.
 	 */
-	if (!intel_can_enable_sagv(display, new_bw_state)) {
+	if (!intel_bw_can_enable_sagv(display, new_bw_state)) {
 		qgv_points = icl_max_bw_qgv_point_mask(display, num_active_planes);
 		drm_dbg_kms(display->drm, "No SAGV, using single QGV point mask 0x%x\n",
 			    qgv_points);
@@ -1474,8 +1474,8 @@ static int intel_bw_check_sagv_mask(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return 0;
 
-	if (intel_can_enable_sagv(display, new_bw_state) !=
-	    intel_can_enable_sagv(display, old_bw_state)) {
+	if (intel_bw_can_enable_sagv(display, new_bw_state) !=
+	    intel_bw_can_enable_sagv(display, old_bw_state)) {
 		ret = intel_atomic_serialize_global_state(&new_bw_state->base);
 		if (ret)
 			return ret;
@@ -1521,8 +1521,8 @@ int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms)
 	new_bw_state = intel_atomic_get_new_bw_state(state);
 
 	if (new_bw_state &&
-	    intel_can_enable_sagv(display, old_bw_state) !=
-	    intel_can_enable_sagv(display, new_bw_state))
+	    intel_bw_can_enable_sagv(display, old_bw_state) !=
+	    intel_bw_can_enable_sagv(display, new_bw_state))
 		changed = true;
 
 	/*
@@ -1658,3 +1658,13 @@ bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state)
 
 	return false;
 }
+
+bool intel_bw_can_enable_sagv(struct intel_display *display,
+			      const struct intel_bw_state *bw_state)
+{
+	if (DISPLAY_VER(display) < 11 &&
+	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
+		return false;
+
+	return bw_state->pipe_sagv_reject == 0;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 0acc6f19c981..ee6e4a7ac89d 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -77,5 +77,7 @@ void intel_bw_update_hw_state(struct intel_display *display);
 void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 
 bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
+bool intel_bw_can_enable_sagv(struct intel_display *display,
+			      const struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 34726895075b..ec2838d641fb 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -252,7 +252,7 @@ static void skl_sagv_pre_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (!intel_can_enable_sagv(display, new_bw_state))
+	if (!intel_bw_can_enable_sagv(display, new_bw_state))
 		skl_sagv_disable(display);
 }
 
@@ -265,7 +265,7 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
 	if (!new_bw_state)
 		return;
 
-	if (intel_can_enable_sagv(display, new_bw_state))
+	if (intel_bw_can_enable_sagv(display, new_bw_state))
 		skl_sagv_enable(display);
 }
 
@@ -466,16 +466,6 @@ bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state)
 		return skl_crtc_can_enable_sagv(crtc_state);
 }
 
-bool intel_can_enable_sagv(struct intel_display *display,
-			   const struct intel_bw_state *bw_state)
-{
-	if (DISPLAY_VER(display) < 11 &&
-	    bw_state->active_pipes && !is_power_of_2(bw_state->active_pipes))
-		return false;
-
-	return bw_state->pipe_sagv_reject == 0;
-}
-
 static u16 skl_ddb_entry_init(struct skl_ddb_entry *entry,
 			      u16 start, u16 end)
 {
@@ -3031,7 +3021,7 @@ skl_compute_wm(struct intel_atomic_state *state)
 		 * drm_atomic_check_only() gets upset if we pull more crtcs
 		 * into the state, so we have to calculate this based on the
 		 * individual intel_crtc_can_enable_sagv() rather than
-		 * the overall intel_can_enable_sagv(). Otherwise the
+		 * the overall intel_bw_can_enable_sagv(). Otherwise the
 		 * crtcs not included in the commit would not switch to the
 		 * SAGV watermarks when we are about to enable SAGV, and that
 		 * would lead to underruns. This does mean extra power draw
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.h b/drivers/gpu/drm/i915/display/skl_watermark.h
index 87d052b640b3..62790816f030 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.h
+++ b/drivers/gpu/drm/i915/display/skl_watermark.h
@@ -10,7 +10,6 @@
 
 enum plane_id;
 struct intel_atomic_state;
-struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_dbuf_state;
@@ -26,8 +25,6 @@ u8 intel_enabled_dbuf_slices_mask(struct intel_display *display);
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state);
 void intel_sagv_post_plane_update(struct intel_atomic_state *state);
 bool intel_crtc_can_enable_sagv(const struct intel_crtc_state *crtc_state);
-bool intel_can_enable_sagv(struct intel_display *display,
-			   const struct intel_bw_state *bw_state);
 bool intel_has_sagv(struct intel_display *display);
 
 u32 skl_ddb_dbuf_slice_mask(struct intel_display *display,
-- 
2.39.5

[PATCH 06/16] drm/i915: move icl_sagv_{pre, post}_plane_update() to intel_bw.c

[Jani Nikula]

Prefer only looking at struct intel_bw_state internals inside
intel_bw.c. To that effect, move icl_sagv_{pre,post}_plane_update()
there.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c      | 68 +++++++++++++++++++-
 drivers/gpu/drm/i915/display/intel_bw.h      |  4 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 64 ------------------
 3 files changed, 68 insertions(+), 68 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 2e801ef313c8..05cb1bd65ee0 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -154,8 +154,8 @@ static bool is_sagv_enabled(struct intel_display *display, u16 points_mask)
 			      ICL_PCODE_REQ_QGV_PT_MASK);
 }
 
-int icl_pcode_restrict_qgv_points(struct intel_display *display,
-				  u32 points_mask)
+static int icl_pcode_restrict_qgv_points(struct intel_display *display,
+					 u32 points_mask)
 {
 	struct drm_i915_private *i915 = to_i915(display->drm);
 	int ret;
@@ -974,6 +974,70 @@ static void icl_force_disable_sagv(struct intel_display *display,
 	icl_pcode_restrict_qgv_points(display, bw_state->qgv_points_mask);
 }
 
+void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_bw_state *old_bw_state =
+		intel_atomic_get_old_bw_state(state);
+	const struct intel_bw_state *new_bw_state =
+		intel_atomic_get_new_bw_state(state);
+	u16 old_mask, new_mask;
+
+	if (!new_bw_state)
+		return;
+
+	old_mask = old_bw_state->qgv_points_mask;
+	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+
+	if (old_mask == new_mask)
+		return;
+
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
+	/*
+	 * Restrict required qgv points before updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(display, new_mask);
+}
+
+void icl_sagv_post_plane_update(struct intel_atomic_state *state)
+{
+	struct intel_display *display = to_intel_display(state);
+	const struct intel_bw_state *old_bw_state =
+		intel_atomic_get_old_bw_state(state);
+	const struct intel_bw_state *new_bw_state =
+		intel_atomic_get_new_bw_state(state);
+	u16 old_mask, new_mask;
+
+	if (!new_bw_state)
+		return;
+
+	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
+	new_mask = new_bw_state->qgv_points_mask;
+
+	if (old_mask == new_mask)
+		return;
+
+	WARN_ON(!new_bw_state->base.changed);
+
+	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
+		    old_mask, new_mask);
+
+	/*
+	 * Allow required qgv points after updating the configuration.
+	 * According to BSpec we can't mask and unmask qgv points at the same
+	 * time. Also masking should be done before updating the configuration
+	 * and unmasking afterwards.
+	 */
+	icl_pcode_restrict_qgv_points(display, new_mask);
+}
+
 static int mtl_find_qgv_points(struct intel_display *display,
 			       unsigned int data_rate,
 			       unsigned int num_active_planes,
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index ee6e4a7ac89d..68b95c2a0cb9 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -67,8 +67,6 @@ intel_atomic_get_bw_state(struct intel_atomic_state *state);
 void intel_bw_init_hw(struct intel_display *display);
 int intel_bw_init(struct intel_display *display);
 int intel_bw_atomic_check(struct intel_atomic_state *state, bool any_ms);
-int icl_pcode_restrict_qgv_points(struct intel_display *display,
-				  u32 points_mask);
 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 			    bool *need_cdclk_calc);
 int intel_bw_min_cdclk(struct intel_display *display,
@@ -79,5 +77,7 @@ void intel_bw_crtc_disable_noatomic(struct intel_crtc *crtc);
 bool intel_bw_pmdemand_needs_update(struct intel_atomic_state *state);
 bool intel_bw_can_enable_sagv(struct intel_display *display,
 			      const struct intel_bw_state *bw_state);
+void icl_sagv_pre_plane_update(struct intel_atomic_state *state);
+void icl_sagv_post_plane_update(struct intel_atomic_state *state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index ec2838d641fb..95515d69ad68 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -269,70 +269,6 @@ static void skl_sagv_post_plane_update(struct intel_atomic_state *state)
 		skl_sagv_enable(display);
 }
 
-static void icl_sagv_pre_plane_update(struct intel_atomic_state *state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_bw_state *old_bw_state =
-		intel_atomic_get_old_bw_state(state);
-	const struct intel_bw_state *new_bw_state =
-		intel_atomic_get_new_bw_state(state);
-	u16 old_mask, new_mask;
-
-	if (!new_bw_state)
-		return;
-
-	old_mask = old_bw_state->qgv_points_mask;
-	new_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
-
-	if (old_mask == new_mask)
-		return;
-
-	WARN_ON(!new_bw_state->base.changed);
-
-	drm_dbg_kms(display->drm, "Restricting QGV points: 0x%x -> 0x%x\n",
-		    old_mask, new_mask);
-
-	/*
-	 * Restrict required qgv points before updating the configuration.
-	 * According to BSpec we can't mask and unmask qgv points at the same
-	 * time. Also masking should be done before updating the configuration
-	 * and unmasking afterwards.
-	 */
-	icl_pcode_restrict_qgv_points(display, new_mask);
-}
-
-static void icl_sagv_post_plane_update(struct intel_atomic_state *state)
-{
-	struct intel_display *display = to_intel_display(state);
-	const struct intel_bw_state *old_bw_state =
-		intel_atomic_get_old_bw_state(state);
-	const struct intel_bw_state *new_bw_state =
-		intel_atomic_get_new_bw_state(state);
-	u16 old_mask, new_mask;
-
-	if (!new_bw_state)
-		return;
-
-	old_mask = old_bw_state->qgv_points_mask | new_bw_state->qgv_points_mask;
-	new_mask = new_bw_state->qgv_points_mask;
-
-	if (old_mask == new_mask)
-		return;
-
-	WARN_ON(!new_bw_state->base.changed);
-
-	drm_dbg_kms(display->drm, "Relaxing QGV points: 0x%x -> 0x%x\n",
-		    old_mask, new_mask);
-
-	/*
-	 * Allow required qgv points after updating the configuration.
-	 * According to BSpec we can't mask and unmask qgv points at the same
-	 * time. Also masking should be done before updating the configuration
-	 * and unmasking afterwards.
-	 */
-	icl_pcode_restrict_qgv_points(display, new_mask);
-}
-
 void intel_sagv_pre_plane_update(struct intel_atomic_state *state)
 {
 	struct intel_display *display = to_intel_display(state);
-- 
2.39.5

[PATCH 07/16] drm/i915/bw: abstract intel_bw_qgv_point_peakbw()

[Jani Nikula]

Add intel_bw_qgv_point_peakbw() helper to avoid looking at struct
intel_bw_state internals outside of intel_bw.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c       | 5 +++++
 drivers/gpu/drm/i915/display/intel_bw.h       | 1 +
 drivers/gpu/drm/i915/display/intel_pmdemand.c | 2 +-
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 05cb1bd65ee0..65718e6b5333 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1732,3 +1732,8 @@ bool intel_bw_can_enable_sagv(struct intel_display *display,
 
 	return bw_state->pipe_sagv_reject == 0;
 }
+
+int intel_bw_qgv_point_peakbw(const struct intel_bw_state *bw_state)
+{
+	return bw_state->qgv_point_peakbw;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 68b95c2a0cb9..7728dc86a31a 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -79,5 +79,6 @@ bool intel_bw_can_enable_sagv(struct intel_display *display,
 			      const struct intel_bw_state *bw_state);
 void icl_sagv_pre_plane_update(struct intel_atomic_state *state);
 void icl_sagv_post_plane_update(struct intel_atomic_state *state);
+int intel_bw_qgv_point_peakbw(const struct intel_bw_state *bw_state);
 
 #endif /* __INTEL_BW_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 8334744a2e23..a4d53fd94489 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -346,7 +346,7 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 
 	/* firmware will calculate the qclk_gv_index, requirement is set to 0 */
 	new_pmdemand_state->params.qclk_gv_index = 0;
-	new_pmdemand_state->params.qclk_gv_bw = new_bw_state->qgv_point_peakbw;
+	new_pmdemand_state->params.qclk_gv_bw = intel_bw_qgv_point_peakbw(new_bw_state);
 
 	new_dbuf_state = intel_atomic_get_dbuf_state(state);
 	if (IS_ERR(new_dbuf_state))
-- 
2.39.5

[PATCH 08/16] drm/i915/bw: make struct intel_bw_state opaque

[Jani Nikula]

With all the code touching struct intel_bw_state moved inside
intel_bw.c, we move the struct definition there too, and make the type
opaque. to_intel_bw_state() needs to be turned into a proper
function. All of this nicely reduces includes from intel_bw.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c | 40 ++++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_bw.h | 44 ++-----------------------
 2 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 65718e6b5333..67c54c144274 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -20,6 +20,41 @@
 #include "intel_pcode.h"
 #include "skl_watermark.h"
 
+struct intel_dbuf_bw {
+	unsigned int max_bw[I915_MAX_DBUF_SLICES];
+	u8 active_planes[I915_MAX_DBUF_SLICES];
+};
+
+struct intel_bw_state {
+	struct intel_global_state base;
+	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
+
+	/*
+	 * Contains a bit mask, used to determine, whether correspondent
+	 * pipe allows SAGV or not.
+	 */
+	u8 pipe_sagv_reject;
+
+	/* bitmask of active pipes */
+	u8 active_pipes;
+
+	/*
+	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
+	 * the selected QGV point as the parameter in multiples of 100MB/s
+	 */
+	u16 qgv_point_peakbw;
+
+	/*
+	 * Current QGV points mask, which restricts
+	 * some particular SAGV states, not to confuse
+	 * with pipe_sagv_mask.
+	 */
+	u16 qgv_points_mask;
+
+	unsigned int data_rate[I915_MAX_PIPES];
+	u8 num_active_planes[I915_MAX_PIPES];
+};
+
 /* Parameters for Qclk Geyserville (QGV) */
 struct intel_qgv_point {
 	u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
@@ -865,6 +900,11 @@ static unsigned int intel_bw_data_rate(struct intel_display *display,
 	return data_rate;
 }
 
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state)
+{
+	return container_of(obj_state, struct intel_bw_state, base);
+}
+
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
 {
diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h
index 7728dc86a31a..d51f50c9d302 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.h
+++ b/drivers/gpu/drm/i915/display/intel_bw.h
@@ -8,52 +8,14 @@
 
 #include <drm/drm_atomic.h>
 
-#include "intel_display_limits.h"
-#include "intel_display_power.h"
-#include "intel_global_state.h"
-
 struct intel_atomic_state;
+struct intel_bw_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
+struct intel_global_state;
 
-struct intel_dbuf_bw {
-	unsigned int max_bw[I915_MAX_DBUF_SLICES];
-	u8 active_planes[I915_MAX_DBUF_SLICES];
-};
-
-struct intel_bw_state {
-	struct intel_global_state base;
-	struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES];
-
-	/*
-	 * Contains a bit mask, used to determine, whether correspondent
-	 * pipe allows SAGV or not.
-	 */
-	u8 pipe_sagv_reject;
-
-	/* bitmask of active pipes */
-	u8 active_pipes;
-
-	/*
-	 * From MTL onwards, to lock a QGV point, punit expects the peak BW of
-	 * the selected QGV point as the parameter in multiples of 100MB/s
-	 */
-	u16 qgv_point_peakbw;
-
-	/*
-	 * Current QGV points mask, which restricts
-	 * some particular SAGV states, not to confuse
-	 * with pipe_sagv_mask.
-	 */
-	u16 qgv_points_mask;
-
-	unsigned int data_rate[I915_MAX_PIPES];
-	u8 num_active_planes[I915_MAX_PIPES];
-};
-
-#define to_intel_bw_state(global_state) \
-	container_of_const((global_state), struct intel_bw_state, base)
+struct intel_bw_state *to_intel_bw_state(struct intel_global_state *obj_state);
 
 struct intel_bw_state *
 intel_atomic_get_old_bw_state(struct intel_atomic_state *state);
-- 
2.39.5

[PATCH 09/16] drm/i915/cdclk: abstract intel_cdclk_logical()

[Jani Nikula]

Add intel_cdclk_logical() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/hsw_ips.c       | 2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c   | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h   | 2 ++
 drivers/gpu/drm/i915/display/intel_display.c | 2 +-
 drivers/gpu/drm/i915/display/intel_fbc.c     | 2 +-
 drivers/gpu/drm/i915/display/skl_watermark.c | 2 +-
 6 files changed, 11 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/hsw_ips.c b/drivers/gpu/drm/i915/display/hsw_ips.c
index 0d33782f11be..35a1e17ec82b 100644
--- a/drivers/gpu/drm/i915/display/hsw_ips.c
+++ b/drivers/gpu/drm/i915/display/hsw_ips.c
@@ -268,7 +268,7 @@ int hsw_ips_compute_config(struct intel_atomic_state *state,
 			return PTR_ERR(cdclk_state);
 
 		/* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
-		if (crtc_state->pixel_rate > cdclk_state->logical.cdclk * 95 / 100)
+		if (crtc_state->pixel_rate > intel_cdclk_logical(cdclk_state) * 95 / 100)
 			return 0;
 	}
 
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 38b3094b37d7..5082d2b64ce5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3837,3 +3837,8 @@ void intel_init_cdclk_hooks(struct intel_display *display)
 		     "Unknown platform. Assuming i830\n"))
 		display->funcs.cdclk = &i830_cdclk_funcs;
 }
+
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->logical.cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index a1cefd455d92..20a66f613072 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -97,4 +97,6 @@ void intel_cdclk_crtc_disable_noatomic(struct intel_crtc *crtc);
 int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
+int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index b0c7c46ffbe2..aa01e48b23f5 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4160,7 +4160,7 @@ static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
 		return 0;
 
 	linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
-					cdclk_state->logical.cdclk);
+					intel_cdclk_logical(cdclk_state));
 
 	return min(linetime_wm, 0x1ff);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_fbc.c b/drivers/gpu/drm/i915/display/intel_fbc.c
index ec1ef8694c35..5d28a6062db1 100644
--- a/drivers/gpu/drm/i915/display/intel_fbc.c
+++ b/drivers/gpu/drm/i915/display/intel_fbc.c
@@ -1576,7 +1576,7 @@ static int intel_fbc_check_plane(struct intel_atomic_state *state,
 		if (IS_ERR(cdclk_state))
 			return PTR_ERR(cdclk_state);
 
-		if (crtc_state->pixel_rate >= cdclk_state->logical.cdclk * 95 / 100) {
+		if (crtc_state->pixel_rate >= intel_cdclk_logical(cdclk_state) * 95 / 100) {
 			plane_state->no_fbc_reason = "pixel rate too high";
 			return 0;
 		}
diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c
index 95515d69ad68..e1e23247d2be 100644
--- a/drivers/gpu/drm/i915/display/skl_watermark.c
+++ b/drivers/gpu/drm/i915/display/skl_watermark.c
@@ -2182,7 +2182,7 @@ cdclk_prefill_adjustment(const struct intel_crtc_state *crtc_state)
 	}
 
 	return min(1, DIV_ROUND_UP(crtc_state->pixel_rate,
-				   2 * cdclk_state->logical.cdclk));
+				   2 * intel_cdclk_logical(cdclk_state)));
 }
 
 static int
-- 
2.39.5

[PATCH 10/16] drm/i915/cdclk: abstract intel_cdclk_min_cdclk()

[Jani Nikula]

Add intel_cdclk_min_cdclk() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_atomic_plane.c | 4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c        | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h        | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_atomic_plane.c b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
index 15ede7678636..1e9b906c3e44 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic_plane.c
@@ -333,7 +333,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 	 * display blinking due to constant cdclk changes.
 	 */
 	if (new_crtc_state->min_cdclk[plane->id] <=
-	    cdclk_state->min_cdclk[crtc->pipe])
+	    intel_cdclk_min_cdclk(cdclk_state, crtc->pipe))
 		return 0;
 
 	drm_dbg_kms(display->drm,
@@ -341,7 +341,7 @@ int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 		    plane->base.base.id, plane->base.name,
 		    new_crtc_state->min_cdclk[plane->id],
 		    crtc->base.base.id, crtc->base.name,
-		    cdclk_state->min_cdclk[crtc->pipe]);
+		    intel_cdclk_min_cdclk(cdclk_state, crtc->pipe));
 	*need_cdclk_calc = true;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 5082d2b64ce5..05e94fcd8326 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3842,3 +3842,8 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state)
 {
 	return cdclk_state->logical.cdclk;
 }
+
+int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe)
+{
+	return cdclk_state->min_cdclk[pipe];
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 20a66f613072..ef6ad9d04c20 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -98,5 +98,6 @@ int intel_cdclk_init(struct intel_display *display);
 void intel_cdclk_debugfs_register(struct intel_display *display);
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
+int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 
 #endif /* __INTEL_CDCLK_H__ */
-- 
2.39.5

[PATCH 11/16] drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()

[Jani Nikula]

Add intel_cdclk_bw_min_cdclk() helper to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_bw.c    | 4 ++--
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c
index 67c54c144274..306a13ef8b35 100644
--- a/drivers/gpu/drm/i915/display/intel_bw.c
+++ b/drivers/gpu/drm/i915/display/intel_bw.c
@@ -1461,12 +1461,12 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 	 * requirements. This can reduce back and forth
 	 * display blinking due to constant cdclk changes.
 	 */
-	if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
+	if (new_min_cdclk <= intel_cdclk_bw_min_cdclk(cdclk_state))
 		return 0;
 
 	drm_dbg_kms(display->drm,
 		    "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
-		    new_min_cdclk, cdclk_state->bw_min_cdclk);
+		    new_min_cdclk, intel_cdclk_bw_min_cdclk(cdclk_state));
 	*need_cdclk_calc = true;
 
 	return 0;
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 05e94fcd8326..59d126e1b12a 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3847,3 +3847,8 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
 {
 	return cdclk_state->min_cdclk[pipe];
 }
+
+int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->bw_min_cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index ef6ad9d04c20..fe1a1f1c1900 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -99,5 +99,6 @@ void intel_cdclk_debugfs_register(struct intel_display *display);
 
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
+int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 
 #endif /* __INTEL_CDCLK_H__ */
-- 
2.39.5

[PATCH 12/16] drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()

[Jani Nikula]

Add intel_cdclk_pmdemand_needs_update() helper to avoid looking at
struct intel_cdclk_state internals outside of intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 15 +++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  1 +
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  9 +--------
 3 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 59d126e1b12a..ed6c407f66c7 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3852,3 +3852,18 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state)
 {
 	return cdclk_state->bw_min_cdclk;
 }
+
+bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
+{
+	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
+
+	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
+	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
+
+	if (new_cdclk_state &&
+	    (new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk ||
+	     new_cdclk_state->actual.voltage_level != old_cdclk_state->actual.voltage_level))
+		return true;
+
+	return false;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index fe1a1f1c1900..8527a6e44ee5 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -100,5 +100,6 @@ void intel_cdclk_debugfs_register(struct intel_display *display);
 int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
+bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index a4d53fd94489..16ef68ef4041 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -294,7 +294,6 @@ intel_pmdemand_connector_needs_update(struct intel_atomic_state *state)
 
 static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 {
-	const struct intel_cdclk_state *new_cdclk_state, *old_cdclk_state;
 	const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
 	struct intel_crtc *crtc;
 	int i;
@@ -305,13 +304,7 @@ static bool intel_pmdemand_needs_update(struct intel_atomic_state *state)
 	if (intel_dbuf_pmdemand_needs_update(state))
 		return true;
 
-	new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
-	old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
-	if (new_cdclk_state &&
-	    (new_cdclk_state->actual.cdclk !=
-	     old_cdclk_state->actual.cdclk ||
-	     new_cdclk_state->actual.voltage_level !=
-	     old_cdclk_state->actual.voltage_level))
+	if (intel_cdclk_pmdemand_needs_update(state))
 		return true;
 
 	for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
-- 
2.39.5

[PATCH 13/16] drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()

[Jani Nikula]

Add intel_cdclk_force_min_cdclk() helper to avoid modifying struct
intel_cdclk_state internals outside of intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_audio.c | 2 +-
 drivers/gpu/drm/i915/display/intel_cdclk.c | 5 +++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 1 +
 3 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_audio.c b/drivers/gpu/drm/i915/display/intel_audio.c
index 55af3a553c58..5bdaef38f13d 100644
--- a/drivers/gpu/drm/i915/display/intel_audio.c
+++ b/drivers/gpu/drm/i915/display/intel_audio.c
@@ -951,7 +951,7 @@ static int glk_force_audio_cdclk_commit(struct intel_atomic_state *state,
 	if (IS_ERR(cdclk_state))
 		return PTR_ERR(cdclk_state);
 
-	cdclk_state->force_min_cdclk = enable ? 2 * 96000 : 0;
+	intel_cdclk_force_min_cdclk(cdclk_state, enable ? 2 * 96000 : 0);
 
 	return drm_atomic_commit(&state->base);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index ed6c407f66c7..f63b6b3b5476 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3867,3 +3867,8 @@ bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state)
 
 	return false;
 }
+
+void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk)
+{
+	cdclk_state->force_min_cdclk = force_min_cdclk;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 8527a6e44ee5..ff10ed526bd4 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -101,5 +101,6 @@ int intel_cdclk_logical(const struct intel_cdclk_state *cdclk_state);
 int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe pipe);
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
+void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 
 #endif /* __INTEL_CDCLK_H__ */
-- 
2.39.5

[PATCH 14/16] drm/i915/cdclk: abstract intel_cdclk_read_hw()

[Jani Nikula]

Add intel_cdclk_read_hw() function to avoid looking at struct
intel_cdclk_state internals outside of intel_cdclk.c.

intel_cdclk_init_hw() would be a better name, but we already have that.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c          | 12 ++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h          |  1 +
 drivers/gpu/drm/i915/display/intel_display_driver.c |  8 +-------
 3 files changed, 14 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index f63b6b3b5476..994be1d0e20c 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3872,3 +3872,15 @@ void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int forc
 {
 	cdclk_state->force_min_cdclk = force_min_cdclk;
 }
+
+void intel_cdclk_read_hw(struct intel_display *display)
+{
+	struct intel_cdclk_state *cdclk_state;
+
+	cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
+
+	intel_update_cdclk(display);
+	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
+	cdclk_state->actual = display->cdclk.hw;
+	cdclk_state->logical = display->cdclk.hw;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index ff10ed526bd4..0d5ee1826168 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -102,5 +102,6 @@ int intel_cdclk_min_cdclk(const struct intel_cdclk_state *cdclk_state, enum pipe
 int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
+void intel_cdclk_read_hw(struct intel_display *display);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_driver.c b/drivers/gpu/drm/i915/display/intel_display_driver.c
index ec799a1773e4..9058c23dd487 100644
--- a/drivers/gpu/drm/i915/display/intel_display_driver.c
+++ b/drivers/gpu/drm/i915/display/intel_display_driver.c
@@ -84,16 +84,10 @@ bool intel_display_driver_probe_defer(struct pci_dev *pdev)
 
 void intel_display_driver_init_hw(struct intel_display *display)
 {
-	struct intel_cdclk_state *cdclk_state;
-
 	if (!HAS_DISPLAY(display))
 		return;
 
-	cdclk_state = to_intel_cdclk_state(display->cdclk.obj.state);
-
-	intel_update_cdclk(display);
-	intel_cdclk_dump_config(display, &display->cdclk.hw, "Current CDCLK");
-	cdclk_state->logical = cdclk_state->actual = display->cdclk.hw;
+	intel_cdclk_read_hw(display);
 
 	intel_display_wa_apply(display);
 }
-- 
2.39.5

[PATCH 15/16] drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()

[Jani Nikula]

Add intel_cdclk_actual() and intel_cdclk_actual_voltage_level() helpers
to avoid looking at struct intel_cdclk_state internals outside of
intel_cdclk.c.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c    | 10 ++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h    |  2 ++
 drivers/gpu/drm/i915/display/intel_pmdemand.c |  4 ++--
 3 files changed, 14 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 994be1d0e20c..2e8abf237bd1 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -3884,3 +3884,13 @@ void intel_cdclk_read_hw(struct intel_display *display)
 	cdclk_state->actual = display->cdclk.hw;
 	cdclk_state->logical = display->cdclk.hw;
 }
+
+int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->actual.cdclk;
+}
+
+int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
+{
+	return cdclk_state->actual.voltage_level;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index 0d5ee1826168..f38605c6ab72 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -103,5 +103,7 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
 bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
 void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
 void intel_cdclk_read_hw(struct intel_display *display);
+int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
+int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
 
 #endif /* __INTEL_CDCLK_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
index 16ef68ef4041..d806c15db7ce 100644
--- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
+++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
@@ -360,9 +360,9 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
 		return PTR_ERR(new_cdclk_state);
 
 	new_pmdemand_state->params.voltage_index =
-		new_cdclk_state->actual.voltage_level;
+		intel_cdclk_actual_voltage_level(new_cdclk_state);
 	new_pmdemand_state->params.cdclk_freq_mhz =
-		DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
+		DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);
 
 	intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
 
-- 
2.39.5

Re: [PATCH 15/16] drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()

[Imre Deak]

On Thu, Jun 12, 2025 at 03:12:10PM +0300, Jani Nikula wrote:
> Add intel_cdclk_actual() and intel_cdclk_actual_voltage_level() helpers
> to avoid looking at struct intel_cdclk_state internals outside of
> intel_cdclk.c.
> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 10 ++++++++++
>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  2 ++
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  4 ++--
>  3 files changed, 14 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> index 994be1d0e20c..2e8abf237bd1 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> @@ -3884,3 +3884,13 @@ void intel_cdclk_read_hw(struct intel_display *display)
>  	cdclk_state->actual = display->cdclk.hw;
>  	cdclk_state->logical = display->cdclk.hw;
>  }
> +
> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
> +{
> +	return cdclk_state->actual.cdclk;
> +}
> +
> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
> +{
> +	return cdclk_state->actual.voltage_level;
> +}

These could've been grouped better after intel_cdclk_logical().

I wondered if it'd make sense to use
intel_cdclk_{logical,actual}_cdclk() instead of 
intel_cdclk_{logical,actual}().

Or *_clock() instead of *_cdclk() in the above and other helpers.

> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> index 0d5ee1826168..f38605c6ab72 100644
> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> @@ -103,5 +103,7 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
>  bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
>  void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
>  void intel_cdclk_read_hw(struct intel_display *display);
> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
>  
>  #endif /* __INTEL_CDCLK_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> index 16ef68ef4041..d806c15db7ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> @@ -360,9 +360,9 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
>  		return PTR_ERR(new_cdclk_state);
>  
>  	new_pmdemand_state->params.voltage_index =
> -		new_cdclk_state->actual.voltage_level;
> +		intel_cdclk_actual_voltage_level(new_cdclk_state);
>  	new_pmdemand_state->params.cdclk_freq_mhz =
> -		DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
> +		DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);
>  
>  	intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
>  
> -- 
> 2.39.5
> 

Re: [PATCH 15/16] drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()

[Jani Nikula]

On Wed, 18 Jun 2025, Imre Deak <imre.deak@intel.com> wrote:
> On Thu, Jun 12, 2025 at 03:12:10PM +0300, Jani Nikula wrote:
>> Add intel_cdclk_actual() and intel_cdclk_actual_voltage_level() helpers
>> to avoid looking at struct intel_cdclk_state internals outside of
>> intel_cdclk.c.
>> 
>> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
>> ---
>>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 10 ++++++++++
>>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  2 ++
>>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  4 ++--
>>  3 files changed, 14 insertions(+), 2 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> index 994be1d0e20c..2e8abf237bd1 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
>> @@ -3884,3 +3884,13 @@ void intel_cdclk_read_hw(struct intel_display *display)
>>  	cdclk_state->actual = display->cdclk.hw;
>>  	cdclk_state->logical = display->cdclk.hw;
>>  }
>> +
>> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
>> +{
>> +	return cdclk_state->actual.cdclk;
>> +}
>> +
>> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
>> +{
>> +	return cdclk_state->actual.voltage_level;
>> +}
>
> These could've been grouped better after intel_cdclk_logical().

Yes, changing that.

> I wondered if it'd make sense to use
> intel_cdclk_{logical,actual}_cdclk() instead of 
> intel_cdclk_{logical,actual}().

Mmh. I dislike the repetition, "cdclk logical cdclk"...

> Or *_clock() instead of *_cdclk() in the above and other helpers.

...so I set out to consistently use "clock", but then it didn't feel
right for things like "intel_cdclk_min_cdclk" because it's then compared
against min_cdclk in a number of places.

I don't know, leave it as it is now in the patches?

BR,
Jani.



>
>> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> index 0d5ee1826168..f38605c6ab72 100644
>> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
>> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
>> @@ -103,5 +103,7 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
>>  bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
>>  void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
>>  void intel_cdclk_read_hw(struct intel_display *display);
>> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
>> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
>>  
>>  #endif /* __INTEL_CDCLK_H__ */
>> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> index 16ef68ef4041..d806c15db7ce 100644
>> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
>> @@ -360,9 +360,9 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
>>  		return PTR_ERR(new_cdclk_state);
>>  
>>  	new_pmdemand_state->params.voltage_index =
>> -		new_cdclk_state->actual.voltage_level;
>> +		intel_cdclk_actual_voltage_level(new_cdclk_state);
>>  	new_pmdemand_state->params.cdclk_freq_mhz =
>> -		DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
>> +		DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);
>>  
>>  	intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
>>  
>> -- 
>> 2.39.5
>> 

-- 
Jani Nikula, Intel

Re: [PATCH 15/16] drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()

[Imre Deak]

On Thu, Jun 19, 2025 at 01:11:32PM +0300, Jani Nikula wrote:
> On Wed, 18 Jun 2025, Imre Deak <imre.deak@intel.com> wrote:
> > On Thu, Jun 12, 2025 at 03:12:10PM +0300, Jani Nikula wrote:
> >> Add intel_cdclk_actual() and intel_cdclk_actual_voltage_level() helpers
> >> to avoid looking at struct intel_cdclk_state internals outside of
> >> intel_cdclk.c.
> >> 
> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> >> ---
> >>  drivers/gpu/drm/i915/display/intel_cdclk.c    | 10 ++++++++++
> >>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  2 ++
> >>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  4 ++--
> >>  3 files changed, 14 insertions(+), 2 deletions(-)
> >> 
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> index 994be1d0e20c..2e8abf237bd1 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
> >> @@ -3884,3 +3884,13 @@ void intel_cdclk_read_hw(struct intel_display *display)
> >>  	cdclk_state->actual = display->cdclk.hw;
> >>  	cdclk_state->logical = display->cdclk.hw;
> >>  }
> >> +
> >> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state)
> >> +{
> >> +	return cdclk_state->actual.cdclk;
> >> +}
> >> +
> >> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state)
> >> +{
> >> +	return cdclk_state->actual.voltage_level;
> >> +}
> >
> > These could've been grouped better after intel_cdclk_logical().
> 
> Yes, changing that.
> 
> > I wondered if it'd make sense to use
> > intel_cdclk_{logical,actual}_cdclk() instead of 
> > intel_cdclk_{logical,actual}().
> 
> Mmh. I dislike the repetition, "cdclk logical cdclk"...

Yes, though there's already intel_cdclk_min_cdclk() anyway.

> > Or *_clock() instead of *_cdclk() in the above and other helpers.
> 
> ...so I set out to consistently use "clock", but then it didn't feel
> right for things like "intel_cdclk_min_cdclk" because it's then compared
> against min_cdclk in a number of places.
> 
> I don't know, leave it as it is now in the patches?

I only pointed this out since intel_cdclk_actual() is strange wrt.
intel_cdclk_actual_voltage_level() for instace. But sure, this is not a
big deal.

> 
> BR,
> Jani.
> 
> 
> 
> >
> >> diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >> index 0d5ee1826168..f38605c6ab72 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_cdclk.h
> >> +++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
> >> @@ -103,5 +103,7 @@ int intel_cdclk_bw_min_cdclk(const struct intel_cdclk_state *cdclk_state);
> >>  bool intel_cdclk_pmdemand_needs_update(struct intel_atomic_state *state);
> >>  void intel_cdclk_force_min_cdclk(struct intel_cdclk_state *cdclk_state, int force_min_cdclk);
> >>  void intel_cdclk_read_hw(struct intel_display *display);
> >> +int intel_cdclk_actual(const struct intel_cdclk_state *cdclk_state);
> >> +int intel_cdclk_actual_voltage_level(const struct intel_cdclk_state *cdclk_state);
> >>  
> >>  #endif /* __INTEL_CDCLK_H__ */
> >> diff --git a/drivers/gpu/drm/i915/display/intel_pmdemand.c b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> index 16ef68ef4041..d806c15db7ce 100644
> >> --- a/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> +++ b/drivers/gpu/drm/i915/display/intel_pmdemand.c
> >> @@ -360,9 +360,9 @@ int intel_pmdemand_atomic_check(struct intel_atomic_state *state)
> >>  		return PTR_ERR(new_cdclk_state);
> >>  
> >>  	new_pmdemand_state->params.voltage_index =
> >> -		new_cdclk_state->actual.voltage_level;
> >> +		intel_cdclk_actual_voltage_level(new_cdclk_state);
> >>  	new_pmdemand_state->params.cdclk_freq_mhz =
> >> -		DIV_ROUND_UP(new_cdclk_state->actual.cdclk, 1000);
> >> +		DIV_ROUND_UP(intel_cdclk_actual(new_cdclk_state), 1000);
> >>  
> >>  	intel_pmdemand_update_max_ddiclk(display, state, new_pmdemand_state);
> >>  
> >> -- 
> >> 2.39.5
> >> 
> 
> -- 
> Jani Nikula, Intel

[PATCH 16/16] drm/i915/cdclk: make struct intel_cdclk_state opaque

[Jani Nikula]

With all the code touching struct intel_cdclk_state moved inside
intel_cdclk.c, we move the struct definition there too, and make the
type opaque. This nicely reduces includes from intel_cdclk.h.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 36 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_cdclk.h | 41 ++--------------------
 2 files changed, 38 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 2e8abf237bd1..ad7a6a53a082 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -114,6 +114,42 @@
  * dividers can be programmed correctly.
  */
 
+struct intel_cdclk_state {
+	struct intel_global_state base;
+
+	/*
+	 * Logical configuration of cdclk (used for all scaling,
+	 * watermark, etc. calculations and checks). This is
+	 * computed as if all enabled crtcs were active.
+	 */
+	struct intel_cdclk_config logical;
+
+	/*
+	 * Actual configuration of cdclk, can be different from the
+	 * logical configuration only when all crtc's are DPMS off.
+	 */
+	struct intel_cdclk_config actual;
+
+	/* minimum acceptable cdclk to satisfy bandwidth requirements */
+	int bw_min_cdclk;
+	/* minimum acceptable cdclk for each pipe */
+	int min_cdclk[I915_MAX_PIPES];
+	/* minimum acceptable voltage level for each pipe */
+	u8 min_voltage_level[I915_MAX_PIPES];
+
+	/* pipe to which cd2x update is synchronized */
+	enum pipe pipe;
+
+	/* forced minimum cdclk for glk+ audio w/a */
+	int force_min_cdclk;
+
+	/* bitmask of active pipes */
+	u8 active_pipes;
+
+	/* update cdclk with pipes disabled */
+	bool disable_pipes;
+};
+
 struct intel_cdclk_funcs {
 	void (*get_cdclk)(struct intel_display *display,
 			  struct intel_cdclk_config *cdclk_config);
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.h b/drivers/gpu/drm/i915/display/intel_cdclk.h
index f38605c6ab72..4a2821bf6c65 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.h
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.h
@@ -8,10 +8,9 @@
 
 #include <linux/types.h>
 
-#include "intel_display_limits.h"
-#include "intel_global_state.h"
-
+enum pipe;
 struct intel_atomic_state;
+struct intel_cdclk_state;
 struct intel_crtc;
 struct intel_crtc_state;
 struct intel_display;
@@ -23,42 +22,6 @@ struct intel_cdclk_config {
 	bool joined_mbus;
 };
 
-struct intel_cdclk_state {
-	struct intel_global_state base;
-
-	/*
-	 * Logical configuration of cdclk (used for all scaling,
-	 * watermark, etc. calculations and checks). This is
-	 * computed as if all enabled crtcs were active.
-	 */
-	struct intel_cdclk_config logical;
-
-	/*
-	 * Actual configuration of cdclk, can be different from the
-	 * logical configuration only when all crtc's are DPMS off.
-	 */
-	struct intel_cdclk_config actual;
-
-	/* minimum acceptable cdclk to satisfy bandwidth requirements */
-	int bw_min_cdclk;
-	/* minimum acceptable cdclk for each pipe */
-	int min_cdclk[I915_MAX_PIPES];
-	/* minimum acceptable voltage level for each pipe */
-	u8 min_voltage_level[I915_MAX_PIPES];
-
-	/* pipe to which cd2x update is synchronized */
-	enum pipe pipe;
-
-	/* forced minimum cdclk for glk+ audio w/a */
-	int force_min_cdclk;
-
-	/* bitmask of active pipes */
-	u8 active_pipes;
-
-	/* update cdclk with pipes disabled */
-	bool disable_pipes;
-};
-
 void intel_cdclk_init_hw(struct intel_display *display);
 void intel_cdclk_uninit_hw(struct intel_display *display);
 void intel_init_cdclk_hooks(struct intel_display *display);
-- 
2.39.5

✗ CI.checkpatch: warning for drm/i915/display: make all global state opaque

[Patchwork]

== Series Details ==

Series: drm/i915/display: make all global state opaque
URL   : https://patchwork.freedesktop.org/series/150157/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
202708c00696422fd217223bb679a353a5936e23
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 0ec5aba21280d173fd611f1f3571b832ca82097e
Author: Jani Nikula <jani.nikula@intel.com>
Date:   Thu Jun 12 15:12:11 2025 +0300

    drm/i915/cdclk: make struct intel_cdclk_state opaque
    
    With all the code touching struct intel_cdclk_state moved inside
    intel_cdclk.c, we move the struct definition there too, and make the
    type opaque. This nicely reduces includes from intel_cdclk.h.
    
    Signed-off-by: Jani Nikula <jani.nikula@intel.com>
+ /mt/dim checkpatch a338c75e43f1604b70e9b2f8d287bb1b5d7ca934 drm-intel
ec9ddf123579 drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()
-:63: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#63: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:44:
+#define intel_atomic_get_old_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:64: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#64: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:45:
+	to_intel_dbuf_state(intel_atomic_get_old_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:65: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'state' - possible side-effects?
#65: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:46:
+#define intel_atomic_get_new_dbuf_state(state) \
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

-:66: WARNING:LONG_LINE: line length of 109 exceeds 100 columns
#66: FILE: drivers/gpu/drm/i915/display/skl_watermark.c:47:
+	to_intel_dbuf_state(intel_atomic_get_new_global_obj_state(state, &to_intel_display(state)->dbuf.obj))

total: 0 errors, 2 warnings, 2 checks, 94 lines checked
d01566e344e3 drm/i915/wm: add more accessors to dbuf state
-:28: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#28: FILE: drivers/gpu/drm/i915/display/intel_pmdemand.c:366:
+			min_t(u8, intel_dbuf_num_active_pipes(new_dbuf_state), INTEL_NUM_PIPES(display));

total: 0 errors, 1 warnings, 0 checks, 40 lines checked
5b546b7ddd65 drm/i915/wm: make struct intel_dbuf_state opaque type
b66ac648b412 drm/i915/bw: abstract intel_bw_pmdemand_needs_update()
e11f9bc27b3f drm/i915/bw: relocate intel_can_enable_sagv() and rename to intel_bw_can_enable_sagv()
ed40e4caf95a drm/i915: move icl_sagv_{pre, post}_plane_update() to intel_bw.c
382c385cb881 drm/i915/bw: abstract intel_bw_qgv_point_peakbw()
a2a197842c96 drm/i915/bw: make struct intel_bw_state opaque
70affc178a2b drm/i915/cdclk: abstract intel_cdclk_logical()
4bc78f94980f drm/i915/cdclk: abstract intel_cdclk_min_cdclk()
8625ae8ad0e2 drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()
066010611645 drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()
5f179f789c38 drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()
13206b7101de drm/i915/cdclk: abstract intel_cdclk_read_hw()
21688a79b280 drm/i915/cdclk: abstract intel_cdclk_actual() and intel_cdclk_actual_voltage_level()
0ec5aba21280 drm/i915/cdclk: make struct intel_cdclk_state opaque

✓ CI.KUnit: success for drm/i915/display: make all global state opaque

[Patchwork]

== Series Details ==

Series: drm/i915/display: make all global state opaque
URL   : https://patchwork.freedesktop.org/series/150157/
State : success

== Summary ==

+ trap cleanup EXIT
+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig
[13:14:17] Configuring KUnit Kernel ...
Generating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:14:21] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:14:48] Starting KUnit Kernel (1/1)...
[13:14:48] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:14:48] ================== guc_buf (11 subtests) ===================
[13:14:48] [PASSED] test_smallest
[13:14:48] [PASSED] test_largest
[13:14:48] [PASSED] test_granular
[13:14:48] [PASSED] test_unique
[13:14:48] [PASSED] test_overlap
[13:14:48] [PASSED] test_reusable
[13:14:48] [PASSED] test_too_big
[13:14:48] [PASSED] test_flush
[13:14:48] [PASSED] test_lookup
[13:14:48] [PASSED] test_data
[13:14:48] [PASSED] test_class
[13:14:48] ===================== [PASSED] guc_buf =====================
[13:14:48] =================== guc_dbm (7 subtests) ===================
[13:14:48] [PASSED] test_empty
[13:14:48] [PASSED] test_default
[13:14:48] ======================== test_size  ========================
[13:14:48] [PASSED] 4
[13:14:48] [PASSED] 8
[13:14:48] [PASSED] 32
[13:14:48] [PASSED] 256
[13:14:48] ==================== [PASSED] test_size ====================
[13:14:48] ======================= test_reuse  ========================
[13:14:48] [PASSED] 4
[13:14:48] [PASSED] 8
[13:14:48] [PASSED] 32
[13:14:48] [PASSED] 256
[13:14:48] =================== [PASSED] test_reuse ====================
[13:14:48] =================== test_range_overlap  ====================
[13:14:48] [PASSED] 4
[13:14:48] [PASSED] 8
[13:14:48] [PASSED] 32
[13:14:48] [PASSED] 256
[13:14:48] =============== [PASSED] test_range_overlap ================
[13:14:48] =================== test_range_compact  ====================
[13:14:48] [PASSED] 4
[13:14:48] [PASSED] 8
[13:14:48] [PASSED] 32
[13:14:48] [PASSED] 256
[13:14:48] =============== [PASSED] test_range_compact ================
[13:14:48] ==================== test_range_spare  =====================
[13:14:48] [PASSED] 4
[13:14:48] [PASSED] 8
[13:14:48] [PASSED] 32
[13:14:48] [PASSED] 256
[13:14:48] ================ [PASSED] test_range_spare =================
[13:14:48] ===================== [PASSED] guc_dbm =====================
[13:14:48] =================== guc_idm (6 subtests) ===================
[13:14:48] [PASSED] bad_init
[13:14:48] [PASSED] no_init
[13:14:48] [PASSED] init_fini
[13:14:48] [PASSED] check_used
[13:14:48] [PASSED] check_quota
[13:14:48] [PASSED] check_all
[13:14:48] ===================== [PASSED] guc_idm =====================
[13:14:48] ================== no_relay (3 subtests) ===================
[13:14:48] [PASSED] xe_drops_guc2pf_if_not_ready
[13:14:48] [PASSED] xe_drops_guc2vf_if_not_ready
[13:14:48] [PASSED] xe_rejects_send_if_not_ready
[13:14:48] ==================== [PASSED] no_relay =====================
[13:14:48] ================== pf_relay (14 subtests) ==================
[13:14:48] [PASSED] pf_rejects_guc2pf_too_short
[13:14:48] [PASSED] pf_rejects_guc2pf_too_long
[13:14:48] [PASSED] pf_rejects_guc2pf_no_payload
[13:14:48] [PASSED] pf_fails_no_payload
[13:14:48] [PASSED] pf_fails_bad_origin
[13:14:48] [PASSED] pf_fails_bad_type
[13:14:48] [PASSED] pf_txn_reports_error
[13:14:48] [PASSED] pf_txn_sends_pf2guc
[13:14:48] [PASSED] pf_sends_pf2guc
[13:14:48] [SKIPPED] pf_loopback_nop
[13:14:48] [SKIPPED] pf_loopback_echo
[13:14:48] [SKIPPED] pf_loopback_fail
[13:14:48] [SKIPPED] pf_loopback_busy
[13:14:48] [SKIPPED] pf_loopback_retry
[13:14:48] ==================== [PASSED] pf_relay =====================
[13:14:48] ================== vf_relay (3 subtests) ===================
[13:14:48] [PASSED] vf_rejects_guc2vf_too_short
[13:14:48] [PASSED] vf_rejects_guc2vf_too_long
[13:14:48] [PASSED] vf_rejects_guc2vf_no_payload
[13:14:48] ==================== [PASSED] vf_relay =====================
[13:14:48] ================= pf_service (11 subtests) =================
[13:14:48] [PASSED] pf_negotiate_any
[13:14:48] [PASSED] pf_negotiate_base_match
[13:14:48] [PASSED] pf_negotiate_base_newer
[13:14:48] [PASSED] pf_negotiate_base_next
[13:14:48] [SKIPPED] pf_negotiate_base_older
[13:14:48] [PASSED] pf_negotiate_base_prev
[13:14:48] [PASSED] pf_negotiate_latest_match
[13:14:48] [PASSED] pf_negotiate_latest_newer
[13:14:48] [PASSED] pf_negotiate_latest_next
[13:14:48] [SKIPPED] pf_negotiate_latest_older
[13:14:48] [SKIPPED] pf_negotiate_latest_prev
[13:14:48] =================== [PASSED] pf_service ====================
[13:14:48] ===================== lmtt (1 subtest) =====================
[13:14:48] ======================== test_ops  =========================
[13:14:48] [PASSED] 2-level
[13:14:48] [PASSED] multi-level
[13:14:48] ==================== [PASSED] test_ops =====================
[13:14:48] ====================== [PASSED] lmtt =======================
[13:14:48] =================== xe_mocs (2 subtests) ===================
[13:14:48] ================ xe_live_mocs_kernel_kunit  ================
[13:14:48] =========== [SKIPPED] xe_live_mocs_kernel_kunit ============
[13:14:48] ================ xe_live_mocs_reset_kunit  =================
[13:14:48] ============ [SKIPPED] xe_live_mocs_reset_kunit ============
[13:14:48] ==================== [SKIPPED] xe_mocs =====================
[13:14:48] ================= xe_migrate (2 subtests) ==================
[13:14:48] ================= xe_migrate_sanity_kunit  =================
[13:14:48] ============ [SKIPPED] xe_migrate_sanity_kunit =============
[13:14:48] ================== xe_validate_ccs_kunit  ==================
[13:14:48] ============= [SKIPPED] xe_validate_ccs_kunit ==============
[13:14:48] =================== [SKIPPED] xe_migrate ===================
[13:14:48] ================== xe_dma_buf (1 subtest) ==================
[13:14:48] ==================== xe_dma_buf_kunit  =====================
[13:14:48] ================ [SKIPPED] xe_dma_buf_kunit ================
[13:14:48] =================== [SKIPPED] xe_dma_buf ===================
[13:14:48] ================= xe_bo_shrink (1 subtest) =================
[13:14:48] =================== xe_bo_shrink_kunit  ====================
[13:14:48] =============== [SKIPPED] xe_bo_shrink_kunit ===============
[13:14:48] ================== [SKIPPED] xe_bo_shrink ==================
[13:14:48] ==================== xe_bo (2 subtests) ====================
[13:14:48] ================== xe_ccs_migrate_kunit  ===================
[13:14:48] ============== [SKIPPED] xe_ccs_migrate_kunit ==============
[13:14:48] ==================== xe_bo_evict_kunit  ====================
[13:14:48] =============== [SKIPPED] xe_bo_evict_kunit ================
[13:14:48] ===================== [SKIPPED] xe_bo ======================
[13:14:48] ==================== args (11 subtests) ====================
[13:14:48] [PASSED] count_args_test
[13:14:48] [PASSED] call_args_example
[13:14:48] [PASSED] call_args_test
[13:14:48] [PASSED] drop_first_arg_example
[13:14:48] [PASSED] drop_first_arg_test
[13:14:48] [PASSED] first_arg_example
[13:14:48] [PASSED] first_arg_test
[13:14:48] [PASSED] last_arg_example
[13:14:48] [PASSED] last_arg_test
[13:14:48] [PASSED] pick_arg_example
[13:14:48] [PASSED] sep_comma_example
[13:14:48] ====================== [PASSED] args =======================
[13:14:48] =================== xe_pci (2 subtests) ====================
[13:14:48] [PASSED] xe_gmdid_graphics_ip
[13:14:48] [PASSED] xe_gmdid_media_ip
[13:14:48] ===================== [PASSED] xe_pci ======================
[13:14:48] =================== xe_rtp (2 subtests) ====================
[13:14:48] =============== xe_rtp_process_to_sr_tests  ================
[13:14:48] [PASSED] coalesce-same-reg
[13:14:48] [PASSED] no-match-no-add
[13:14:48] [PASSED] match-or
[13:14:48] [PASSED] match-or-xfail
[13:14:48] [PASSED] no-match-no-add-multiple-rules
[13:14:48] [PASSED] two-regs-two-entries
[13:14:48] [PASSED] clr-one-set-other
[13:14:48] [PASSED] set-field
[13:14:48] [PASSED] conflict-duplicate
[13:14:48] [PASSED] conflict-not-disjoint
stty: 'standard input': Inappropriate ioctl for device
[13:14:48] [PASSED] conflict-reg-type
[13:14:48] =========== [PASSED] xe_rtp_process_to_sr_tests ============
[13:14:48] ================== xe_rtp_process_tests  ===================
[13:14:48] [PASSED] active1
[13:14:48] [PASSED] active2
[13:14:48] [PASSED] active-inactive
[13:14:48] [PASSED] inactive-active
[13:14:48] [PASSED] inactive-1st_or_active-inactive
[13:14:48] [PASSED] inactive-2nd_or_active-inactive
[13:14:48] [PASSED] inactive-last_or_active-inactive
[13:14:48] [PASSED] inactive-no_or_active-inactive
[13:14:48] ============== [PASSED] xe_rtp_process_tests ===============
[13:14:48] ===================== [PASSED] xe_rtp ======================
[13:14:48] ==================== xe_wa (1 subtest) =====================
[13:14:48] ======================== xe_wa_gt  =========================
[13:14:48] [PASSED] TIGERLAKE (B0)
[13:14:48] [PASSED] DG1 (A0)
[13:14:48] [PASSED] DG1 (B0)
[13:14:48] [PASSED] ALDERLAKE_S (A0)
[13:14:48] [PASSED] ALDERLAKE_S (B0)
[13:14:48] [PASSED] ALDERLAKE_S (C0)
[13:14:48] [PASSED] ALDERLAKE_S (D0)
[13:14:48] [PASSED] ALDERLAKE_P (A0)
[13:14:48] [PASSED] ALDERLAKE_P (B0)
[13:14:48] [PASSED] ALDERLAKE_P (C0)
[13:14:48] [PASSED] ALDERLAKE_S_RPLS (D0)
[13:14:48] [PASSED] ALDERLAKE_P_RPLU (E0)
[13:14:48] [PASSED] DG2_G10 (C0)
[13:14:48] [PASSED] DG2_G11 (B1)
[13:14:48] [PASSED] DG2_G12 (A1)
[13:14:48] [PASSED] METEORLAKE (g:A0, m:A0)
[13:14:48] [PASSED] METEORLAKE (g:A0, m:A0)
[13:14:48] [PASSED] METEORLAKE (g:A0, m:A0)
[13:14:48] [PASSED] LUNARLAKE (g:A0, m:A0)
[13:14:48] [PASSED] LUNARLAKE (g:B0, m:A0)
[13:14:48] [PASSED] BATTLEMAGE (g:A0, m:A1)
[13:14:48] ==================== [PASSED] xe_wa_gt =====================
[13:14:48] ====================== [PASSED] xe_wa ======================
[13:14:48] ============================================================
[13:14:48] Testing complete. Ran 133 tests: passed: 117, skipped: 16
[13:14:48] Elapsed time: 31.523s total, 4.218s configuring, 26.988s building, 0.301s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig
[13:14:48] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:14:50] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:15:12] Starting KUnit Kernel (1/1)...
[13:15:12] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:15:12] == drm_test_atomic_get_connector_for_encoder (1 subtest) ===
[13:15:12] [PASSED] drm_test_drm_atomic_get_connector_for_encoder
[13:15:12] ==== [PASSED] drm_test_atomic_get_connector_for_encoder ====
[13:15:12] =========== drm_validate_clone_mode (2 subtests) ===========
[13:15:12] ============== drm_test_check_in_clone_mode  ===============
[13:15:12] [PASSED] in_clone_mode
[13:15:12] [PASSED] not_in_clone_mode
[13:15:12] ========== [PASSED] drm_test_check_in_clone_mode ===========
[13:15:12] =============== drm_test_check_valid_clones  ===============
[13:15:12] [PASSED] not_in_clone_mode
[13:15:12] [PASSED] valid_clone
[13:15:12] [PASSED] invalid_clone
[13:15:12] =========== [PASSED] drm_test_check_valid_clones ===========
[13:15:12] ============= [PASSED] drm_validate_clone_mode =============
[13:15:12] ============= drm_validate_modeset (1 subtest) =============
[13:15:12] [PASSED] drm_test_check_connector_changed_modeset
[13:15:12] ============== [PASSED] drm_validate_modeset ===============
[13:15:12] ====== drm_test_bridge_get_current_state (2 subtests) ======
[13:15:12] [PASSED] drm_test_drm_bridge_get_current_state_atomic
[13:15:12] [PASSED] drm_test_drm_bridge_get_current_state_legacy
[13:15:12] ======== [PASSED] drm_test_bridge_get_current_state ========
[13:15:12] ====== drm_test_bridge_helper_reset_crtc (3 subtests) ======
[13:15:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic
[13:15:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_atomic_disabled
[13:15:12] [PASSED] drm_test_drm_bridge_helper_reset_crtc_legacy
[13:15:12] ======== [PASSED] drm_test_bridge_helper_reset_crtc ========
[13:15:12] ============== drm_bridge_alloc (2 subtests) ===============
[13:15:12] [PASSED] drm_test_drm_bridge_alloc_basic
[13:15:12] [PASSED] drm_test_drm_bridge_alloc_get_put
[13:15:12] ================ [PASSED] drm_bridge_alloc =================
[13:15:12] ================== drm_buddy (7 subtests) ==================
[13:15:12] [PASSED] drm_test_buddy_alloc_limit
[13:15:12] [PASSED] drm_test_buddy_alloc_optimistic
[13:15:12] [PASSED] drm_test_buddy_alloc_pessimistic
[13:15:12] [PASSED] drm_test_buddy_alloc_pathological
[13:15:12] [PASSED] drm_test_buddy_alloc_contiguous
[13:15:12] [PASSED] drm_test_buddy_alloc_clear
[13:15:12] [PASSED] drm_test_buddy_alloc_range_bias
[13:15:12] ==================== [PASSED] drm_buddy ====================
[13:15:12] ============= drm_cmdline_parser (40 subtests) =============
[13:15:12] [PASSED] drm_test_cmdline_force_d_only
[13:15:12] [PASSED] drm_test_cmdline_force_D_only_dvi
[13:15:12] [PASSED] drm_test_cmdline_force_D_only_hdmi
[13:15:12] [PASSED] drm_test_cmdline_force_D_only_not_digital
[13:15:12] [PASSED] drm_test_cmdline_force_e_only
[13:15:12] [PASSED] drm_test_cmdline_res
[13:15:12] [PASSED] drm_test_cmdline_res_vesa
[13:15:12] [PASSED] drm_test_cmdline_res_vesa_rblank
[13:15:12] [PASSED] drm_test_cmdline_res_rblank
[13:15:12] [PASSED] drm_test_cmdline_res_bpp
[13:15:12] [PASSED] drm_test_cmdline_res_refresh
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_margins
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital
[13:15:12] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on
[13:15:12] [PASSED] drm_test_cmdline_res_margins_force_on
[13:15:12] [PASSED] drm_test_cmdline_res_vesa_margins
[13:15:12] [PASSED] drm_test_cmdline_name
[13:15:12] [PASSED] drm_test_cmdline_name_bpp
[13:15:12] [PASSED] drm_test_cmdline_name_option
[13:15:12] [PASSED] drm_test_cmdline_name_bpp_option
[13:15:12] [PASSED] drm_test_cmdline_rotate_0
[13:15:12] [PASSED] drm_test_cmdline_rotate_90
[13:15:12] [PASSED] drm_test_cmdline_rotate_180
[13:15:12] [PASSED] drm_test_cmdline_rotate_270
[13:15:12] [PASSED] drm_test_cmdline_hmirror
[13:15:12] [PASSED] drm_test_cmdline_vmirror
[13:15:12] [PASSED] drm_test_cmdline_margin_options
[13:15:12] [PASSED] drm_test_cmdline_multiple_options
[13:15:12] [PASSED] drm_test_cmdline_bpp_extra_and_option
[13:15:12] [PASSED] drm_test_cmdline_extra_and_option
[13:15:12] [PASSED] drm_test_cmdline_freestanding_options
[13:15:12] [PASSED] drm_test_cmdline_freestanding_force_e_and_options
[13:15:12] [PASSED] drm_test_cmdline_panel_orientation
[13:15:12] ================ drm_test_cmdline_invalid  =================
[13:15:12] [PASSED] margin_only
[13:15:12] [PASSED] interlace_only
[13:15:12] [PASSED] res_missing_x
[13:15:12] [PASSED] res_missing_y
[13:15:12] [PASSED] res_bad_y
[13:15:12] [PASSED] res_missing_y_bpp
[13:15:12] [PASSED] res_bad_bpp
[13:15:12] [PASSED] res_bad_refresh
[13:15:12] [PASSED] res_bpp_refresh_force_on_off
[13:15:12] [PASSED] res_invalid_mode
[13:15:12] [PASSED] res_bpp_wrong_place_mode
[13:15:12] [PASSED] name_bpp_refresh
[13:15:12] [PASSED] name_refresh
[13:15:12] [PASSED] name_refresh_wrong_mode
[13:15:12] [PASSED] name_refresh_invalid_mode
[13:15:12] [PASSED] rotate_multiple
[13:15:12] [PASSED] rotate_invalid_val
[13:15:12] [PASSED] rotate_truncated
[13:15:12] [PASSED] invalid_option
[13:15:12] [PASSED] invalid_tv_option
[13:15:12] [PASSED] truncated_tv_option
[13:15:12] ============ [PASSED] drm_test_cmdline_invalid =============
[13:15:12] =============== drm_test_cmdline_tv_options  ===============
[13:15:12] [PASSED] NTSC
[13:15:12] [PASSED] NTSC_443
[13:15:12] [PASSED] NTSC_J
[13:15:12] [PASSED] PAL
[13:15:12] [PASSED] PAL_M
[13:15:12] [PASSED] PAL_N
[13:15:12] [PASSED] SECAM
[13:15:12] [PASSED] MONO_525
[13:15:12] [PASSED] MONO_625
[13:15:12] =========== [PASSED] drm_test_cmdline_tv_options ===========
[13:15:12] =============== [PASSED] drm_cmdline_parser ================
[13:15:12] ========== drmm_connector_hdmi_init (20 subtests) ==========
[13:15:12] [PASSED] drm_test_connector_hdmi_init_valid
[13:15:12] [PASSED] drm_test_connector_hdmi_init_bpc_8
[13:15:12] [PASSED] drm_test_connector_hdmi_init_bpc_10
[13:15:12] [PASSED] drm_test_connector_hdmi_init_bpc_12
[13:15:12] [PASSED] drm_test_connector_hdmi_init_bpc_invalid
[13:15:12] [PASSED] drm_test_connector_hdmi_init_bpc_null
[13:15:12] [PASSED] drm_test_connector_hdmi_init_formats_empty
[13:15:12] [PASSED] drm_test_connector_hdmi_init_formats_no_rgb
[13:15:12] === drm_test_connector_hdmi_init_formats_yuv420_allowed  ===
[13:15:12] [PASSED] supported_formats=0x9 yuv420_allowed=1
[13:15:12] [PASSED] supported_formats=0x9 yuv420_allowed=0
[13:15:12] [PASSED] supported_formats=0x3 yuv420_allowed=1
[13:15:12] [PASSED] supported_formats=0x3 yuv420_allowed=0
[13:15:12] === [PASSED] drm_test_connector_hdmi_init_formats_yuv420_allowed ===
[13:15:12] [PASSED] drm_test_connector_hdmi_init_null_ddc
[13:15:12] [PASSED] drm_test_connector_hdmi_init_null_product
[13:15:12] [PASSED] drm_test_connector_hdmi_init_null_vendor
[13:15:12] [PASSED] drm_test_connector_hdmi_init_product_length_exact
[13:15:12] [PASSED] drm_test_connector_hdmi_init_product_length_too_long
[13:15:12] [PASSED] drm_test_connector_hdmi_init_product_valid
[13:15:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_exact
[13:15:12] [PASSED] drm_test_connector_hdmi_init_vendor_length_too_long
[13:15:12] [PASSED] drm_test_connector_hdmi_init_vendor_valid
[13:15:12] ========= drm_test_connector_hdmi_init_type_valid  =========
[13:15:12] [PASSED] HDMI-A
[13:15:12] [PASSED] HDMI-B
[13:15:12] ===== [PASSED] drm_test_connector_hdmi_init_type_valid =====
[13:15:12] ======== drm_test_connector_hdmi_init_type_invalid  ========
[13:15:12] [PASSED] Unknown
[13:15:12] [PASSED] VGA
[13:15:12] [PASSED] DVI-I
[13:15:12] [PASSED] DVI-D
[13:15:12] [PASSED] DVI-A
[13:15:12] [PASSED] Composite
[13:15:12] [PASSED] SVIDEO
[13:15:12] [PASSED] LVDS
[13:15:12] [PASSED] Component
[13:15:12] [PASSED] DIN
[13:15:12] [PASSED] DP
[13:15:12] [PASSED] TV
[13:15:12] [PASSED] eDP
[13:15:12] [PASSED] Virtual
[13:15:12] [PASSED] DSI
[13:15:12] [PASSED] DPI
[13:15:12] [PASSED] Writeback
[13:15:12] [PASSED] SPI
[13:15:12] [PASSED] USB
[13:15:12] ==== [PASSED] drm_test_connector_hdmi_init_type_invalid ====
[13:15:12] ============ [PASSED] drmm_connector_hdmi_init =============
[13:15:12] ============= drmm_connector_init (3 subtests) =============
[13:15:12] [PASSED] drm_test_drmm_connector_init
[13:15:12] [PASSED] drm_test_drmm_connector_init_null_ddc
[13:15:12] ========= drm_test_drmm_connector_init_type_valid  =========
[13:15:12] [PASSED] Unknown
[13:15:12] [PASSED] VGA
[13:15:12] [PASSED] DVI-I
[13:15:12] [PASSED] DVI-D
[13:15:12] [PASSED] DVI-A
[13:15:12] [PASSED] Composite
[13:15:12] [PASSED] SVIDEO
[13:15:12] [PASSED] LVDS
[13:15:12] [PASSED] Component
[13:15:12] [PASSED] DIN
[13:15:12] [PASSED] DP
[13:15:12] [PASSED] HDMI-A
[13:15:12] [PASSED] HDMI-B
[13:15:12] [PASSED] TV
[13:15:12] [PASSED] eDP
[13:15:12] [PASSED] Virtual
[13:15:12] [PASSED] DSI
[13:15:12] [PASSED] DPI
[13:15:12] [PASSED] Writeback
[13:15:12] [PASSED] SPI
[13:15:12] [PASSED] USB
[13:15:12] ===== [PASSED] drm_test_drmm_connector_init_type_valid =====
[13:15:12] =============== [PASSED] drmm_connector_init ===============
[13:15:12] ========= drm_connector_dynamic_init (6 subtests) ==========
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_init
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_init_null_ddc
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_init_not_added
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_init_properties
[13:15:12] ===== drm_test_drm_connector_dynamic_init_type_valid  ======
[13:15:12] [PASSED] Unknown
[13:15:12] [PASSED] VGA
[13:15:12] [PASSED] DVI-I
[13:15:12] [PASSED] DVI-D
[13:15:12] [PASSED] DVI-A
[13:15:12] [PASSED] Composite
[13:15:12] [PASSED] SVIDEO
[13:15:12] [PASSED] LVDS
[13:15:12] [PASSED] Component
[13:15:12] [PASSED] DIN
[13:15:12] [PASSED] DP
[13:15:12] [PASSED] HDMI-A
[13:15:12] [PASSED] HDMI-B
[13:15:12] [PASSED] TV
[13:15:12] [PASSED] eDP
[13:15:12] [PASSED] Virtual
[13:15:12] [PASSED] DSI
[13:15:12] [PASSED] DPI
[13:15:12] [PASSED] Writeback
[13:15:12] [PASSED] SPI
[13:15:12] [PASSED] USB
[13:15:12] = [PASSED] drm_test_drm_connector_dynamic_init_type_valid ==
[13:15:12] ======== drm_test_drm_connector_dynamic_init_name  =========
[13:15:12] [PASSED] Unknown
[13:15:12] [PASSED] VGA
[13:15:12] [PASSED] DVI-I
[13:15:12] [PASSED] DVI-D
[13:15:12] [PASSED] DVI-A
[13:15:12] [PASSED] Composite
[13:15:12] [PASSED] SVIDEO
[13:15:12] [PASSED] LVDS
[13:15:12] [PASSED] Component
[13:15:12] [PASSED] DIN
[13:15:12] [PASSED] DP
[13:15:12] [PASSED] HDMI-A
[13:15:12] [PASSED] HDMI-B
[13:15:12] [PASSED] TV
[13:15:12] [PASSED] eDP
[13:15:12] [PASSED] Virtual
[13:15:12] [PASSED] DSI
[13:15:12] [PASSED] DPI
[13:15:12] [PASSED] Writeback
[13:15:12] [PASSED] SPI
[13:15:12] [PASSED] USB
[13:15:12] ==== [PASSED] drm_test_drm_connector_dynamic_init_name =====
[13:15:12] =========== [PASSED] drm_connector_dynamic_init ============
[13:15:12] ==== drm_connector_dynamic_register_early (4 subtests) =====
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_early_on_list
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_early_defer
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_init
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_early_no_mode_object
[13:15:12] ====== [PASSED] drm_connector_dynamic_register_early =======
[13:15:12] ======= drm_connector_dynamic_register (7 subtests) ========
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_on_list
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_no_defer
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_no_init
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_mode_object
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_sysfs_name
[13:15:12] [PASSED] drm_test_drm_connector_dynamic_register_debugfs
[13:15:12] ========= [PASSED] drm_connector_dynamic_register ==========
[13:15:12] = drm_connector_attach_broadcast_rgb_property (2 subtests) =
[13:15:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property
[13:15:12] [PASSED] drm_test_drm_connector_attach_broadcast_rgb_property_hdmi_connector
[13:15:12] === [PASSED] drm_connector_attach_broadcast_rgb_property ===
[13:15:12] ========== drm_get_tv_mode_from_name (2 subtests) ==========
[13:15:12] ========== drm_test_get_tv_mode_from_name_valid  ===========
[13:15:12] [PASSED] NTSC
[13:15:12] [PASSED] NTSC-443
[13:15:12] [PASSED] NTSC-J
[13:15:12] [PASSED] PAL
[13:15:12] [PASSED] PAL-M
[13:15:12] [PASSED] PAL-N
[13:15:12] [PASSED] SECAM
[13:15:12] [PASSED] Mono
[13:15:12] ====== [PASSED] drm_test_get_tv_mode_from_name_valid =======
[13:15:12] [PASSED] drm_test_get_tv_mode_from_name_truncated
[13:15:12] ============ [PASSED] drm_get_tv_mode_from_name ============
[13:15:12] = drm_test_connector_hdmi_compute_mode_clock (12 subtests) =
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_10bpc_vic_1
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_12bpc_vic_1
[13:15:12] [PASSED] drm_test_drm_hdmi_compute_mode_clock_rgb_double
[13:15:12] = drm_test_connector_hdmi_compute_mode_clock_yuv420_valid  =
[13:15:12] [PASSED] VIC 96
[13:15:12] [PASSED] VIC 97
[13:15:12] [PASSED] VIC 101
[13:15:12] [PASSED] VIC 102
[13:15:12] [PASSED] VIC 106
[13:15:12] [PASSED] VIC 107
[13:15:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_valid ===
[13:15:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_10_bpc
[13:15:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv420_12_bpc
[13:15:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_8_bpc
[13:15:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_10_bpc
[13:15:12] [PASSED] drm_test_connector_hdmi_compute_mode_clock_yuv422_12_bpc
[13:15:12] === [PASSED] drm_test_connector_hdmi_compute_mode_clock ====
[13:15:12] == drm_hdmi_connector_get_broadcast_rgb_name (2 subtests) ==
[13:15:12] === drm_test_drm_hdmi_connector_get_broadcast_rgb_name  ====
[13:15:12] [PASSED] Automatic
[13:15:12] [PASSED] Full
[13:15:12] [PASSED] Limited 16:235
[13:15:12] === [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name ===
[13:15:12] [PASSED] drm_test_drm_hdmi_connector_get_broadcast_rgb_name_invalid
[13:15:12] ==== [PASSED] drm_hdmi_connector_get_broadcast_rgb_name ====
[13:15:12] == drm_hdmi_connector_get_output_format_name (2 subtests) ==
[13:15:12] === drm_test_drm_hdmi_connector_get_output_format_name  ====
[13:15:12] [PASSED] RGB
[13:15:12] [PASSED] YUV 4:2:0
[13:15:12] [PASSED] YUV 4:2:2
[13:15:12] [PASSED] YUV 4:4:4
[13:15:12] === [PASSED] drm_test_drm_hdmi_connector_get_output_format_name ===
[13:15:12] [PASSED] drm_test_drm_hdmi_connector_get_output_format_name_invalid
[13:15:12] ==== [PASSED] drm_hdmi_connector_get_output_format_name ====
[13:15:12] ============= drm_damage_helper (21 subtests) ==============
[13:15:12] [PASSED] drm_test_damage_iter_no_damage
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_src_moved
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_not_visible
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_no_crtc
[13:15:12] [PASSED] drm_test_damage_iter_no_damage_no_fb
[13:15:12] [PASSED] drm_test_damage_iter_simple_damage
[13:15:12] [PASSED] drm_test_damage_iter_single_damage
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_intersect_src
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_outside_src
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_src_moved
[13:15:12] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved
[13:15:12] [PASSED] drm_test_damage_iter_damage
[13:15:12] [PASSED] drm_test_damage_iter_damage_one_intersect
[13:15:12] [PASSED] drm_test_damage_iter_damage_one_outside
[13:15:12] [PASSED] drm_test_damage_iter_damage_src_moved
[13:15:12] [PASSED] drm_test_damage_iter_damage_not_visible
[13:15:12] ================ [PASSED] drm_damage_helper ================
[13:15:12] ============== drm_dp_mst_helper (3 subtests) ==============
[13:15:12] ============== drm_test_dp_mst_calc_pbn_mode  ==============
[13:15:12] [PASSED] Clock 154000 BPP 30 DSC disabled
[13:15:12] [PASSED] Clock 234000 BPP 30 DSC disabled
[13:15:12] [PASSED] Clock 297000 BPP 24 DSC disabled
[13:15:12] [PASSED] Clock 332880 BPP 24 DSC enabled
[13:15:12] [PASSED] Clock 324540 BPP 24 DSC enabled
[13:15:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ==========
[13:15:12] ============== drm_test_dp_mst_calc_pbn_div  ===============
[13:15:12] [PASSED] Link rate 2000000 lane count 4
[13:15:12] [PASSED] Link rate 2000000 lane count 2
[13:15:12] [PASSED] Link rate 2000000 lane count 1
[13:15:12] [PASSED] Link rate 1350000 lane count 4
[13:15:12] [PASSED] Link rate 1350000 lane count 2
[13:15:12] [PASSED] Link rate 1350000 lane count 1
[13:15:12] [PASSED] Link rate 1000000 lane count 4
[13:15:12] [PASSED] Link rate 1000000 lane count 2
[13:15:12] [PASSED] Link rate 1000000 lane count 1
[13:15:12] [PASSED] Link rate 810000 lane count 4
[13:15:12] [PASSED] Link rate 810000 lane count 2
[13:15:12] [PASSED] Link rate 810000 lane count 1
[13:15:12] [PASSED] Link rate 540000 lane count 4
[13:15:12] [PASSED] Link rate 540000 lane count 2
[13:15:12] [PASSED] Link rate 540000 lane count 1
[13:15:12] [PASSED] Link rate 270000 lane count 4
[13:15:12] [PASSED] Link rate 270000 lane count 2
[13:15:12] [PASSED] Link rate 270000 lane count 1
[13:15:12] [PASSED] Link rate 162000 lane count 4
[13:15:12] [PASSED] Link rate 162000 lane count 2
[13:15:12] [PASSED] Link rate 162000 lane count 1
[13:15:12] ========== [PASSED] drm_test_dp_mst_calc_pbn_div ===========
[13:15:12] ========= drm_test_dp_mst_sideband_msg_req_decode  =========
[13:15:12] [PASSED] DP_ENUM_PATH_RESOURCES with port number
[13:15:12] [PASSED] DP_POWER_UP_PHY with port number
[13:15:12] [PASSED] DP_POWER_DOWN_PHY with port number
[13:15:12] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks
[13:15:12] [PASSED] DP_ALLOCATE_PAYLOAD with port number
[13:15:12] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI
[13:15:12] [PASSED] DP_ALLOCATE_PAYLOAD with PBN
[13:15:12] [PASSED] DP_QUERY_PAYLOAD with port number
[13:15:12] [PASSED] DP_QUERY_PAYLOAD with VCPI
[13:15:12] [PASSED] DP_REMOTE_DPCD_READ with port number
[13:15:12] [PASSED] DP_REMOTE_DPCD_READ with DPCD address
[13:15:12] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes
[13:15:12] [PASSED] DP_REMOTE_DPCD_WRITE with port number
[13:15:12] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address
[13:15:12] [PASSED] DP_REMOTE_DPCD_WRITE with data array
[13:15:12] [PASSED] DP_REMOTE_I2C_READ with port number
[13:15:12] [PASSED] DP_REMOTE_I2C_READ with I2C device ID
[13:15:12] [PASSED] DP_REMOTE_I2C_READ with transactions array
[13:15:12] [PASSED] DP_REMOTE_I2C_WRITE with port number
[13:15:12] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID
[13:15:12] [PASSED] DP_REMOTE_I2C_WRITE with data array
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior
[13:15:12] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior
[13:15:12] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode =====
[13:15:12] ================ [PASSED] drm_dp_mst_helper ================
[13:15:12] ================== drm_exec (7 subtests) ===================
[13:15:12] [PASSED] sanitycheck
[13:15:12] [PASSED] test_lock
[13:15:12] [PASSED] test_lock_unlock
[13:15:12] [PASSED] test_duplicates
[13:15:12] [PASSED] test_prepare
[13:15:12] [PASSED] test_prepare_array
[13:15:12] [PASSED] test_multiple_loops
[13:15:12] ==================== [PASSED] drm_exec =====================
[13:15:12] =========== drm_format_helper_test (18 subtests) ===========
[13:15:12] ============== drm_test_fb_xrgb8888_to_gray8  ==============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ==========
[13:15:12] ============= drm_test_fb_xrgb8888_to_rgb332  ==============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ==========
[13:15:12] ============= drm_test_fb_xrgb8888_to_rgb565  ==============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ==========
[13:15:12] ============ drm_test_fb_xrgb8888_to_xrgb1555  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 =========
[13:15:12] ============ drm_test_fb_xrgb8888_to_argb1555  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 =========
[13:15:12] ============ drm_test_fb_xrgb8888_to_rgba5551  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 =========
[13:15:12] ============= drm_test_fb_xrgb8888_to_rgb888  ==============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ==========
[13:15:12] ============= drm_test_fb_xrgb8888_to_bgr888  ==============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========= [PASSED] drm_test_fb_xrgb8888_to_bgr888 ==========
[13:15:12] ============ drm_test_fb_xrgb8888_to_argb8888  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 =========
[13:15:12] =========== drm_test_fb_xrgb8888_to_xrgb2101010  ===========
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 =======
[13:15:12] =========== drm_test_fb_xrgb8888_to_argb2101010  ===========
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 =======
[13:15:12] ============== drm_test_fb_xrgb8888_to_mono  ===============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ========== [PASSED] drm_test_fb_xrgb8888_to_mono ===========
[13:15:12] ==================== drm_test_fb_swab  =====================
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ================ [PASSED] drm_test_fb_swab =================
[13:15:12] ============ drm_test_fb_xrgb8888_to_xbgr8888  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_xbgr8888 =========
[13:15:12] ============ drm_test_fb_xrgb8888_to_abgr8888  =============
[13:15:12] [PASSED] single_pixel_source_buffer
[13:15:12] [PASSED] single_pixel_clip_rectangle
[13:15:12] [PASSED] well_known_colors
[13:15:12] [PASSED] destination_pitch
[13:15:12] ======== [PASSED] drm_test_fb_xrgb8888_to_abgr8888 =========
[13:15:12] ================= drm_test_fb_clip_offset  =================
[13:15:12] [PASSED] pass through
[13:15:12] [PASSED] horizontal offset
[13:15:12] [PASSED] vertical offset
[13:15:12] [PASSED] horizontal and vertical offset
[13:15:12] [PASSED] horizontal offset (custom pitch)
[13:15:12] [PASSED] vertical offset (custom pitch)
[13:15:12] [PASSED] horizontal and vertical offset (custom pitch)
[13:15:12] ============= [PASSED] drm_test_fb_clip_offset =============
[13:15:12] ============== drm_test_fb_build_fourcc_list  ==============
[13:15:12] [PASSED] no native formats
[13:15:12] [PASSED] XRGB8888 as native format
[13:15:12] [PASSED] remove duplicates
[13:15:12] [PASSED] convert alpha formats
[13:15:12] [PASSED] random formats
[13:15:12] ========== [PASSED] drm_test_fb_build_fourcc_list ==========
[13:15:12] =================== drm_test_fb_memcpy  ====================
[13:15:12] [PASSED] single_pixel_source_buffer: XR24 little-endian (0x34325258)
[13:15:12] [PASSED] single_pixel_source_buffer: XRA8 little-endian (0x38415258)
[13:15:12] [PASSED] single_pixel_source_buffer: YU24 little-endian (0x34325559)
[13:15:12] [PASSED] single_pixel_clip_rectangle: XB24 little-endian (0x34324258)
[13:15:12] [PASSED] single_pixel_clip_rectangle: XRA8 little-endian (0x38415258)
[13:15:12] [PASSED] single_pixel_clip_rectangle: YU24 little-endian (0x34325559)
[13:15:12] [PASSED] well_known_colors: XB24 little-endian (0x34324258)
[13:15:12] [PASSED] well_known_colors: XRA8 little-endian (0x38415258)
[13:15:12] [PASSED] well_known_colors: YU24 little-endian (0x34325559)
[13:15:12] [PASSED] destination_pitch: XB24 little-endian (0x34324258)
[13:15:12] [PASSED] destination_pitch: XRA8 little-endian (0x38415258)
[13:15:12] [PASSED] destination_pitch: YU24 little-endian (0x34325559)
[13:15:12] =============== [PASSED] drm_test_fb_memcpy ================
[13:15:12] ============= [PASSED] drm_format_helper_test ==============
[13:15:12] ================= drm_format (18 subtests) =================
[13:15:12] [PASSED] drm_test_format_block_width_invalid
[13:15:12] [PASSED] drm_test_format_block_width_one_plane
[13:15:12] [PASSED] drm_test_format_block_width_two_plane
[13:15:12] [PASSED] drm_test_format_block_width_three_plane
[13:15:12] [PASSED] drm_test_format_block_width_tiled
[13:15:12] [PASSED] drm_test_format_block_height_invalid
[13:15:12] [PASSED] drm_test_format_block_height_one_plane
[13:15:12] [PASSED] drm_test_format_block_height_two_plane
[13:15:12] [PASSED] drm_test_format_block_height_three_plane
[13:15:12] [PASSED] drm_test_format_block_height_tiled
[13:15:12] [PASSED] drm_test_format_min_pitch_invalid
[13:15:12] [PASSED] drm_test_format_min_pitch_one_plane_8bpp
[13:15:12] [PASSED] drm_test_format_min_pitch_one_plane_16bpp
[13:15:12] [PASSED] drm_test_format_min_pitch_one_plane_24bpp
[13:15:12] [PASSED] drm_test_format_min_pitch_one_plane_32bpp
[13:15:12] [PASSED] drm_test_format_min_pitch_two_plane
[13:15:12] [PASSED] drm_test_format_min_pitch_three_plane_8bpp
[13:15:12] [PASSED] drm_test_format_min_pitch_tiled
[13:15:12] =================== [PASSED] drm_format ====================
[13:15:12] ============== drm_framebuffer (10 subtests) ===============
[13:15:12] ========== drm_test_framebuffer_check_src_coords  ==========
[13:15:12] [PASSED] Success: source fits into fb
[13:15:12] [PASSED] Fail: overflowing fb with x-axis coordinate
[13:15:12] [PASSED] Fail: overflowing fb with y-axis coordinate
[13:15:12] [PASSED] Fail: overflowing fb with source width
[13:15:12] [PASSED] Fail: overflowing fb with source height
[13:15:12] ====== [PASSED] drm_test_framebuffer_check_src_coords ======
[13:15:12] [PASSED] drm_test_framebuffer_cleanup
[13:15:12] =============== drm_test_framebuffer_create  ===============
[13:15:12] [PASSED] ABGR8888 normal sizes
[13:15:12] [PASSED] ABGR8888 max sizes
[13:15:12] [PASSED] ABGR8888 pitch greater than min required
[13:15:12] [PASSED] ABGR8888 pitch less than min required
[13:15:12] [PASSED] ABGR8888 Invalid width
[13:15:12] [PASSED] ABGR8888 Invalid buffer handle
[13:15:12] [PASSED] No pixel format
[13:15:12] [PASSED] ABGR8888 Width 0
[13:15:12] [PASSED] ABGR8888 Height 0
[13:15:12] [PASSED] ABGR8888 Out of bound height * pitch combination
[13:15:12] [PASSED] ABGR8888 Large buffer offset
[13:15:12] [PASSED] ABGR8888 Buffer offset for inexistent plane
[13:15:12] [PASSED] ABGR8888 Invalid flag
[13:15:12] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers
[13:15:12] [PASSED] ABGR8888 Valid buffer modifier
[13:15:12] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE)
[13:15:12] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] NV12 Normal sizes
[13:15:12] [PASSED] NV12 Max sizes
[13:15:12] [PASSED] NV12 Invalid pitch
[13:15:12] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag
[13:15:12] [PASSED] NV12 different  modifier per-plane
[13:15:12] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE
[13:15:12] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] NV12 Modifier for inexistent plane
[13:15:12] [PASSED] NV12 Handle for inexistent plane
[13:15:12] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier
[13:15:12] [PASSED] YVU420 Normal sizes
[13:15:12] [PASSED] YVU420 Max sizes
[13:15:12] [PASSED] YVU420 Invalid pitch
[13:15:12] [PASSED] YVU420 Different pitches
[13:15:12] [PASSED] YVU420 Different buffer offsets/pitches
[13:15:12] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS
[13:15:12] [PASSED] YVU420 Valid modifier
[13:15:12] [PASSED] YVU420 Different modifiers per plane
[13:15:12] [PASSED] YVU420 Modifier for inexistent plane
[13:15:12] [PASSED] YUV420_10BIT Invalid modifier(DRM_FORMAT_MOD_LINEAR)
[13:15:12] [PASSED] X0L2 Normal sizes
[13:15:12] [PASSED] X0L2 Max sizes
[13:15:12] [PASSED] X0L2 Invalid pitch
[13:15:12] [PASSED] X0L2 Pitch greater than minimum required
[13:15:12] [PASSED] X0L2 Handle for inexistent plane
[13:15:12] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set
[13:15:12] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set
[13:15:12] [PASSED] X0L2 Valid modifier
[13:15:12] [PASSED] X0L2 Modifier for inexistent plane
[13:15:12] =========== [PASSED] drm_test_framebuffer_create ===========
[13:15:12] [PASSED] drm_test_framebuffer_free
[13:15:12] [PASSED] drm_test_framebuffer_init
[13:15:12] [PASSED] drm_test_framebuffer_init_bad_format
[13:15:12] [PASSED] drm_test_framebuffer_init_dev_mismatch
[13:15:12] [PASSED] drm_test_framebuffer_lookup
[13:15:12] [PASSED] drm_test_framebuffer_lookup_inexistent
[13:15:12] [PASSED] drm_test_framebuffer_modifiers_not_supported
[13:15:12] ================= [PASSED] drm_framebuffer =================
[13:15:12] ================ drm_gem_shmem (8 subtests) ================
[13:15:12] [PASSED] drm_gem_shmem_test_obj_create
[13:15:12] [PASSED] drm_gem_shmem_test_obj_create_private
[13:15:12] [PASSED] drm_gem_shmem_test_pin_pages
[13:15:12] [PASSED] drm_gem_shmem_test_vmap
[13:15:12] [PASSED] drm_gem_shmem_test_get_pages_sgt
[13:15:12] [PASSED] drm_gem_shmem_test_get_sg_table
[13:15:12] [PASSED] drm_gem_shmem_test_madvise
[13:15:12] [PASSED] drm_gem_shmem_test_purge
[13:15:12] ================== [PASSED] drm_gem_shmem ==================
[13:15:12] === drm_atomic_helper_connector_hdmi_check (27 subtests) ===
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_auto_cea_mode_vic_1
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_full_cea_mode_vic_1
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_limited_cea_mode_vic_1
[13:15:12] ====== drm_test_check_broadcast_rgb_cea_mode_yuv420  =======
[13:15:12] [PASSED] Automatic
[13:15:12] [PASSED] Full
[13:15:12] [PASSED] Limited 16:235
[13:15:12] == [PASSED] drm_test_check_broadcast_rgb_cea_mode_yuv420 ===
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_changed
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_crtc_mode_not_changed
[13:15:12] [PASSED] drm_test_check_disable_connector
[13:15:12] [PASSED] drm_test_check_hdmi_funcs_reject_rate
[13:15:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_rgb
[13:15:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_yuv420
[13:15:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv422
[13:15:12] [PASSED] drm_test_check_max_tmds_rate_bpc_fallback_ignore_yuv420
[13:15:12] [PASSED] drm_test_check_driver_unsupported_fallback_yuv420
[13:15:12] [PASSED] drm_test_check_output_bpc_crtc_mode_changed
[13:15:12] [PASSED] drm_test_check_output_bpc_crtc_mode_not_changed
[13:15:12] [PASSED] drm_test_check_output_bpc_dvi
[13:15:12] [PASSED] drm_test_check_output_bpc_format_vic_1
[13:15:12] [PASSED] drm_test_check_output_bpc_format_display_8bpc_only
[13:15:12] [PASSED] drm_test_check_output_bpc_format_display_rgb_only
[13:15:12] [PASSED] drm_test_check_output_bpc_format_driver_8bpc_only
[13:15:12] [PASSED] drm_test_check_output_bpc_format_driver_rgb_only
[13:15:12] [PASSED] drm_test_check_tmds_char_rate_rgb_8bpc
[13:15:12] [PASSED] drm_test_check_tmds_char_rate_rgb_10bpc
[13:15:12] [PASSED] drm_test_check_tmds_char_rate_rgb_12bpc
[13:15:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_check ======
[13:15:12] === drm_atomic_helper_connector_hdmi_reset (6 subtests) ====
[13:15:12] [PASSED] drm_test_check_broadcast_rgb_value
[13:15:12] [PASSED] drm_test_check_bpc_8_value
[13:15:12] [PASSED] drm_test_check_bpc_10_value
[13:15:12] [PASSED] drm_test_check_bpc_12_value
[13:15:12] [PASSED] drm_test_check_format_value
[13:15:12] [PASSED] drm_test_check_tmds_char_value
[13:15:12] ===== [PASSED] drm_atomic_helper_connector_hdmi_reset ======
[13:15:12] = drm_atomic_helper_connector_hdmi_mode_valid (4 subtests) =
[13:15:12] [PASSED] drm_test_check_mode_valid
[13:15:12] [PASSED] drm_test_check_mode_valid_reject
[13:15:12] [PASSED] drm_test_check_mode_valid_reject_rate
[13:15:12] [PASSED] drm_test_check_mode_valid_reject_max_clock
[13:15:12] === [PASSED] drm_atomic_helper_connector_hdmi_mode_valid ===
[13:15:12] ================= drm_managed (2 subtests) =================
[13:15:12] [PASSED] drm_test_managed_release_action
[13:15:12] [PASSED] drm_test_managed_run_action
[13:15:12] =================== [PASSED] drm_managed ===================
[13:15:12] =================== drm_mm (6 subtests) ====================
[13:15:12] [PASSED] drm_test_mm_init
[13:15:12] [PASSED] drm_test_mm_debug
[13:15:12] [PASSED] drm_test_mm_align32
[13:15:12] [PASSED] drm_test_mm_align64
[13:15:12] [PASSED] drm_test_mm_lowest
[13:15:12] [PASSED] drm_test_mm_highest
[13:15:12] ===================== [PASSED] drm_mm ======================
[13:15:12] ============= drm_modes_analog_tv (5 subtests) =============
[13:15:12] [PASSED] drm_test_modes_analog_tv_mono_576i
[13:15:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i
[13:15:12] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined
[13:15:12] [PASSED] drm_test_modes_analog_tv_pal_576i
[13:15:12] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined
[13:15:12] =============== [PASSED] drm_modes_analog_tv ===============
[13:15:12] ============== drm_plane_helper (2 subtests) ===============
[13:15:12] =============== drm_test_check_plane_state  ================
[13:15:12] [PASSED] clipping_simple
[13:15:12] [PASSED] clipping_rotate_reflect
[13:15:12] [PASSED] positioning_simple
[13:15:12] [PASSED] upscaling
[13:15:12] [PASSED] downscaling
[13:15:12] [PASSED] rounding1
[13:15:12] [PASSED] rounding2
[13:15:12] [PASSED] rounding3
[13:15:12] [PASSED] rounding4
[13:15:12] =========== [PASSED] drm_test_check_plane_state ============
[13:15:12] =========== drm_test_check_invalid_plane_state  ============
[13:15:12] [PASSED] positioning_invalid
[13:15:12] [PASSED] upscaling_invalid
[13:15:12] [PASSED] downscaling_invalid
[13:15:12] ======= [PASSED] drm_test_check_invalid_plane_state ========
[13:15:12] ================ [PASSED] drm_plane_helper =================
[13:15:12] ====== drm_connector_helper_tv_get_modes (1 subtest) =======
[13:15:12] ====== drm_test_connector_helper_tv_get_modes_check  =======
[13:15:12] [PASSED] None
[13:15:12] [PASSED] PAL
[13:15:12] [PASSED] NTSC
[13:15:12] [PASSED] Both, NTSC Default
[13:15:12] [PASSED] Both, PAL Default
[13:15:12] [PASSED] Both, NTSC Default, with PAL on command-line
[13:15:12] [PASSED] Both, PAL Default, with NTSC on command-line
[13:15:12] == [PASSED] drm_test_connector_helper_tv_get_modes_check ===
[13:15:12] ======== [PASSED] drm_connector_helper_tv_get_modes ========
[13:15:12] ================== drm_rect (9 subtests) ===================
[13:15:12] [PASSED] drm_test_rect_clip_scaled_div_by_zero
[13:15:12] [PASSED] drm_test_rect_clip_scaled_not_clipped
[13:15:12] [PASSED] drm_test_rect_clip_scaled_clipped
[13:15:12] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned
[13:15:12] ================= drm_test_rect_intersect  =================
[13:15:12] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0
[13:15:12] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1
[13:15:12] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0
[13:15:12] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1
[13:15:12] [PASSED] right x left: 2x1+0+0 x 3x1+1+0
[13:15:12] [PASSED] left x right: 3x1+1+0 x 2x1+0+0
[13:15:12] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1
[13:15:12] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0
[13:15:12] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1
[13:15:12] [PASSED] touching side: 1x1+0+0 x 1x1+1+0
[13:15:12] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0
[13:15:12] [PASSED] inside another: 2x2+0+0 x 1x1+1+1
[13:15:12] [PASSED] far away: 1x1+0+0 x 1x1+3+6
[13:15:12] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10
[13:15:12] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10
[13:15:12] ============= [PASSED] drm_test_rect_intersect =============
[13:15:12] ================ drm_test_rect_calc_hscale  ================
[13:15:12] [PASSED] normal use
[13:15:12] [PASSED] out of max range
[13:15:12] [PASSED] out of min range
[13:15:12] [PASSED] zero dst
[13:15:12] [PASSED] negative src
[13:15:12] [PASSED] negative dst
[13:15:12] ============ [PASSED] drm_test_rect_calc_hscale ============
[13:15:12] ================ drm_test_rect_calc_vscale  ================
[13:15:12] [PASSED] normal use
[13:15:12] [PASSED] out of max range
[13:15:12] [PASSED] out of min range
[13:15:12] [PASSED] zero dst
[13:15:12] [PASSED] negative src
[13:15:12] [PASSED] negative dst
stty: 'standard input': Inappropriate ioctl for device
[13:15:12] ============ [PASSED] drm_test_rect_calc_vscale ============
[13:15:12] ================== drm_test_rect_rotate  ===================
[13:15:12] [PASSED] reflect-x
[13:15:12] [PASSED] reflect-y
[13:15:12] [PASSED] rotate-0
[13:15:12] [PASSED] rotate-90
[13:15:12] [PASSED] rotate-180
[13:15:12] [PASSED] rotate-270
[13:15:12] ============== [PASSED] drm_test_rect_rotate ===============
[13:15:12] ================ drm_test_rect_rotate_inv  =================
[13:15:12] [PASSED] reflect-x
[13:15:12] [PASSED] reflect-y
[13:15:12] [PASSED] rotate-0
[13:15:12] [PASSED] rotate-90
[13:15:12] [PASSED] rotate-180
[13:15:12] [PASSED] rotate-270
[13:15:12] ============ [PASSED] drm_test_rect_rotate_inv =============
[13:15:12] ==================== [PASSED] drm_rect =====================
[13:15:12] ============================================================
[13:15:12] Testing complete. Ran 616 tests: passed: 616
[13:15:12] Elapsed time: 23.755s total, 1.676s configuring, 21.910s building, 0.147s running

+ /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/ttm/tests/.kunitconfig
[13:15:12] Configuring KUnit Kernel ...
Regenerating .config ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
[13:15:14] Building KUnit Kernel ...
Populating config with:
$ make ARCH=um O=.kunit olddefconfig
Building with:
$ make all compile_commands.json scripts_gdb ARCH=um O=.kunit --jobs=48
[13:15:22] Starting KUnit Kernel (1/1)...
[13:15:22] ============================================================
Running tests with:
$ .kunit/linux kunit.enable=1 mem=1G console=tty kunit_shutdown=halt
[13:15:22] ================= ttm_device (5 subtests) ==================
[13:15:22] [PASSED] ttm_device_init_basic
[13:15:22] [PASSED] ttm_device_init_multiple
[13:15:22] [PASSED] ttm_device_fini_basic
[13:15:22] [PASSED] ttm_device_init_no_vma_man
[13:15:22] ================== ttm_device_init_pools  ==================
[13:15:22] [PASSED] No DMA allocations, no DMA32 required
[13:15:22] [PASSED] DMA allocations, DMA32 required
[13:15:22] [PASSED] No DMA allocations, DMA32 required
[13:15:22] [PASSED] DMA allocations, no DMA32 required
[13:15:22] ============== [PASSED] ttm_device_init_pools ==============
[13:15:22] =================== [PASSED] ttm_device ====================
[13:15:22] ================== ttm_pool (8 subtests) ===================
[13:15:22] ================== ttm_pool_alloc_basic  ===================
[13:15:22] [PASSED] One page
[13:15:22] [PASSED] More than one page
[13:15:22] [PASSED] Above the allocation limit
[13:15:22] [PASSED] One page, with coherent DMA mappings enabled
[13:15:22] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:15:22] ============== [PASSED] ttm_pool_alloc_basic ===============
[13:15:22] ============== ttm_pool_alloc_basic_dma_addr  ==============
[13:15:22] [PASSED] One page
[13:15:22] [PASSED] More than one page
[13:15:22] [PASSED] Above the allocation limit
[13:15:22] [PASSED] One page, with coherent DMA mappings enabled
[13:15:22] [PASSED] Above the allocation limit, with coherent DMA mappings enabled
[13:15:22] ========== [PASSED] ttm_pool_alloc_basic_dma_addr ==========
[13:15:22] [PASSED] ttm_pool_alloc_order_caching_match
[13:15:22] [PASSED] ttm_pool_alloc_caching_mismatch
[13:15:22] [PASSED] ttm_pool_alloc_order_mismatch
[13:15:22] [PASSED] ttm_pool_free_dma_alloc
[13:15:22] [PASSED] ttm_pool_free_no_dma_alloc
[13:15:22] [PASSED] ttm_pool_fini_basic
[13:15:22] ==================== [PASSED] ttm_pool =====================
[13:15:22] ================ ttm_resource (8 subtests) =================
[13:15:22] ================= ttm_resource_init_basic  =================
[13:15:22] [PASSED] Init resource in TTM_PL_SYSTEM
[13:15:22] [PASSED] Init resource in TTM_PL_VRAM
[13:15:22] [PASSED] Init resource in a private placement
[13:15:22] [PASSED] Init resource in TTM_PL_SYSTEM, set placement flags
[13:15:22] ============= [PASSED] ttm_resource_init_basic =============
[13:15:22] [PASSED] ttm_resource_init_pinned
[13:15:22] [PASSED] ttm_resource_fini_basic
[13:15:22] [PASSED] ttm_resource_manager_init_basic
[13:15:22] [PASSED] ttm_resource_manager_usage_basic
[13:15:22] [PASSED] ttm_resource_manager_set_used_basic
[13:15:22] [PASSED] ttm_sys_man_alloc_basic
[13:15:22] [PASSED] ttm_sys_man_free_basic
[13:15:22] ================== [PASSED] ttm_resource ===================
[13:15:22] =================== ttm_tt (15 subtests) ===================
[13:15:22] ==================== ttm_tt_init_basic  ====================
[13:15:22] [PASSED] Page-aligned size
[13:15:22] [PASSED] Extra pages requested
[13:15:22] ================ [PASSED] ttm_tt_init_basic ================
[13:15:22] [PASSED] ttm_tt_init_misaligned
[13:15:22] [PASSED] ttm_tt_fini_basic
[13:15:22] [PASSED] ttm_tt_fini_sg
[13:15:22] [PASSED] ttm_tt_fini_shmem
[13:15:22] [PASSED] ttm_tt_create_basic
[13:15:22] [PASSED] ttm_tt_create_invalid_bo_type
[13:15:22] [PASSED] ttm_tt_create_ttm_exists
[13:15:22] [PASSED] ttm_tt_create_failed
[13:15:22] [PASSED] ttm_tt_destroy_basic
[13:15:22] [PASSED] ttm_tt_populate_null_ttm
[13:15:22] [PASSED] ttm_tt_populate_populated_ttm
[13:15:22] [PASSED] ttm_tt_unpopulate_basic
[13:15:22] [PASSED] ttm_tt_unpopulate_empty_ttm
[13:15:22] [PASSED] ttm_tt_swapin_basic
[13:15:22] ===================== [PASSED] ttm_tt ======================
[13:15:22] =================== ttm_bo (14 subtests) ===================
[13:15:22] =========== ttm_bo_reserve_optimistic_no_ticket  ===========
[13:15:22] [PASSED] Cannot be interrupted and sleeps
[13:15:22] [PASSED] Cannot be interrupted, locks straight away
[13:15:22] [PASSED] Can be interrupted, sleeps
[13:15:22] ======= [PASSED] ttm_bo_reserve_optimistic_no_ticket =======
[13:15:22] [PASSED] ttm_bo_reserve_locked_no_sleep
[13:15:22] [PASSED] ttm_bo_reserve_no_wait_ticket
[13:15:22] [PASSED] ttm_bo_reserve_double_resv
[13:15:22] [PASSED] ttm_bo_reserve_interrupted
[13:15:22] [PASSED] ttm_bo_reserve_deadlock
[13:15:22] [PASSED] ttm_bo_unreserve_basic
[13:15:22] [PASSED] ttm_bo_unreserve_pinned
[13:15:22] [PASSED] ttm_bo_unreserve_bulk
[13:15:22] [PASSED] ttm_bo_put_basic
[13:15:22] [PASSED] ttm_bo_put_shared_resv
[13:15:22] [PASSED] ttm_bo_pin_basic
[13:15:22] [PASSED] ttm_bo_pin_unpin_resource
[13:15:22] [PASSED] ttm_bo_multiple_pin_one_unpin
[13:15:22] ===================== [PASSED] ttm_bo ======================
[13:15:22] ============== ttm_bo_validate (22 subtests) ===============
[13:15:22] ============== ttm_bo_init_reserved_sys_man  ===============
[13:15:22] [PASSED] Buffer object for userspace
[13:15:22] [PASSED] Kernel buffer object
[13:15:22] [PASSED] Shared buffer object
[13:15:22] ========== [PASSED] ttm_bo_init_reserved_sys_man ===========
[13:15:22] ============== ttm_bo_init_reserved_mock_man  ==============
[13:15:22] [PASSED] Buffer object for userspace
[13:15:22] [PASSED] Kernel buffer object
[13:15:22] [PASSED] Shared buffer object
[13:15:22] ========== [PASSED] ttm_bo_init_reserved_mock_man ==========
[13:15:22] [PASSED] ttm_bo_init_reserved_resv
[13:15:22] ================== ttm_bo_validate_basic  ==================
[13:15:22] [PASSED] Buffer object for userspace
[13:15:22] [PASSED] Kernel buffer object
[13:15:22] [PASSED] Shared buffer object
[13:15:22] ============== [PASSED] ttm_bo_validate_basic ==============
[13:15:22] [PASSED] ttm_bo_validate_invalid_placement
[13:15:22] ============= ttm_bo_validate_same_placement  ==============
[13:15:22] [PASSED] System manager
[13:15:22] [PASSED] VRAM manager
[13:15:22] ========= [PASSED] ttm_bo_validate_same_placement ==========
[13:15:22] [PASSED] ttm_bo_validate_failed_alloc
[13:15:22] [PASSED] ttm_bo_validate_pinned
[13:15:22] [PASSED] ttm_bo_validate_busy_placement
[13:15:22] ================ ttm_bo_validate_multihop  =================
[13:15:22] [PASSED] Buffer object for userspace
[13:15:22] [PASSED] Kernel buffer object
[13:15:22] [PASSED] Shared buffer object
[13:15:22] ============ [PASSED] ttm_bo_validate_multihop =============
[13:15:22] ========== ttm_bo_validate_no_placement_signaled  ==========
[13:15:22] [PASSED] Buffer object in system domain, no page vector
[13:15:22] [PASSED] Buffer object in system domain with an existing page vector
[13:15:22] ====== [PASSED] ttm_bo_validate_no_placement_signaled ======
[13:15:22] ======== ttm_bo_validate_no_placement_not_signaled  ========
[13:15:22] [PASSED] Buffer object for userspace
[13:15:22] [PASSED] Kernel buffer object
[13:15:22] [PASSED] Shared buffer object
[13:15:22] ==== [PASSED] ttm_bo_validate_no_placement_not_signaled ====
[13:15:22] [PASSED] ttm_bo_validate_move_fence_signaled
[13:15:22] ========= ttm_bo_validate_move_fence_not_signaled  =========
[13:15:22] [PASSED] Waits for GPU
[13:15:22] [PASSED] Tries to lock straight away
[13:15:22] ===== [PASSED] ttm_bo_validate_move_fence_not_signaled =====
[13:15:22] [PASSED] ttm_bo_validate_swapout
[13:15:22] [PASSED] ttm_bo_validate_happy_evict
[13:15:22] [PASSED] ttm_bo_validate_all_pinned_evict
[13:15:22] [PASSED] ttm_bo_validate_allowed_only_evict
[13:15:22] [PASSED] ttm_bo_validate_deleted_evict
[13:15:22] [PASSED] ttm_bo_validate_busy_domain_evict
[13:15:22] [PASSED] ttm_bo_validate_evict_gutting
[13:15:22] [PASSED] ttm_bo_validate_recrusive_evict
stty: 'standard input': Inappropriate ioctl for device
[13:15:22] ================= [PASSED] ttm_bo_validate =================
[13:15:22] ============================================================
[13:15:22] Testing complete. Ran 102 tests: passed: 102
[13:15:22] Elapsed time: 10.038s total, 1.657s configuring, 7.764s building, 0.530s running

+ cleanup
++ stat -c %u:%g /kernel
+ chown -R 1003:1003 /kernel

✓ Xe.CI.BAT: success for drm/i915/display: make all global state opaque

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 1583 bytes --]

== Series Details ==

Series: drm/i915/display: make all global state opaque
URL   : https://patchwork.freedesktop.org/series/150157/
State : success

== Summary ==

CI Bug Log - changes from xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303_BAT -> xe-pw-150157v1_BAT
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Participating hosts (7 -> 7)
------------------------------

  No changes in participating hosts

Known issues
------------

  Here are the changes found in xe-pw-150157v1_BAT that come from known issues:

### IGT changes ###

#### Warnings ####

  * igt@sriov_basic@enable-vfs-autoprobe-on:
    - bat-adlp-7:         [INCOMPLETE][1] ([Intel XE#5214]) -> [ABORT][2] ([Intel XE#5214]) +1 other test abort
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/bat-adlp-7/igt@sriov_basic@enable-vfs-autoprobe-on.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/bat-adlp-7/igt@sriov_basic@enable-vfs-autoprobe-on.html

  
  [Intel XE#5214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5214


Build changes
-------------

  * Linux: xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303 -> xe-pw-150157v1

  IGT_8406: 12d7c99650c85e479571b6db2c392408be474c88 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303: 97cffe7577962cb45e3a66d758f9a7cd2633c303
  xe-pw-150157v1: 150157v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/index.html

[-- Attachment #2: Type: text/html, Size: 2217 bytes --]

✗ Xe.CI.Full: failure for drm/i915/display: make all global state opaque

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 60329 bytes --]

== Series Details ==

Series: drm/i915/display: make all global state opaque
URL   : https://patchwork.freedesktop.org/series/150157/
State : failure

== Summary ==

CI Bug Log - changes from xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303_FULL -> xe-pw-150157v1_FULL
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with xe-pw-150157v1_FULL absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in xe-pw-150157v1_FULL, please notify your bug team (I915-ci-infra@lists.freedesktop.org) to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (4 -> 4)
------------------------------

  No changes in participating hosts

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in xe-pw-150157v1_FULL:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_cursor_legacy@cursor-vs-flip-toggle:
    - shard-lnl:          [PASS][1] -> [ABORT][2]
   [1]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-lnl-4/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html
   [2]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-3/igt@kms_cursor_legacy@cursor-vs-flip-toggle.html

  * igt@xe_exec_system_allocator@twice-large-mmap-new-nomemset:
    - shard-bmg:          [PASS][3] -> [FAIL][4]
   [3]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-3/igt@xe_exec_system_allocator@twice-large-mmap-new-nomemset.html
   [4]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-3/igt@xe_exec_system_allocator@twice-large-mmap-new-nomemset.html

  
#### Warnings ####

  * igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random:
    - shard-adlp:         [ABORT][5] ([Intel XE#5214]) -> [DMESG-FAIL][6] +1 other test dmesg-fail
   [5]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-9/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html
   [6]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-2/igt@xe_sriov_scheduling@nonpreempt-engine-resets@numvfs-random.html

  
Known issues
------------

  Here are the changes found in xe-pw-150157v1_FULL that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@intel_hwmon@hwmon-read:
    - shard-lnl:          NOTRUN -> [SKIP][7] ([Intel XE#1125])
   [7]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@intel_hwmon@hwmon-read.html
    - shard-adlp:         NOTRUN -> [SKIP][8] ([Intel XE#1125])
   [8]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@intel_hwmon@hwmon-read.html

  * igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
    - shard-dg2-set2:     NOTRUN -> [SKIP][9] ([Intel XE#623])
   [9]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html

  * igt@kms_big_fb@4-tiled-64bpp-rotate-270:
    - shard-dg2-set2:     NOTRUN -> [SKIP][10] ([Intel XE#316])
   [10]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_big_fb@4-tiled-64bpp-rotate-270.html

  * igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0:
    - shard-adlp:         NOTRUN -> [SKIP][11] ([Intel XE#1124]) +1 other test skip
   [11]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0.html

  * igt@kms_big_fb@y-tiled-64bpp-rotate-90:
    - shard-adlp:         NOTRUN -> [SKIP][12] ([Intel XE#316])
   [12]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_big_fb@y-tiled-64bpp-rotate-90.html

  * igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
    - shard-lnl:          NOTRUN -> [SKIP][13] ([Intel XE#1124]) +2 other tests skip
   [13]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
    - shard-dg2-set2:     NOTRUN -> [SKIP][14] ([Intel XE#1124]) +1 other test skip
   [14]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_big_fb@yf-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html

  * igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p:
    - shard-dg2-set2:     NOTRUN -> [SKIP][15] ([Intel XE#2191])
   [15]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_bw@connected-linear-tiling-4-displays-3840x2160p.html

  * igt@kms_bw@linear-tiling-3-displays-2560x1440p:
    - shard-lnl:          NOTRUN -> [SKIP][16] ([Intel XE#367])
   [16]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html
    - shard-adlp:         NOTRUN -> [SKIP][17] ([Intel XE#367])
   [17]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_bw@linear-tiling-3-displays-2560x1440p.html

  * igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2:
    - shard-bmg:          NOTRUN -> [SKIP][18] ([Intel XE#2652] / [Intel XE#787]) +3 other tests skip
   [18]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_ccs@bad-rotation-90-4-tiled-lnl-ccs@pipe-c-dp-2.html

  * igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc:
    - shard-lnl:          NOTRUN -> [SKIP][19] ([Intel XE#2887]) +5 other tests skip
   [19]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_ccs@ccs-on-another-bo-4-tiled-mtl-rc-ccs-cc.html

  * igt@kms_ccs@crc-primary-basic-y-tiled-ccs:
    - shard-adlp:         NOTRUN -> [SKIP][20] ([Intel XE#455] / [Intel XE#787]) +7 other tests skip
   [20]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_ccs@crc-primary-basic-y-tiled-ccs.html

  * igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1:
    - shard-adlp:         NOTRUN -> [SKIP][21] ([Intel XE#787]) +11 other tests skip
   [21]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_ccs@crc-primary-rotation-180-yf-tiled-ccs@pipe-c-hdmi-a-1.html

  * igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2:
    - shard-dg2-set2:     NOTRUN -> [SKIP][22] ([Intel XE#787]) +97 other tests skip
   [22]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-432/igt@kms_ccs@crc-primary-suspend-y-tiled-gen12-rc-ccs@pipe-c-hdmi-a-2.html

  * igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][23] ([Intel XE#455] / [Intel XE#787]) +18 other tests skip
   [23]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_ccs@missing-ccs-buffer-4-tiled-mtl-mc-ccs@pipe-d-dp-4.html

  * igt@kms_cdclk@plane-scaling@pipe-b-dp-4:
    - shard-dg2-set2:     NOTRUN -> [SKIP][24] ([Intel XE#4416]) +3 other tests skip
   [24]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_cdclk@plane-scaling@pipe-b-dp-4.html

  * igt@kms_chamelium_color@ctm-negative:
    - shard-lnl:          NOTRUN -> [SKIP][25] ([Intel XE#306])
   [25]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_chamelium_color@ctm-negative.html
    - shard-adlp:         NOTRUN -> [SKIP][26] ([Intel XE#306])
   [26]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_chamelium_color@ctm-negative.html

  * igt@kms_chamelium_edid@hdmi-edid-read:
    - shard-dg2-set2:     NOTRUN -> [SKIP][27] ([Intel XE#373]) +1 other test skip
   [27]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_chamelium_edid@hdmi-edid-read.html

  * igt@kms_chamelium_hpd@dp-hpd-storm-disable:
    - shard-adlp:         NOTRUN -> [SKIP][28] ([Intel XE#373]) +1 other test skip
   [28]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html
    - shard-lnl:          NOTRUN -> [SKIP][29] ([Intel XE#373]) +3 other tests skip
   [29]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_chamelium_hpd@dp-hpd-storm-disable.html

  * igt@kms_content_protection@atomic@pipe-a-dp-2:
    - shard-bmg:          NOTRUN -> [FAIL][30] ([Intel XE#1178])
   [30]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_content_protection@atomic@pipe-a-dp-2.html

  * igt@kms_content_protection@lic-type-0:
    - shard-lnl:          NOTRUN -> [SKIP][31] ([Intel XE#5176])
   [31]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_content_protection@lic-type-0.html

  * igt@kms_cursor_crc@cursor-offscreen-512x170:
    - shard-lnl:          NOTRUN -> [SKIP][32] ([Intel XE#2321])
   [32]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_cursor_crc@cursor-offscreen-512x170.html
    - shard-adlp:         NOTRUN -> [SKIP][33] ([Intel XE#308])
   [33]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_cursor_crc@cursor-offscreen-512x170.html

  * igt@kms_cursor_crc@cursor-random-512x512:
    - shard-dg2-set2:     NOTRUN -> [SKIP][34] ([Intel XE#308])
   [34]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_cursor_crc@cursor-random-512x512.html

  * igt@kms_cursor_crc@cursor-sliding-32x10:
    - shard-lnl:          NOTRUN -> [SKIP][35] ([Intel XE#1424])
   [35]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_cursor_crc@cursor-sliding-32x10.html

  * igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy:
    - shard-adlp:         NOTRUN -> [SKIP][36] ([Intel XE#309])
   [36]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html
    - shard-lnl:          NOTRUN -> [SKIP][37] ([Intel XE#309])
   [37]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_cursor_legacy@2x-flip-vs-cursor-legacy.html

  * igt@kms_cursor_legacy@cursora-vs-flipb-varying-size:
    - shard-bmg:          [PASS][38] -> [SKIP][39] ([Intel XE#2291]) +2 other tests skip
   [38]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-2/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html
   [39]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_cursor_legacy@cursora-vs-flipb-varying-size.html

  * igt@kms_dirtyfb@drrs-dirtyfb-ioctl:
    - shard-lnl:          NOTRUN -> [SKIP][40] ([Intel XE#1508])
   [40]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_dirtyfb@drrs-dirtyfb-ioctl.html

  * igt@kms_dp_link_training@uhbr-sst:
    - shard-dg2-set2:     NOTRUN -> [SKIP][41] ([Intel XE#4356])
   [41]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_dp_link_training@uhbr-sst.html

  * igt@kms_dsc@dsc-with-formats:
    - shard-lnl:          NOTRUN -> [SKIP][42] ([Intel XE#2244])
   [42]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_dsc@dsc-with-formats.html

  * igt@kms_feature_discovery@display-4x:
    - shard-adlp:         NOTRUN -> [SKIP][43] ([Intel XE#1138])
   [43]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_feature_discovery@display-4x.html
    - shard-lnl:          NOTRUN -> [SKIP][44] ([Intel XE#1138])
   [44]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_feature_discovery@display-4x.html

  * igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
    - shard-lnl:          NOTRUN -> [SKIP][45] ([Intel XE#1421]) +3 other tests skip
   [45]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html

  * igt@kms_flip@2x-flip-vs-modeset-vs-hang:
    - shard-adlp:         NOTRUN -> [SKIP][46] ([Intel XE#310]) +2 other tests skip
   [46]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_flip@2x-flip-vs-modeset-vs-hang.html

  * igt@kms_flip@bo-too-big-interruptible@a-edp1:
    - shard-lnl:          NOTRUN -> [TIMEOUT][47] ([Intel XE#1504]) +1 other test timeout
   [47]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_flip@bo-too-big-interruptible@a-edp1.html

  * igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible:
    - shard-lnl:          [PASS][48] -> [FAIL][49] ([Intel XE#886]) +1 other test fail
   [48]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-lnl-1/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html
   [49]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-2/igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank:
    - shard-adlp:         [PASS][50] -> [FAIL][51] ([Intel XE#3098] / [Intel XE#886])
   [50]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [51]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank.html
    - shard-dg2-set2:     [PASS][52] -> [FAIL][53] ([Intel XE#886])
   [52]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-434/igt@kms_flip@flip-vs-blocking-wf-vblank.html
   [53]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-432/igt@kms_flip@flip-vs-blocking-wf-vblank.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a2:
    - shard-dg2-set2:     NOTRUN -> [FAIL][54] ([Intel XE#886])
   [54]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-432/igt@kms_flip@flip-vs-blocking-wf-vblank@a-hdmi-a2.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1:
    - shard-adlp:         [PASS][55] -> [FAIL][56] ([Intel XE#3098])
   [55]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html
   [56]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank@b-hdmi-a1.html

  * igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1:
    - shard-adlp:         [PASS][57] -> [FAIL][58] ([Intel XE#886]) +1 other test fail
   [57]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html
   [58]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-4/igt@kms_flip@flip-vs-blocking-wf-vblank@c-hdmi-a1.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [PASS][59] -> [FAIL][60] ([Intel XE#3321]) +2 other tests fail
   [59]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html
   [60]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_flip@flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4:
    - shard-dg2-set2:     [PASS][61] -> [FAIL][62] ([Intel XE#301]) +9 other tests fail
   [61]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html
   [62]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-436/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-dp4.html

  * igt@kms_flip@flip-vs-suspend:
    - shard-bmg:          [PASS][63] -> [INCOMPLETE][64] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [63]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-7/igt@kms_flip@flip-vs-suspend.html
   [64]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-5/igt@kms_flip@flip-vs-suspend.html

  * igt@kms_flip@flip-vs-suspend@d-dp4:
    - shard-dg2-set2:     [PASS][65] -> [INCOMPLETE][66] ([Intel XE#2049] / [Intel XE#2597]) +1 other test incomplete
   [65]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-433/igt@kms_flip@flip-vs-suspend@d-dp4.html
   [66]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-435/igt@kms_flip@flip-vs-suspend@d-dp4.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-dg2-set2:     NOTRUN -> [SKIP][67] ([Intel XE#455]) +5 other tests skip
   [67]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling:
    - shard-lnl:          NOTRUN -> [SKIP][68] ([Intel XE#1397] / [Intel XE#1745])
   [68]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling.html

  * igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode:
    - shard-lnl:          NOTRUN -> [SKIP][69] ([Intel XE#1397])
   [69]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_flip_scaled_crc@flip-64bpp-xtile-to-32bpp-xtile-downscaling@pipe-a-default-mode.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y:
    - shard-adlp:         [PASS][70] -> [DMESG-FAIL][71] ([Intel XE#4543])
   [70]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html
   [71]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-y-to-y.html

  * igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt:
    - shard-dg2-set2:     NOTRUN -> [SKIP][72] ([Intel XE#651]) +7 other tests skip
   [72]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_frontbuffer_tracking@drrs-1p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render:
    - shard-lnl:          NOTRUN -> [SKIP][73] ([Intel XE#651]) +5 other tests skip
   [73]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html
    - shard-adlp:         NOTRUN -> [SKIP][74] ([Intel XE#651]) +3 other tests skip
   [74]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-1p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render:
    - shard-adlp:         NOTRUN -> [SKIP][75] ([Intel XE#656]) +5 other tests skip
   [75]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt:
    - shard-lnl:          NOTRUN -> [SKIP][76] ([Intel XE#656]) +10 other tests skip
   [76]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_frontbuffer_tracking@fbcdrrs-2p-scndscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@pipe-fbc-rte:
    - shard-adlp:         NOTRUN -> [SKIP][77] ([Intel XE#455]) +3 other tests skip
   [77]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_frontbuffer_tracking@pipe-fbc-rte.html

  * igt@kms_frontbuffer_tracking@plane-fbc-rte:
    - shard-dg2-set2:     NOTRUN -> [SKIP][78] ([Intel XE#1158])
   [78]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_frontbuffer_tracking@plane-fbc-rte.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc:
    - shard-dg2-set2:     NOTRUN -> [SKIP][79] ([Intel XE#653]) +8 other tests skip
   [79]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_frontbuffer_tracking@psr-1p-primscrn-pri-shrfb-draw-mmap-wc.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt:
    - shard-adlp:         NOTRUN -> [SKIP][80] ([Intel XE#653]) +4 other tests skip
   [80]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-plflip-blt.html

  * igt@kms_joiner@basic-max-non-joiner:
    - shard-lnl:          NOTRUN -> [SKIP][81] ([Intel XE#4298])
   [81]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_joiner@basic-max-non-joiner.html
    - shard-adlp:         NOTRUN -> [SKIP][82] ([Intel XE#4298])
   [82]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_joiner@basic-max-non-joiner.html

  * igt@kms_pipe_stress@stress-xrgb8888-ytiled:
    - shard-dg2-set2:     NOTRUN -> [SKIP][83] ([Intel XE#4359])
   [83]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_pipe_stress@stress-xrgb8888-ytiled.html

  * igt@kms_plane_multiple@tiling-y:
    - shard-lnl:          NOTRUN -> [SKIP][84] ([Intel XE#5020])
   [84]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_plane_multiple@tiling-y.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a:
    - shard-lnl:          NOTRUN -> [SKIP][85] ([Intel XE#2763]) +3 other tests skip
   [85]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a.html

  * igt@kms_pm_backlight@brightness-with-dpms:
    - shard-dg2-set2:     NOTRUN -> [SKIP][86] ([Intel XE#2938])
   [86]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_pm_backlight@brightness-with-dpms.html

  * igt@kms_pm_dc@dc5-psr:
    - shard-adlp:         NOTRUN -> [SKIP][87] ([Intel XE#1129])
   [87]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_pm_dc@dc5-psr.html

  * igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area:
    - shard-lnl:          NOTRUN -> [SKIP][88] ([Intel XE#2893]) +1 other test skip
   [88]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_psr2_sf@fbc-pr-overlay-plane-update-sf-dmg-area.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf:
    - shard-lnl:          NOTRUN -> [SKIP][89] ([Intel XE#2893] / [Intel XE#4608])
   [89]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1:
    - shard-lnl:          NOTRUN -> [SKIP][90] ([Intel XE#4608]) +1 other test skip
   [90]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-sf@pipe-a-edp-1.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf:
    - shard-dg2-set2:     NOTRUN -> [SKIP][91] ([Intel XE#1489]) +2 other tests skip
   [91]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-fully-sf.html

  * igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf:
    - shard-adlp:         NOTRUN -> [SKIP][92] ([Intel XE#1489]) +1 other test skip
   [92]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_psr2_sf@psr2-overlay-plane-move-continuous-exceed-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-adlp:         NOTRUN -> [SKIP][93] ([Intel XE#1122])
   [93]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_psr2_su@page_flip-xrgb8888.html
    - shard-lnl:          NOTRUN -> [SKIP][94] ([Intel XE#1128])
   [94]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@fbc-pr-sprite-render:
    - shard-dg2-set2:     NOTRUN -> [SKIP][95] ([Intel XE#2850] / [Intel XE#929]) +4 other tests skip
   [95]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_psr@fbc-pr-sprite-render.html

  * igt@kms_psr@fbc-psr-sprite-blt:
    - shard-adlp:         NOTRUN -> [SKIP][96] ([Intel XE#2850] / [Intel XE#929]) +2 other tests skip
   [96]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_psr@fbc-psr-sprite-blt.html

  * igt@kms_rotation_crc@primary-4-tiled-reflect-x-0:
    - shard-lnl:          NOTRUN -> [SKIP][97] ([Intel XE#3414] / [Intel XE#3904]) +1 other test skip
   [97]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_rotation_crc@primary-4-tiled-reflect-x-0.html

  * igt@kms_setmode@invalid-clone-single-crtc-stealing:
    - shard-lnl:          NOTRUN -> [SKIP][98] ([Intel XE#1435])
   [98]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@kms_setmode@invalid-clone-single-crtc-stealing.html

  * igt@kms_vrr@lobf:
    - shard-lnl:          NOTRUN -> [SKIP][99] ([Intel XE#1499])
   [99]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-1/igt@kms_vrr@lobf.html

  * igt@xe_ccs@suspend-resume:
    - shard-adlp:         NOTRUN -> [SKIP][100] ([Intel XE#455] / [Intel XE#488])
   [100]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_ccs@suspend-resume.html

  * igt@xe_copy_basic@mem-copy-linear-0xfffe:
    - shard-dg2-set2:     NOTRUN -> [SKIP][101] ([Intel XE#1123])
   [101]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_copy_basic@mem-copy-linear-0xfffe.html

  * igt@xe_eu_stall@invalid-event-report-count:
    - shard-dg2-set2:     NOTRUN -> [SKIP][102] ([Intel XE#4497])
   [102]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_eu_stall@invalid-event-report-count.html

  * igt@xe_eudebug@basic-vm-access-parameters:
    - shard-dg2-set2:     NOTRUN -> [SKIP][103] ([Intel XE#4837]) +4 other tests skip
   [103]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_eudebug@basic-vm-access-parameters.html

  * igt@xe_eudebug_online@reset-with-attention:
    - shard-adlp:         NOTRUN -> [SKIP][104] ([Intel XE#4837]) +1 other test skip
   [104]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_eudebug_online@reset-with-attention.html
    - shard-lnl:          NOTRUN -> [SKIP][105] ([Intel XE#4837]) +2 other tests skip
   [105]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_eudebug_online@reset-with-attention.html

  * igt@xe_evict@evict-beng-small-multi-vm:
    - shard-adlp:         NOTRUN -> [SKIP][106] ([Intel XE#261] / [Intel XE#688]) +1 other test skip
   [106]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_evict@evict-beng-small-multi-vm.html

  * igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd:
    - shard-adlp:         NOTRUN -> [SKIP][107] ([Intel XE#688])
   [107]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html
    - shard-lnl:          NOTRUN -> [SKIP][108] ([Intel XE#688]) +2 other tests skip
   [108]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_evict_ccs@evict-overcommit-parallel-instantfree-samefd.html

  * igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate:
    - shard-adlp:         NOTRUN -> [SKIP][109] ([Intel XE#1392]) +1 other test skip
   [109]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html
    - shard-lnl:          NOTRUN -> [SKIP][110] ([Intel XE#1392]) +1 other test skip
   [110]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_exec_basic@multigpu-many-execqueues-many-vm-bindexecqueue-userptr-invalidate.html

  * igt@xe_exec_basic@multigpu-once-null-rebind:
    - shard-dg2-set2:     [PASS][111] -> [SKIP][112] ([Intel XE#1392]) +2 other tests skip
   [111]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-434/igt@xe_exec_basic@multigpu-once-null-rebind.html
   [112]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-432/igt@xe_exec_basic@multigpu-once-null-rebind.html

  * igt@xe_exec_fault_mode@many-bindexecqueue-userptr-rebind:
    - shard-adlp:         NOTRUN -> [SKIP][113] ([Intel XE#288]) +5 other tests skip
   [113]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_exec_fault_mode@many-bindexecqueue-userptr-rebind.html

  * igt@xe_exec_fault_mode@once-bindexecqueue-rebind:
    - shard-dg2-set2:     NOTRUN -> [SKIP][114] ([Intel XE#288]) +7 other tests skip
   [114]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_exec_fault_mode@once-bindexecqueue-rebind.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge:
    - shard-lnl:          NOTRUN -> [SKIP][115] ([Intel XE#4943]) +10 other tests skip
   [115]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_exec_system_allocator@many-execqueues-mmap-new-huge.html

  * igt@xe_exec_system_allocator@many-execqueues-mmap-nomemset:
    - shard-adlp:         NOTRUN -> [SKIP][116] ([Intel XE#4915]) +44 other tests skip
   [116]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_exec_system_allocator@many-execqueues-mmap-nomemset.html

  * igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race-nomemset:
    - shard-dg2-set2:     NOTRUN -> [SKIP][117] ([Intel XE#4915]) +73 other tests skip
   [117]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_exec_system_allocator@threads-shared-vm-many-large-execqueues-mmap-new-race-nomemset.html

  * igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit:
    - shard-adlp:         NOTRUN -> [SKIP][118] ([Intel XE#2229])
   [118]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html
    - shard-lnl:          NOTRUN -> [SKIP][119] ([Intel XE#2229])
   [119]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_live_ktest@xe_migrate@xe_validate_ccs_kunit.html

  * igt@xe_mmap@pci-membarrier:
    - shard-lnl:          NOTRUN -> [SKIP][120] ([Intel XE#5100])
   [120]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_mmap@pci-membarrier.html
    - shard-adlp:         NOTRUN -> [SKIP][121] ([Intel XE#5100])
   [121]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_mmap@pci-membarrier.html

  * igt@xe_module_load@force-load:
    - shard-dg2-set2:     NOTRUN -> [SKIP][122] ([Intel XE#378])
   [122]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_module_load@force-load.html

  * igt@xe_oa@invalid-oa-metric-set-id:
    - shard-adlp:         NOTRUN -> [SKIP][123] ([Intel XE#2541] / [Intel XE#3573])
   [123]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_oa@invalid-oa-metric-set-id.html

  * igt@xe_oa@map-oa-buffer:
    - shard-dg2-set2:     NOTRUN -> [SKIP][124] ([Intel XE#2541] / [Intel XE#3573]) +1 other test skip
   [124]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_oa@map-oa-buffer.html

  * igt@xe_pm@s3-basic:
    - shard-lnl:          NOTRUN -> [SKIP][125] ([Intel XE#584])
   [125]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_pm@s3-basic.html

  * igt@xe_pm@s4-basic:
    - shard-adlp:         [PASS][126] -> [ABORT][127] ([Intel XE#1794])
   [126]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-1/igt@xe_pm@s4-basic.html
   [127]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-9/igt@xe_pm@s4-basic.html

  * igt@xe_pm@s4-mocs:
    - shard-lnl:          [PASS][128] -> [ABORT][129] ([Intel XE#1794])
   [128]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-lnl-8/igt@xe_pm@s4-mocs.html
   [129]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-2/igt@xe_pm@s4-mocs.html

  * igt@xe_pmu@gt-frequency:
    - shard-adlp:         NOTRUN -> [ABORT][130] ([Intel XE#5214]) +1 other test abort
   [130]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-6/igt@xe_pmu@gt-frequency.html

  * igt@xe_pxp@display-pxp-fb:
    - shard-dg2-set2:     NOTRUN -> [SKIP][131] ([Intel XE#4733])
   [131]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_pxp@display-pxp-fb.html

  * igt@xe_query@multigpu-query-uc-fw-version-huc:
    - shard-adlp:         NOTRUN -> [SKIP][132] ([Intel XE#944])
   [132]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_query@multigpu-query-uc-fw-version-huc.html
    - shard-lnl:          NOTRUN -> [SKIP][133] ([Intel XE#944])
   [133]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_query@multigpu-query-uc-fw-version-huc.html

  
#### Possible fixes ####

  * igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p:
    - shard-bmg:          [SKIP][134] ([Intel XE#2314] / [Intel XE#2894]) -> [PASS][135]
   [134]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html
   [135]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_bw@connected-linear-tiling-2-displays-2160x1440p.html

  * igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4:
    - shard-dg2-set2:     [INCOMPLETE][136] ([Intel XE#2705] / [Intel XE#4212]) -> [PASS][137] +1 other test pass
   [136]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-436/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html
   [137]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_ccs@random-ccs-data-4-tiled-dg2-rc-ccs-cc@pipe-c-dp-4.html

  * igt@kms_cursor_crc@cursor-offscreen-256x85:
    - shard-dg2-set2:     [SKIP][138] ([Intel XE#4208] / [i915#2575]) -> [PASS][139] +8 other tests pass
   [138]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_cursor_crc@cursor-offscreen-256x85.html
   [139]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_cursor_crc@cursor-offscreen-256x85.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
    - shard-bmg:          [SKIP][140] ([Intel XE#2291]) -> [PASS][141] +1 other test pass
   [140]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
   [141]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html

  * igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3:
    - shard-bmg:          [FAIL][142] ([Intel XE#3321]) -> [PASS][143] +1 other test pass
   [142]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-8/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html
   [143]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-3/igt@kms_flip@2x-flip-vs-expired-vblank@ab-dp2-hdmi-a3.html

  * igt@kms_flip@2x-flip-vs-suspend:
    - shard-dg2-set2:     [INCOMPLETE][144] ([Intel XE#2049] / [Intel XE#2597]) -> [PASS][145]
   [144]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-432/igt@kms_flip@2x-flip-vs-suspend.html
   [145]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@kms_flip@2x-flip-vs-suspend.html

  * igt@kms_flip@2x-modeset-vs-vblank-race:
    - shard-bmg:          [SKIP][146] ([Intel XE#2316]) -> [PASS][147] +1 other test pass
   [146]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_flip@2x-modeset-vs-vblank-race.html
   [147]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_flip@2x-modeset-vs-vblank-race.html

  * igt@kms_flip@flip-vs-suspend@b-hdmi-a1:
    - shard-adlp:         [DMESG-WARN][148] ([Intel XE#2953] / [Intel XE#4173]) -> [PASS][149] +5 other tests pass
   [148]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-4/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html
   [149]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@kms_flip@flip-vs-suspend@b-hdmi-a1.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y:
    - shard-adlp:         [DMESG-FAIL][150] ([Intel XE#4543]) -> [PASS][151]
   [150]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html
   [151]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-b-hdmi-a-1-x-to-y.html

  * igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y:
    - shard-adlp:         [FAIL][152] ([Intel XE#1874]) -> [PASS][153]
   [152]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-3/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html
   [153]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-8/igt@kms_flip_tiling@flip-change-tiling@pipe-c-hdmi-a-1-x-to-y.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render:
    - shard-dg2-set2:     [SKIP][154] ([Intel XE#4208]) -> [PASS][155] +16 other tests pass
   [154]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html
   [155]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
    - shard-dg2-set2:     [SKIP][156] ([Intel XE#2351] / [Intel XE#4208]) -> [PASS][157]
   [156]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html
   [157]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt.html

  * igt@kms_hdr@static-toggle-suspend:
    - shard-bmg:          [SKIP][158] ([Intel XE#1503]) -> [PASS][159]
   [158]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_hdr@static-toggle-suspend.html
   [159]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_hdr@static-toggle-suspend.html

  * igt@kms_plane_multiple@2x-tiling-4:
    - shard-bmg:          [SKIP][160] ([Intel XE#4596]) -> [PASS][161]
   [160]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_plane_multiple@2x-tiling-4.html
   [161]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_plane_multiple@2x-tiling-4.html

  * igt@kms_vrr@cmrr@pipe-a-edp-1:
    - shard-lnl:          [FAIL][162] ([Intel XE#4459]) -> [PASS][163] +1 other test pass
   [162]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-lnl-7/igt@kms_vrr@cmrr@pipe-a-edp-1.html
   [163]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-8/igt@kms_vrr@cmrr@pipe-a-edp-1.html

  * igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind:
    - shard-dg2-set2:     [SKIP][164] ([Intel XE#1392]) -> [PASS][165] +3 other tests pass
   [164]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-432/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html
   [165]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-433/igt@xe_exec_basic@multigpu-once-bindexecqueue-rebind.html

  * igt@xe_pm@s4-vm-bind-unbind-all:
    - shard-adlp:         [ABORT][166] ([Intel XE#1794]) -> [PASS][167]
   [166]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-9/igt@xe_pm@s4-vm-bind-unbind-all.html
   [167]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-1/igt@xe_pm@s4-vm-bind-unbind-all.html
    - shard-lnl:          [ABORT][168] ([Intel XE#1794]) -> [PASS][169] +1 other test pass
   [168]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-lnl-2/igt@xe_pm@s4-vm-bind-unbind-all.html
   [169]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-lnl-4/igt@xe_pm@s4-vm-bind-unbind-all.html

  
#### Warnings ####

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180:
    - shard-dg2-set2:     [SKIP][170] ([Intel XE#4208]) -> [SKIP][171] ([Intel XE#1124])
   [170]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html
   [171]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180.html

  * igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs:
    - shard-dg2-set2:     [SKIP][172] ([Intel XE#2351] / [Intel XE#4208]) -> [SKIP][173] ([Intel XE#455] / [Intel XE#787]) +1 other test skip
   [172]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html
   [173]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_ccs@bad-rotation-90-y-tiled-gen12-rc-ccs.html

  * igt@kms_chamelium_hpd@hdmi-hpd-storm-disable:
    - shard-dg2-set2:     [SKIP][174] ([Intel XE#4208] / [i915#2575]) -> [SKIP][175] ([Intel XE#373])
   [174]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html
   [175]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_chamelium_hpd@hdmi-hpd-storm-disable.html

  * igt@kms_content_protection@atomic:
    - shard-bmg:          [SKIP][176] ([Intel XE#2341]) -> [FAIL][177] ([Intel XE#1178])
   [176]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_content_protection@atomic.html
   [177]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_content_protection@atomic.html

  * igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
    - shard-bmg:          [FAIL][178] ([Intel XE#3321]) -> [SKIP][179] ([Intel XE#2316])
   [178]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-2/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
   [179]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html

  * igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling:
    - shard-dg2-set2:     [SKIP][180] ([Intel XE#4208]) -> [SKIP][181] ([Intel XE#455])
   [180]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html
   [181]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_flip_scaled_crc@flip-64bpp-yftile-to-32bpp-yftile-downscaling.html

  * igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt:
    - shard-bmg:          [SKIP][182] ([Intel XE#2311]) -> [SKIP][183] ([Intel XE#2312]) +1 other test skip
   [182]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-2/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html
   [183]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_frontbuffer_tracking@drrs-2p-primscrn-pri-shrfb-draw-blt.html

  * igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render:
    - shard-bmg:          [SKIP][184] ([Intel XE#4141]) -> [SKIP][185] ([Intel XE#2312]) +1 other test skip
   [184]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-2/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html
   [185]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render:
    - shard-bmg:          [SKIP][186] ([Intel XE#2312]) -> [SKIP][187] ([Intel XE#4141]) +2 other tests skip
   [186]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html
   [187]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-render.html

  * igt@kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw:
    - shard-bmg:          [SKIP][188] ([Intel XE#2312]) -> [SKIP][189] ([Intel XE#2311]) +2 other tests skip
   [188]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw.html
   [189]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_frontbuffer_tracking@fbcdrrs-2p-pri-indfb-multidraw.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt:
    - shard-dg2-set2:     [SKIP][190] ([Intel XE#4208]) -> [SKIP][191] ([Intel XE#653]) +1 other test skip
   [190]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html
   [191]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-shrfb-pgflip-blt.html

  * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt:
    - shard-bmg:          [SKIP][192] ([Intel XE#2313]) -> [SKIP][193] ([Intel XE#2312]) +4 other tests skip
   [192]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-2/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html
   [193]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-shrfb-plflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt:
    - shard-dg2-set2:     [SKIP][194] ([Intel XE#2351] / [Intel XE#4208]) -> [SKIP][195] ([Intel XE#653])
   [194]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html
   [195]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_frontbuffer_tracking@psr-1p-primscrn-shrfb-msflip-blt.html

  * igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt:
    - shard-bmg:          [SKIP][196] ([Intel XE#2312]) -> [SKIP][197] ([Intel XE#2313]) +3 other tests skip
   [196]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-bmg-6/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html
   [197]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-bmg-8/igt@kms_frontbuffer_tracking@psr-2p-primscrn-indfb-plflip-blt.html

  * igt@kms_pm_dc@dc6-dpms:
    - shard-dg2-set2:     [SKIP][198] ([Intel XE#2351] / [Intel XE#4208]) -> [SKIP][199] ([Intel XE#908])
   [198]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_pm_dc@dc6-dpms.html
   [199]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_pm_dc@dc6-dpms.html

  * igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf:
    - shard-dg2-set2:     [SKIP][200] ([Intel XE#4208]) -> [SKIP][201] ([Intel XE#1489])
   [200]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html
   [201]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_psr2_sf@fbc-psr2-cursor-plane-move-continuous-exceed-sf.html

  * igt@kms_psr@pr-primary-blt:
    - shard-dg2-set2:     [SKIP][202] ([Intel XE#4208]) -> [SKIP][203] ([Intel XE#2850] / [Intel XE#929])
   [202]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_psr@pr-primary-blt.html
   [203]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_psr@pr-primary-blt.html

  * igt@kms_vrr@max-min:
    - shard-dg2-set2:     [SKIP][204] ([Intel XE#4208] / [i915#2575]) -> [SKIP][205] ([Intel XE#455]) +1 other test skip
   [204]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@kms_vrr@max-min.html
   [205]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@kms_vrr@max-min.html

  * igt@xe_eudebug@basic-vm-bind-extended:
    - shard-dg2-set2:     [SKIP][206] ([Intel XE#4208]) -> [SKIP][207] ([Intel XE#4837])
   [206]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@xe_eudebug@basic-vm-bind-extended.html
   [207]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@xe_eudebug@basic-vm-bind-extended.html

  * igt@xe_exec_fault_mode@twice-bindexecqueue-rebind:
    - shard-dg2-set2:     [SKIP][208] ([Intel XE#4208]) -> [SKIP][209] ([Intel XE#288]) +1 other test skip
   [208]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind.html
   [209]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@xe_exec_fault_mode@twice-bindexecqueue-rebind.html

  * igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-huge-nomemset:
    - shard-dg2-set2:     [SKIP][210] ([Intel XE#4208]) -> [SKIP][211] ([Intel XE#4915]) +14 other tests skip
   [210]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-huge-nomemset.html
   [211]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@xe_exec_system_allocator@threads-many-large-execqueues-mmap-huge-nomemset.html

  * igt@xe_oa@polling:
    - shard-dg2-set2:     [SKIP][212] ([Intel XE#4208]) -> [SKIP][213] ([Intel XE#2541] / [Intel XE#3573])
   [212]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@xe_oa@polling.html
   [213]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@xe_oa@polling.html

  * igt@xe_pmu@engine-activity-load:
    - shard-adlp:         [DMESG-WARN][214] ([Intel XE#5214]) -> [ABORT][215] ([Intel XE#5214]) +2 other tests abort
   [214]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-adlp-1/igt@xe_pmu@engine-activity-load.html
   [215]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-adlp-9/igt@xe_pmu@engine-activity-load.html

  * igt@xe_query@multigpu-query-engines:
    - shard-dg2-set2:     [SKIP][216] ([Intel XE#4208]) -> [SKIP][217] ([Intel XE#944])
   [216]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303/shard-dg2-435/igt@xe_query@multigpu-query-engines.html
   [217]: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/shard-dg2-434/igt@xe_query@multigpu-query-engines.html

  
  [Intel XE#1122]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1122
  [Intel XE#1123]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1123
  [Intel XE#1124]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1124
  [Intel XE#1125]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1125
  [Intel XE#1128]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1128
  [Intel XE#1129]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1129
  [Intel XE#1138]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1138
  [Intel XE#1158]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1158
  [Intel XE#1178]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1178
  [Intel XE#1392]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1392
  [Intel XE#1397]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1397
  [Intel XE#1421]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1421
  [Intel XE#1424]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1424
  [Intel XE#1435]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1435
  [Intel XE#1489]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1489
  [Intel XE#1499]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1499
  [Intel XE#1503]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1503
  [Intel XE#1504]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1504
  [Intel XE#1508]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1508
  [Intel XE#1745]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1745
  [Intel XE#1794]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1794
  [Intel XE#1874]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/1874
  [Intel XE#2049]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2049
  [Intel XE#2191]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2191
  [Intel XE#2229]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2229
  [Intel XE#2244]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2244
  [Intel XE#2291]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2291
  [Intel XE#2311]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2311
  [Intel XE#2312]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2312
  [Intel XE#2313]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2313
  [Intel XE#2314]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2314
  [Intel XE#2316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2316
  [Intel XE#2321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2321
  [Intel XE#2341]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2341
  [Intel XE#2351]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2351
  [Intel XE#2541]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2541
  [Intel XE#2597]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2597
  [Intel XE#261]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/261
  [Intel XE#2652]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2652
  [Intel XE#2705]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2705
  [Intel XE#2763]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2763
  [Intel XE#2850]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2850
  [Intel XE#288]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/288
  [Intel XE#2887]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2887
  [Intel XE#2893]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2893
  [Intel XE#2894]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2894
  [Intel XE#2938]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2938
  [Intel XE#2953]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/2953
  [Intel XE#301]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/301
  [Intel XE#306]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/306
  [Intel XE#308]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/308
  [Intel XE#309]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/309
  [Intel XE#3098]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3098
  [Intel XE#310]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/310
  [Intel XE#316]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/316
  [Intel XE#3321]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3321
  [Intel XE#3414]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3414
  [Intel XE#3573]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3573
  [Intel XE#367]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/367
  [Intel XE#373]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/373
  [Intel XE#378]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/378
  [Intel XE#3904]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/3904
  [Intel XE#4141]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4141
  [Intel XE#4173]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4173
  [Intel XE#4208]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4208
  [Intel XE#4212]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4212
  [Intel XE#4298]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4298
  [Intel XE#4356]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4356
  [Intel XE#4359]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4359
  [Intel XE#4416]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4416
  [Intel XE#4459]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4459
  [Intel XE#4497]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4497
  [Intel XE#4543]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4543
  [Intel XE#455]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/455
  [Intel XE#4596]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4596
  [Intel XE#4608]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4608
  [Intel XE#4733]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4733
  [Intel XE#4837]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4837
  [Intel XE#488]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/488
  [Intel XE#4915]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4915
  [Intel XE#4943]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/4943
  [Intel XE#5020]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5020
  [Intel XE#5100]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5100
  [Intel XE#5176]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5176
  [Intel XE#5214]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/5214
  [Intel XE#584]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/584
  [Intel XE#623]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/623
  [Intel XE#651]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/651
  [Intel XE#653]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/653
  [Intel XE#656]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/656
  [Intel XE#688]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/688
  [Intel XE#787]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/787
  [Intel XE#886]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/886
  [Intel XE#908]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/908
  [Intel XE#929]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/929
  [Intel XE#944]: https://gitlab.freedesktop.org/drm/xe/kernel/issues/944
  [i915#2575]: https://gitlab.freedesktop.org/drm/i915/kernel/-/issues/2575


Build changes
-------------

  * Linux: xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303 -> xe-pw-150157v1

  IGT_8406: 12d7c99650c85e479571b6db2c392408be474c88 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  xe-3238-97cffe7577962cb45e3a66d758f9a7cd2633c303: 97cffe7577962cb45e3a66d758f9a7cd2633c303
  xe-pw-150157v1: 150157v1

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/intel-xe/xe-pw-150157v1/index.html

[-- Attachment #2: Type: text/html, Size: 71825 bytes --]

Re: [PATCH 00/16] drm/i915/display: make all global state opaque

[Imre Deak]

On Thu, Jun 12, 2025 at 03:11:55PM +0300, Jani Nikula wrote:
> Hide all the structs that "derive" from struct intel_global_state inside
> their respective implementation files.

On the patchset:
Reviewed-by: Imre Deak <imre.deak@intel.com>

A nit later about naming of functions.

> Jani Nikula (16):
>   drm/i915/wm: abstract intel_dbuf_pmdemand_needs_update()
>   drm/i915/wm: add more accessors to dbuf state
>   drm/i915/wm: make struct intel_dbuf_state opaque type
>   drm/i915/bw: abstract intel_bw_pmdemand_needs_update()
>   drm/i915/bw: relocate intel_can_enable_sagv() and rename to
>     intel_bw_can_enable_sagv()
>   drm/i915: move icl_sagv_{pre,post}_plane_update() to intel_bw.c
>   drm/i915/bw: abstract intel_bw_qgv_point_peakbw()
>   drm/i915/bw: make struct intel_bw_state opaque
>   drm/i915/cdclk: abstract intel_cdclk_logical()
>   drm/i915/cdclk: abstract intel_cdclk_min_cdclk()
>   drm/i915/cdclk: abstract intel_cdclk_bw_min_cdclk()
>   drm/i915/cdclk: abstract intel_cdclk_pmdemand_needs_update()
>   drm/i915/cdclk: abstract intel_cdclk_force_min_cdclk()
>   drm/i915/cdclk: abstract intel_cdclk_read_hw()
>   drm/i915/cdclk: abstract intel_cdclk_actual() and
>     intel_cdclk_actual_voltage_level()
>   drm/i915/cdclk: make struct intel_cdclk_state opaque
> 
>  drivers/gpu/drm/i915/display/hsw_ips.c        |   2 +-
>  .../gpu/drm/i915/display/intel_atomic_plane.c |   4 +-
>  drivers/gpu/drm/i915/display/intel_audio.c    |   2 +-
>  drivers/gpu/drm/i915/display/intel_bw.c       | 153 ++++++++++++++++--
>  drivers/gpu/drm/i915/display/intel_bw.h       |  53 ++----
>  drivers/gpu/drm/i915/display/intel_cdclk.c    |  93 +++++++++++
>  drivers/gpu/drm/i915/display/intel_cdclk.h    |  50 ++----
>  drivers/gpu/drm/i915/display/intel_display.c  |   2 +-
>  .../drm/i915/display/intel_display_driver.c   |   8 +-
>  drivers/gpu/drm/i915/display/intel_fbc.c      |   2 +-
>  drivers/gpu/drm/i915/display/intel_pmdemand.c |  41 ++---
>  drivers/gpu/drm/i915/display/skl_watermark.c  | 134 +++++++--------
>  drivers/gpu/drm/i915/display/skl_watermark.h  |  33 +---
>  13 files changed, 336 insertions(+), 241 deletions(-)
> 
> -- 
> 2.39.5
>